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| 3.3 V 2.7 Gb/s Limiting Amplifier ADN2890 FEATURES SFP reference design available Input sensitivity: 3 mV p-p 80 ps rise/fall times CML outputs: 700 mV p-p differential Programmable LOS detector: 2 mV to 13 mV Rx signal strength indicator (RSSI): SFF-8472 compliant average power measurement Single-supply operation: 3.3 V Low power dissipation: 130 mW Available in space-saving 3 mm x 3 mm 16-lead LFCSP GENERAL DESCRIPTION The ADN2890 is a high gain, limiting amplifier optimized for use in SONET, Gigabit Ethernet (GbE), and Fibre Channel optical receivers that accept input levels of up to 2.0 V p-p differential and have 3 mV p-p differential input sensitivity. The ADN2890 provides the receiver functions of quantization and loss of signal (LOS) detection. The ADN2890 can easily operate at up to 3.2 Gb/s to support LX4 transceivers. The limiting amplifier also measures average received power based on a direct measurement of the photodiode current with better than 1 dB of accuracy over the entire input range of the receiver. This eliminates the need for external average Rx power detection circuitry in SFF-8472 compliant optical transceivers. The ADN2890 limiting amplifier operates from a single 3.3 V supply, has low power dissipation, and is available in a spacesaving 3 mm x 3 mm 16-lead lead frame chip scale package (LFCSP). APPLICATIONS SFP/SFF/GBIC optical transceivers OC-3/12/48, GbE, Fibre Channel receivers 10GBASE-LX4 transceivers WDM transponders FUNCTIONAL BLOCK DIAGRAM AVCC AVEE DRVCC DRVCC DRVEE ADN2890 50 CF RF PIN 50 OUTP OUTN 50 50 3k PD_VCC PD_CATHODE 04509-0-001 ADN2880 NIN +V VREF LOS RSSI/LOS DETECTOR 10k RSSI_OUT ADuC7020 CAZ1 0.01F CAZ2 THRADJ SQUELCH Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADN2890 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 LIMAMP ....................................................................................... 8 Loss of Signal (LOS) Detector .....................................................8 Received Signal Strength Indicator (RSSI).................................8 Squelch Mode ................................................................................8 Applications Information .................................................................9 PCB Design Guidelines ................................................................9 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADN2890 SPECIFICATIONS VCC = VMIN to VMAX, VEE = 0 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter QUANTIZER DC CHARACTERISTICS Input Voltage Range Input Common Mode Peak-to-Peak Differential Input Range Input Sensitivity Input Offset Voltage Input RMS Noise Input Resistance Input Capacitance QUANTIZER AC CHARACTERISTICS Input Data Rate Small Signal Gain S11 S22 Random Jitter Deterministic Jitter Low Frequency Cutoff Power Supply Rejection LOSS OF SIGNAL DETECTOR (LOS) LOS Assert Level Hysteresis 2.0 2.5 LOS Assert Time LOS De-Assert Time RSSI Input Current Range RSSI Output Accuracy Gain Offset Compliance Voltage POWER SUPPLIES VCC ICC OPERATING TEMPERATURE RANGE CML OUTPUT CHARACTERISTICS Output Impedance Output Voltage Swing Output Rise and Fall Time LOGIC INPUTS (SQUELCH) VIH, Input High Voltage VIL, Input Low Voltage Input Current Min 1.8 2.1 4 3 100 235 50 0.65 2700 57 -10 -10 2.4 13.7 30 1.0 45 0.5 7.0 2.5 12.0 3.0 3.0 4.5 4.5 600 100 Typ Max 2.8 2.7 2.0 Unit V p-p V V p-p mV p-p V V rms pF Mb/s dB dB dB ps rms ps p-p kHz kHz dB mV p-p mV p-p dB dB dB dB ns ns A IIN 20 A IIN > 20 A IRSSI/IPD @ PD_CATHODE Test Conditions/Comments @ PIN or NIN, dc-coupled DC-coupled PIN - NIN, ac-coupled PIN - NIN, BER 1 x 10-10 Single-ended 155 5 19 Differential Differential, f < 2.7 GHz Differential, f < 2.7 GHz Input > 10 mV p-p, OC-48, PRBS 223 - 1 Input > 10 mV p-p, OC-48, PRBS 223 - 1 CAZ = Open CAZ = 0.0 1 F 100 kHz < f < 10 MHz RTHRADJ = 100 k RTHRADJ = 0 OC-3, PRBS 223 - 1, RTHRADJ = 0 OC-3, PRBS 223 - 1, RTHRADJ = 10 k OC-48, PRBS 223 - 1, RTHRADJ = 0 OC-48, PRBS 223 - 1, RTHRADJ = 100 k DC-coupled DC-coupled 4.0 16.0 6.0 7.5 5 1000 15% 10% 1.0 50 VCC - 1.05 3.0 -40 3.3 39 +25 50 700 80 VCC - 0.3 3.6 54 +85 mA/mA nA V V mA C V p-p ps V V nA nA TMIN to TMAX Single-ended Differential 20% to 80% 650 800 100 2.0 0.8 -100 100 Rev. 0 | Page 3 of 12 IINH, VIN = 2.4 V IINL, VIN = 0.4 V ADN2890 Parameter LOGIC OUTPUTS (LOS) VOH, Output High Voltage VOL, Output Low Voltage Min 2.4 0.4 Typ Max Unit V V Test Conditions/Comments Open drain output, 4.7 k - 10 k pull-up resistor to VCC Open drain output, 4.7 k - 10 k pull-up resistor to VCC Rev. 0 | Page 4 of 12 ADN2890 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 s) Junction Temperature Rating 4.2 V VEE - 0.4 V VCC + 0.4 V -65C to +155C -40C to +85C 300C 125C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for 4-layer PCB with exposed paddle soldered to GND. Table 3. Package Type 16-lead 3 mm x 3 mm LFCSP JA 28 Unit C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 12 ADN2890 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PD_CATHODE RSSI_OUT 14 7 16 15 13 12 DRVCC AVCC 1 PIN 2 11 OUTP TOP VIEW NIN 3 (Not To Scale)10 OUTN AVEE 4 9 DRVEE 5 6 8 ADN2890 CAZ1 THRADJ CAZ2 LOS SQUELCH PD_VCC Figure 2. Pin Configuration Note: There is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias. Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad Mnemonic AVCC PIN NIN AVEE THRADJ CAZ1 CAZ2 LOS DRVEE OUTN OUTP DRVCC SQUELCH RSSI_OUT PD_VCC PD_CATHODE Pad I/O Power Input Input Power Input Description Analog Power Differential Data Input Differential Data Input Analog Ground LOS Threshold Adjust Resistor Offset Correction Loop Capacitor Offset Correction Loop Capacitor LOS Detector Output Output Buffer Ground Differential Data Output Differential Data Output Output Buffer Power Disable Outputs Average Current Output Power Input for RSSI Measurement Photodiode Bias Voltage Connect to Ground Output Power Output Output Power Input Output Power Output Power Rev. 0 | Page 6 of 12 04509-0-004 ADN2890 TYPICAL PERFORMANCE CHARACTERISTICS 0.96 0.88 0.80 0.72 RSSI_OUT (mA) VERTICAL SCALE: 100mV/DIV 0.64 0.56 0.48 0.40 0.32 0.24 04509-0-002 0.16 0.08 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RSSI_IN (mA) Figure 3. RSSI Output vs. Average PIN Photodiode Current Figure 6. Eye Diagram at 3.2 Gb/s 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0 10 VERTICAL SCALE: 100mV/DIV LOS TRIP POINT (V) 04509-0-009 100 1k RTH () 10k 100k Figure 4. LOS Trip Point vs. Threshold Adjust Resistor Figure 7. Eye Diagram at 2.488 Gb/s 70 60 50 40 30 20 10 0 100k SUPPLY-NOISE REJECTION (dB) 1M SUPPLY-NOISE FREQUENCY (Hz) 10M Figure 5. Typical PSRR vs. Supply-Noise Frequency 04509-0-010 Rev. 0 | Page 7 of 12 04509-0-021 04509-0-020 ADN2890 THEORY OF OPERATION LIMAMP Input Buffer The limiting amplifier has differential inputs (PIN/NIN), with an internal 50 termination. The ROSA (receive optical subassembly) is typically ac-coupled to the ADN2890 inputs, although dc coupling is possible. An internal offset correction loop requires that a capacitor be connected between the CAZ1 and CAZ2 pins. A 0.01 F capacitor provides a low frequency cutoff of 2 kHz. RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) The ADN2890 has an on-chip RSSI circuit that automatically detects the average received power based on a direct measurement of the PIN photodiode's current. The photodiode bias is supplied by the ADN2890, which allows a very accurate, onchip, average power measurement based on the amount of current supplied to the photodiode. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current. Placing a resistor between the RSSI_OUT pin and GND converts the current to a GND referenced voltage. This function eliminates the need for external RSSI circuitry in SFF-8472 compliant optical receivers. CML Output Buffer The ADN2890 provides CML outputs, OUTP/OUTN. The outputs are internally terminated with 50 to VCC. The outputs can be kept at a static voltage by driving the SQUELCH pin to a logic high. The SQUELCH pin can be driven directly by the LOS pin, which automatically disables the LIMAMP outputs in situations with no data input. SQUELCH MODE Driving the SQUELCH input to a logic high disables the limiting amplifier outputs. The SQUELCH input can be connected to the LOS output to keep the limiting amplifier outputs at a static voltage level anytime the input level to the limiting amplifier drops below the programmed LOS threshold. LOSS OF SIGNAL (LOS) DETECTOR The receiver front-end LOS detector circuit indicates when the input signal level has fallen below the user-adjustable threshold. The threshold is set by a resistor connected between the THRADJ pin and VEE. The ADN2890 LOS circuit has a trip point down to <3.0 mV with >3 dB electrical hysteresis to prevent chatter at the LOS output. The LOS output is an opencollector output that must be pulled up externally with a 4.7 k to 10 k resistor. Rev. 0 | Page 8 of 12 ADN2890 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. greatly enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow. Use of a 10 F electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2890 VCC pins. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 12, which supplies power to the high speed OUTP/OUTN output buffers. Refer to the schematic in Figure 8 for recommended connections. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on Pin 9, which is the ground return for the output buffers. The exposed pad should be connected to the GND plane using filled vias so that solder does not leak through the vias during reflow. Using filled vias under the package VCC C9 PD_CATHODE VCC 0.1F VCC C5 C6 AVCC C1 PIN NIN AVEE 1 2 3 4 5 6 7 8 RSSI_OUT SQUELCH 200 PD_VCC R1 C10 RSSI MEASUREMENT TO ADC VCC C7 12 16 15 14 13 C8 DRVCC OUTP C3 TO HOST BOARD ADN2880 C2 CONNECT EXPOSED PAD TO GND 11 10 9 OUTN C4 DRVEE CAZ1 THRADJ CAZ2 LOS C1-C4, C11: 0.01F X5R/X7R DIELECTRIC, 0201 CASE C5, C7, C9, C10, C12: 0.1F X5R/X7R DIELECTRIC, 0402 CASE C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE R3 4.7k TO 10k ON HOST BOARD C11 C12 R2 VCC Figure 8. Typical ADN2890 Applications Circuit Rev. 0 | Page 9 of 12 04509-0-007 ADN2890 PCB Layout Figure 9 shows a recommended PC board layout. Use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, OUTP and OUTN. It is also necessary for the PIN/NIN input traces to be matched in length, and OUTP/OUTN output traces to be matched in length to avoid skew between the differential traces. C1, C2, C3, and C4 are ac-coupling capacitors in series with the high speed I/O. It is recommended that components be used such that the pad for the capacitor is the same width as the transmission line in order to minimize the mismatch in the 50 transmission line at the capacitor's pads. It is recommended that the transmission lines not change layers through vias, if possible. For supply decoupling, the 1 nF decoupling capacitor should be placed on the same layer as the ADN2890 as close as possible to the VCC pin. The 0.1 F capacitor can be placed on the bottom of the PCB directly underneath the 1 nF decoupling capacitor. All high speed CML outputs are back-terminated on chip with 50 resistors connected between the output pin and VCC. The high speed inputs, PIN and NIN, are internally terminated with 50 to an internal reference voltage. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. Soldering Guidelines for Chip Scale Package The lands on the 16 LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using filled vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. R1, C9, C10 ON BOTTOM TO ROSA DOUBLE-VIAS TO REDUCE INDUCTANCE TO SUPPLY AND GND PLACE C7 ON BOTTOM OF BOARD UNDERNEATH C8 C8 VIAS TO GND NIN C2 C4 OUTN C3 OUTP PLACE C5 ON BOTTOM OF BOARD UNDERNEATH C6 C1 PIN C6 1 EXPOSED PAD 4mm DOUBLE-VIA TO GND TO REDUCE INDUCTANCE 04509-0-008 VIA TO C12, R2 ON BOTTOM C11 VIA TO BOTTOM Figure 9. Recommended ADN2890 PCB Layout Rev. 0 | Page 10 of 12 ADN2890 OUTLINE DIMENSIONS 0.50 0.40 0.30 PIN 1 INDICATOR 16 1 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 0.60 MAX 13 12 BOTTOM VIEW 1.65 1.50 SQ* 1.35 9 8 5 4 0.25 MIN 1.50 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 10. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADN2890ACP ADN2890ACP-RL ADN2890ACP-RL7 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 16-LFCSP 16-LFCSP 16-LFCSP Package Option CP-16-3 CP-16-3 CP-16-3 Branding F02 F02 F02 Rev. 0 | Page 11 of 12 ADN2890 NOTES (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04509-0-5/04(0) Rev. 0 | Page 12 of 12 |
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