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| STD45NF75 N-CHANNEL 75V - 0.018 -40A DPAK STripFETTM II POWER MOSFET TYPE STD45NF75 VDSS 75 V RDS(on) <0.024 ID 40 A(**) TYPICAL RDS(on) = 0.018 100% AVALANCHE TESTED GATE CHARGE MINIMIZED SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4") 3 1 DPAK TO-252 (Suffix "T4") DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS HIGH CURRENT, SWITCHING APPLICATIONS INTERNAL SCHEMATIC DIAGRAM Ordering Information SALES TYPE STD45NF75T4 MARKING D45NF75 PACKAGE DPAK PACKAGING TAPE & REEL ABSOLUTE MAXIMUM RATINGS Symbol Parameter Drain-source Voltage (VGS = 0) VDS VDGR Drain-gate Voltage (RGS = 20 k) VGS Gate- source Voltage ID(**) Drain Current (continuous) at TC = 25C ID Drain Current (continuous) at TC = 100C IDM(*) Drain Current (pulsed) Ptot Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope dv/dt (1) Single Pulse Avalanche Energy EAS (2) Tstg Storage Temperature Tj Operating Junction Temperature (*) Pulse width limited by safe operating area. (**) Current Limited by Package Value 75 75 20 40 30 160 100 0.67 20 500 -55 to 175 Unit V V V A A A W W/C V/ns mJ C (1) ISD 40A, di/dt 800A/s, VDD V(BR)DSS, Tj TJMAX (2) Starting Tj = 25 oC, ID = 20 A, VDD = 40V April 2004 1/12 STD45NF75 THERMAL DATA Rthj-case Rthj-pcb Tl Thermal Resistance Junction-case Thermal Resistance Junction-pcb Maximum Lead Temperature For Soldering Purpose (for 10 sec. 1.6 mm from case) Max Max 1.5 see curve on page 6 275 C/W C/W C ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A VGS = 0 Min. 75 1 10 100 Typ. Max. Unit V A A nA VDS = Max Rating VDS = Max Rating TC = 125C VGS = 20 V IGSS ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V ID = 250 A ID = 20 A Min. 2 0.018 Typ. Max. 4 0.024 Unit V DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 25 V ID = 20 A Min. Typ. 50 1760 360 140 Max. Unit S pF pF pF VDS = 25V, f = 1 MHz, VGS = 0 2/12 STD45NF75 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 37 V ID = 20 A VGS = 10 V RG = 4.7 (Resistive Load, Figure 3) VDD=60 V ID=40A VGS= 10V Min. Typ. 15 40 60 13 23 Max. Unit ns ns 80 (see test circuit, Figure 4) nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 37 V ID = 20 A VGS = 10 V RG = 4.7, (Resistive Load, Figure 3) Min. Typ. 55 12 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A VGS = 0 120 410 7.5 Test Conditions Min. Typ. Max. 40 160 1.5 Unit A A V ns nC A ISD = 40 A di/dt = 100A/s Tj = 150C VDD = 30 V (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/12 STD45NF75 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/12 STD45NF75 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. Power Derating vs Tc . Max Id Current vs Tc. . 5/12 STD45NF75 Thermal Resistance Rthj-a vs PCB Copper Area Max Power Dissipation vs PCB Copper Area Allowable Iav vs. Time in Avalanche The previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5 * (1.3 * BVDSS * IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche To derate above 25 oC, at fixed IAV, the following equation must be applied: IAV = 2 * (Tjmax - TCASE)/ (1.3 * BVDSS * Zth) Where: Zth = K * Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV . 6/12 STD45NF75 SPICE THERMAL MODEL Parameter CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERM5 CTHERM6 Node 7-6 6-5 5-4 4-3 3-2 2-1 Value 6 * 10-4 8 * 10-3 2 * 10-2 6 * 10-2 9.65 * 10-2 6 * 10-1 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 7-6 6-5 5-4 4-3 3-2 2-1 0.045 0.105 0.150 0.225 0.375 0.600 7/12 STD45NF75 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 3.1: Switching Time Waveform Fig. 4: Gate Charge Test Circuit Fig. 4.1: Gate Charge Test Waveform 8/12 STD45NF75 Fig. 5: Diode Switching Test Circuit Fig. 5.1: Diode Recovery Times Waveform 9/12 STD45NF75 TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 10/12 STD45NF75 11/12 STD45NF75 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 12/12 |
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