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| PRELIMINARY DATA SHEET MICRONAS VSP 94x5B, VSP 94x7B OPTIMUS Color Decoder and Scan-Rate Converter Version Cx Edition Nov. 28, 2002 6251-576-3PD MICRONAS VSP 94x5B, VSP 94x7B Contents Page 5 6 8 10 10 10 10 11 13 14 15 15 15 15 16 16 16 16 17 17 18 19 20 20 21 21 22 23 23 23 23 23 24 24 24 24 25 25 26 26 27 28 29 30 30 30 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.2.1. 2.3.2.2. 2.3.2.3. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 2.3.12. 2.3.13. 2.3.13.1. 2.3.13.2. 2.3.13.3. 2.3.14. 2.3.15. 2.3.16. 2.3.17. 2.3.18. 2.3.18.1. 2.3.18.2. 2.3.18.3. 2.3.19. 2.3.20. 2.3.21. 2.3.22. 2.3.23. 2.3.24. 2.3.25. 2.3.26. 2.3.27. 2.4. 2.4.1. 2.4.2. Title Introduction Feature Overview Block Diagram Functional Description General Description Chip Architecture Data Acquisition Double CVBS Frontend Analog CVBS and Y/C Inputs Signal Magnitudes and Gain Control Clamping Double Frontend Adjustments CVBS Frontend Synchronization Color Decoder IF-Compensation Chrominance Filter Automatic Standard Recognition Color Saturation Control Color Killer Luminance Processing Adaptive Comb-filter Analog RGB/YUV Inputs Source Select Signal Magnitudes and Gain Control Clamping RGB-Frontend Digital Prefiltering RGB/YPbPr to YCrCb Matrix Component YCrCb Control Soft Mix Static Switch Mode Static Mixer Mode Dynamic Mixer Mode Fast Blank Activity and Overflow Detection Digital 656-Input/-Output Data-Slicer Indication of New Data Closed Caption Violence Protection Widescreen Signalling (625 lines WSS) Widescreen Signalling (525 lines WSS) Channel Mux Input Processing Mosaic Mode Generator Horizontal Prescaler PRELIMINARY DATA SHEET 2 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Contents, continued Page 31 31 32 32 33 34 34 36 36 38 38 38 39 39 40 45 45 47 49 50 51 52 52 52 52 54 56 57 57 59 60 60 61 61 62 62 62 63 63 64 64 64 64 65 65 65 Section 2.4.3. 2.4.4. 2.4.5. 2.4.6. 2.4.7. 2.4.7.1. 2.4.8. 2.4.9. 2.4.10. 2.5. 2.5.1. 2.5.1.1. 2.5.2. 2.5.2.1. 2.5.3. 2.5.4. 2.5.5. 2.5.6. 2.5.7. 2.5.8. 2.5.8.1. 2.5.8.2. 2.5.8.3. 2.5.8.4. 2.5.8.5. 2.5.8.6. 2.5.8.7. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.6.4.1. 2.6.4.2. 2.6.4.3. 2.6.5. 2.6.6. 2.6.7. 2.6.8. 2.6.9. 2.6.9.1. 2.6.9.2. 2.6.9.3. 2.6.10. 2.6.11. 2.6.12. Title Vertical Prescaler Filmmode Detection Motion Detection for Scan-Rate Conversion Global Motion and Global Still Detection Letterbox Detection Visualization of Letterbox Results Preframe Generator Noise Measurement Noise Reduction Output Processing Vertical Postscaler Vertical Panorama Mode Horizontal Postscaler Horizontal Panorama Mode Application Modes Write/Read Positioning Multi-Picture Display PiP Processing Basic Upconversion Concept General Upconversion Parameters Motion Phase (MotPh) and Motion Sequence (MotSeq) Line Scan Pattern (Lsp) and Line Scan Pattern Sequence (LspSeq) Interpolation Type Values (IpolType) SoftBlend Enable Switch (SoftBlendEna) Filmmode Handling Dynamic Operation Table (DynOpTable) Inverse 3-2 Pull Down Display Processing Digital Contrast Improvement (DCI) Adaptive Peaking Color Transition Improvement (CTI) Pixel Mixer Priority Decoder Background and Testpattern Component Window Generator Coarse and Fine Delay YCrCb Control for Digital Output RGB Matrix Oversampling and DAC Output-Data Controller HOUT Generator VOUT Generator BLANK Generator Static Pin Switching VSPB in PiP Operation Only Digital 656 Output Micronas Nov. 28, 2002; 6251-576-3PD 3 VSP 94x5B, VSP 94x7B Contents, continued Page 65 66 67 68 68 68 69 70 71 71 72 90 100 100 145 167 209 209 210 210 215 220 222 222 223 225 225 228 230 233 234 Section 2.6.13. 2.7. 2.7.1. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. 3.9. 3.9.1. 3.9.2. 3.9.3. 4. 4.1. 4.2. 4.2.1. 4.2.2. 4.3. 4.4. 4.4.1. 4.4.2. 4.4.3. 4.4.3.1. 4.4.3.2. 5. 5.1. 6. Title Digital YUV/RGB Output Clock Concept Line-locked Clock Generator IC Bus IC Bus Slave Address IC Bus Format Modification of IC Write Registers Update of IC Read Registers Miscellaneous Important Hints IC Bus List in Alphabetical Order IC Command Table IC Command Description Master Channel Slave Channel Common PRELIMINARY DATA SHEET Specifications Outline Dimensions Pin Connections and Short Descriptions for VSPB Common Pin Connection and Short Descriptions Differing Pin Connections and Short Descriptions for VSP 941xB and VSP 944xB Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics General Characteristics IC Bus Characteristics Application Circuit Application Overview Data Sheet History 4 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B channel only. VSP 94x5B supports two channels, including PiP, double-window etc. The VSP 942xB versions come in a MQFP144 package, whereas all other versions come in a MQFP80 package, pin compatible to other VSP 94xx devices (e.g. VSP 94x2A). The VSP 943xB and VSP 944xB come without scan-rateconverter and a single-scan (50i/60i) signal is output. Table 1-1 and Table 1-2 give an overview of the VSPB single-chip family. Color Decoder and Scan-Rate Converter Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the VSP 94x5B/VSP 94x7B version Cx. 1. Introduction The VSPB family supports 15/32 kHz systems and is available with different options. VSP 94xxB has one Table 1-1: Optimus family for double-scan application Type VSP 9405B VSP 9415B VSP 9425B VSP 9407B VSP 9417B VSP 9427B Package MQFP80 MQFP80 MQFP144 MQFP80 MQFP80 MQFP144 PiP Digital Input ITU6561) ITU656 ITU656 ITU6561) ITU656 ITU656 Analog Input 7xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 9xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 9xCVBS/YC, 2xRGB/YUV to DDP 3315C Digital Output DS6561),2) DS656 ITU601, DS656, RGB/YUV(27bit) DS6561) DS656 ITU601, DS656, RGB/YUV(27bit) Analog Output 1xYUV/RGB, 3xCVBS 3xCVBS 1xYUV/RGB, 3xCVBS 1xYUV/RGB, 3xCVBS 3xCVBS 1xYUV/RGB, 3xCVBS 1) Input and output can not be used at same time (pin sharing) 2) DS656 is an ITU656 like, double-scan interface for connection Table 1-2: Optimus family for single-scan applications Type VSP 9435B VSP 9445B VSP 9437B VSP 9447B VSP 9425B2) VSP 9427B2) 1) 2) Package MQFP80 MQFP80 MQFP80 MQFP80 MQFP144 MQFP144 PiP Digital Input ITU6561) ITU656 Analog Input 7xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 7xCVBS/YC, 2xRGB/YUV 9xCVBS/YC, 2xRGB/YUV 9xCVBS/YC, 2xRGB/YUV Digital Output ITU6561) ITU656 ITU6561) ITU656 ITU601, DS656, RGB/YUV(27bit) ITU601, DS656, RGB/YUV(27bit) Analog Output 1xYUV/RGB, 3xCVBS 3xCVBS 1xYUV/RGB, 3xCVBS 3xCVBS 1xYUV/RGB, 3xCVBS 1xYUV/RGB, 3xCVBS ITU6561) ITU656 ITU656 ITU656 Input and output can not be used at same time (pin sharing) VSP 9425B and 9427B can be used in single-or double-scan applications. Micronas Nov. 28, 2002; 6251-576-3PD 5 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Table 1-3: Compatibility and suited backend ICs Hardware Compatible1) VSP 9402A, VSP 9432A VSP 9405B, VSP 9435B VSP 9407B, VSP 9437B VSP 9412A, VSP 9442A VSP 9415B, VSP 9445B VSP 9417B, VSP 9447B VSP 9425B VSP 9427B 1) DDP 3315C (no ITU656 input possible) SDA 9380 With some restrictions. Please refer to pin description and/or respective application note 1.1. Feature Overview - Different application modes * FSM: Frame based high performance master with PiP * SSC: Split screen ("Double Window") * MUP: Multi pictures, several still and 2 live pictures possible * PC: PC signal in combination with TV signal (TV in PC or PC in TV) - Data acquisition connectivity * Up to seven (VSP 9425B/9427B: nine) CVBS inputs, up to two Y/C inputs * Up to three CVBS outputs (even when Y/C input) * ITU-R 656 compatible digital input * RGB/FBL or YUV or YUV-H-V input * 9 bit amplitude resolution for CVBS/Y/C A/D converter * 8 bit amplitude resolution for RGB/FBL A/D converter - Multi-standard color decoder with 4H comb-filter * PAL/NTSC/SECAM including all substandard * Automatic recognition of chroma standard * AGC (Automatic Gain Control) - Second multi-standard color decoder for slave channel (VSP 94x7B only) - Processing of two input channels independently: Master and slave channel - Temporal noise reduction for master and slave channel * Field or frame based temporal noise reduction for luminance and chrominance - Pre-scaling of the 1fH signal (master and slave channel) * Horizontal scaling factors: 3/2...1...1/28 * Vertical scaling factors: 1...1/30 - Horizontal and vertical scaling of the 2fH signal (master and slave channel) * Horizontal Scaling factors: 3...0.75 * 5 zone horizontal panorama generator - Vertical scaling of the 2fH signal (master channel) * Vertical scaling factors: 8...0.92 * 5 zone vertical panorama generator - Detection circuits * Global motion and global still detection * Film mode and phase detection (PAL, NTSC; 2-2, 3-2 pull down) * Measurement of the noise level (blanking) * Detection of letter box formats - Embedded memory * On-chip memory controller * Embedded DRAM core for field memory * SRAM for delay lines - Data format 4:2:2 - Data slicer for closed caption ("V-chip") and WSS - Flexible clock and synchronization concept * Horizontal line-locked or free-running mode 6 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B - Sharpness improvement * Digital color transition improvement (DCTI) * Adaptive horizontal and vertical peaking (luminance) * Digital luminance transition improvement (DLTI) * Digital contrast improvement (DCI, master channel only) - (S) VGA support * Synchronization to external (S)VGA source possible * Scaling of VGA picture, including TV picture and VGA display "side-by-side" - Three D/A converters * 9 bit amplitude resolution for YUV, RGB output * (Nominal) 72 MHz clock frequency with two-fold oversampling - Digital output (version dependent) * 4:4:4 YUV or RGB output with 24 or 27 bit * 4:2:2 YUV output with 24 or 27 bit * 2fH-8bit (656 like) digital output * ITU-R 656 compatible digital output - I2C bus control (400 kHz) - 1.8 V 5% and 3.3 V 5% supply voltages - P-MQFP-80 or P-MQFP-144 package - Only one crystal necessary for whole IC and all color standards - Scan-rate-conversion (version dependent) * Motion adaptive frame based 100/120 Hz interlaced scan-rate conversion * Motion adaptive frame based 50/60 Hz progressive scan-rate conversion * Special treatment for film material ("Inverse 3-2 pull down") * Large area and line flicker reduction * Simple progressive modes: AB, AA* * Simple interlaced modes (100/120 Hz): ABAB, AABB, AAAA, BBBB * No scan-rate-conversion modes (50/60 Hz): AB, AA, BB - Signal manipulations * Still field or still frame * Insertion of colored background * 2D and 3D frames for master and slave channel * Snapshot * Windowing * Temporal overblending between master and slave * Vertical chrominance shift for improved VCR picture quality * Mosaic-mode generator * Test pattern generator * Demo mode * Contrast, brightness and saturation control Micronas Nov. 28, 2002; 6251-576-3PD 7 data buffer data buffer 8 h50/ irq siscen xout 122 123 51 39 32 cvbso1 xin 33 35 91 cvbso2 cvbso3 Reset vin/ intr clkout vout hout v50/ blank 111 110 109 40 29 6 dgout8 dgout7 dgout6 dgout5 dgout4 648 MHz clk cvbs1 (20.25, 40.5 MHz) 216 MHz clk line-locked 8 7 96 GAIN clamping signals to ADCs clamped, filterd sync signal from master decoder C800 Controller Divider Output Sync Controller xtal Oscillator Free-running Clocks cvbs2 Sync 9 AGC generator 97 ADC1 LL-PLL (36, 72 MHz) 21 CVBS/Y 4H delay H V 648 MHz DTO Divider Line-locked Clocks cvbs3 98 Notch, Deskew, delay cvbs4 Delay Control (PAL/SECAM) 100 GAIN Comb Filter 22 ADC2 YUV CVBS/C 1.2. Block Diagram cvbs5 102 Source Select Input Mux Color Decoder dgout3 23 cvbs6 1H Delay 104 dgout2 24 cvbs7 106 dgout1 25 cvbs8 AGC generator 94 cvbs9 Sync Memory Controller Noise Measure ment H V 95 clamping signals to ADCs Picture Noise Measure ment dgout0 CLAMP Delay Control (PAL/SECAM) Notch, Deskew, Delay Output Data Controller 114 dbout8 115 dbout7 116 Color Decoder YUV 1H Delay YUV YUV Master Output dbout6 Motion Adaptive Upconversion 124 Mosaic Mode Global Motion Detection HPrescaler VPrescaler Temporal Noise Reduction Preframe Generator dbout5 125 VSP 94x5B, VSP 94x7B dbout4 126 Fig. 1-1: Block diagram (MQFP144 package) Letterbox Detection Line Memories Channel Mux Motion Detection YUV Data Slicer dbout3 127 eDRAM dbout2 128 dbout1 132 rin1 YUV Slave Output main YUV insert 70 GAIN ADCR Mosaic Mode HPrescaler VPrescaler Temporal Noise Reduction Preframe Generator Pre Processing Y Noise Measure ment Line Memories Filmmode Detection dbout0 RGB gin1 72 43 drout8 PiPEngine 44 YUV bin1 Soft-mix 73 GAIN ADCG Pre Processing or bypass U Down Sampling drout7 45 fbl1 67 Contrast 2 drout6 46 rin2 78 Source Select GAIN Brightness ADCB Pre Processing Saturation V 4:4:4 drout5 47 Nov. 28, 2002; 6251-576-3PD to 656io 4:2:2 4:4:4 gin2 80 4:2:2 ITU656 Encoder CTI LTI Adaptive Peaking drout4 48 bin2 Offset, Gain VPostscaler HPostscaler 82 GAIN F drout3 52 ADCF DCI Antialias, Deskew fbl2 68 CLAMP grey shaded blocks not available in drout2 53 drout1 ITU601 Encoder Pattern Generator GAIN Y DAC Curtain Generator PixelMixer OFFSET GAIN U DAC Frame Generator OFFSET GAIN 143 2 54 656clk 15 656io0 62 OPTIMUS VSP 94x7B VSP 94x5B VPanorama Generator HPanorama Generator drout0 656io1 61 (pinning corresponds to QFP-144 package) ayout 656io2 60 656io3 38 ITU656 Decoder ITU656 Memory out auout 656io4 37 HPanorama Generator YUV-> RGB or bypass Delay Adjust 8:8:8 656io5 31 4:2:2 4:4:4 656io6 30 Test-controller, Memory Bist IC Interface HPostscaler CTI LTI Adaptive Peaking V DAC OFFSET 140 avout 656io7 28 10 16 138 14 18 129 13 34 656hio/ 656vio/ clkf20 blank scl sda tdo tclk tms adr/tdi PRELIMINARY DATA SHEET Micronas cvbso1 xout xin vout hout 23 17 70 27 cvbso2 cvbso3 clkout 18 20 69 Reset vin/ intr h50/ v50/ irq blank 63 62 61 24 14 648 MHz clk Fig. 1-2: Block diagram (MQFP80 package) xtal Oscillator Divider (20.25, 40.5 MHz) 216 MHz clk line-locked YUV YUV Data Slicer Channel Mux Motion Detection YUV Letterbox Detection Line Memories Global Motion Detection Data buffer Data buffer Micronas Free-running Clocks Output Sync Controller Sync AGC generator cvbs1 52 GAIN clamping signals to ADCs clamped, filtered sync signal from master decoder C800 Controller cvbs2 LL-PLL (36, 72 MHz) 53 ADC1 H V 648 MHz DTO Divider Line-locked Clocks CVBS/Y 4H Delay cvbs3 54 Notch, Deskew, delay cvbs4 Delay Control (PAL/SECAM) 55 GAIN Comb Filter ADC2 YUV 1H Delay Picture Noise Measure ment CVBS/C cvbs5 56 Source Select Input Mux Color Decoder cvbs6 57 cvbs7 58 PRELIMINARY DATA SHEET AGC generator clamping signals to ADCs CLAMP Delay Control (PAL/SECAM) Notch, Deskew, Delay Sync Noise Measure ment Memory Controller H V Output Data Controller Color Decoder YUV 1H Delay Master Output Mosaic Mode HPrescaler VPrescaler Temporal Noise Reduction Preframe Generator Motion Adaptive Upconversion 941xB, 944xB only eDRAM 75 i656iclk 76 rin1 YUV Slave Output main insert 39 GAIN Y Noise Measure ment Line Memories Filmmode Detection i656i0 77 ADCR Mosaic Mode HPrescaler VPrescaler Temporal Noise Reduction Preframe Generator Pre Processing gin1 RGB i656i1 PiPEngine 78 40 YUV i656i2 79 bin1 Soft-mix 41 GAIN ADCG Pre Processing or Bypass Down U Sampling YUV i656i3 80 fbl1 37 Contrast 2 rin2 46 Source Select GAIN Brightness i656i4 1 ADCB Pre Processing Saturation V 4:4:4 i656i5 2 gin2 47 4:2:2 to 656io 4:2:2 4:4:4 i656i6 ITU656/ DS656 Encoder 3 Nov. 28, 2002; 6251-576-3PD Offset, Gain VPostscaler HPostscaler bin2 48 GAIN F ADCF DCI Antialias, Deskew i656i7 CTI LTI Adaptive Peaking to 656decoder fbl2 38 CLAMP grey shaded blocks not available in VSP 94x5B VPanorama Generator HPanorama Generator 656clk 9 656io0 32 OPTIMUS VSP 94x7B Pattern Generator 656io1 31 (Pinning corresponds to QFP-80 package) Curtain Generator PixelMixer GAIN Y DAC OFFSET GAIN U DAC Frame Generator OFFSET GAIN 79 2 940xB, 943xB only ayout 656io2 30 656io3 22 ITU656 Decoder ITU656 Memory Output auout 656io4 21 HPanorama Generator YUV-> RGB or Bypass Delay Adjust 8:8:8 656io5 IC Interface 16 4:2:2 4:4:4 656io6 15 Test-controller, Memory bist HPostscaler CTI LTI Adaptive Peaking V DAC OFFSET 76 avout 656io7 13 6 10 74 8 71 7 19 656hio/ 656vio/ clkf20 blank scl sda tclk tms adr/tdi VSP 94x5B, VSP 94x7B 9 VSP 94x5B, VSP 94x7B 2. Functional Description 2.1. General Description The VSP 94xxB (OPTIMUS) is a new component of the Micronas MEGAVISION(R) single-chip-IC family. The VSP 94xxB family comprises all main functions of a digital featurebox in one monolithic IC. The amount of features is splitted up to different levels from mid to high end, always giving highest picture quality. The family is ideally suited to work in conjunction with the deflection processors SDA 9380 or DDP 3315C (dependent on VSP 94xxB version). In combination with the "digital TV decoder" MDE 9500 double-scan iDTV are possible. 50/60 Hz derivatives are also available. The device comprises digital multistandard color decoder for master and slave channel, a RGB interface with fast-blank capability (SCART), scaling units including panorama, embedded DRAM for upconversion, high performance frame based upconversion algorithms, picture improvements, temporal noise reduction as well as A/D and D/A converter. 2.2. Chip Architecture PRELIMINARY DATA SHEET The OPTIMUS contains many blocks which are dedicated to master channel only (e.g. vertical postscaler) which can only be used with master channel. Some blocks are twice implemented (e.g. noise reduction). Some blocks are only once available but can be selected to work in master or slave channel (e.g. dataslicer). VSP 94xxB does not contain dedicated slave blocks. All items mentioned for slave channel in the data sheet are not valid for VSP 94xxB (see Table 2-2 on page 11). All IC bus registers mentioned are printed in bold and italics (e.g. YCDEL). 2.3. Data Acquisition The "Data Acquisition Processing" provides two independent data streams (master and slave) for the input processing. They either come from a CVBS, Y/C, RGB or YUV input or from a CCIR 656 compatible digital input signal. For RGB and YUV, interlace and progressive signals up to XGA can be connected. High resolution PC signals (SVGA, XGA etc.) may only be reproduced with limited picture quality (see Table 2-3 on page 11). Table 2-1: Versions available Version 9405B 9415B 9425B 9435B 9445B 9407B 9417B 9427B 9437B 9447B Scan-rate Conversion 50p/60p/100i/120i 50p/60p/100i/120i 50i/60i/50p/60p/100i/120i 50i/60i 50i/60i 50p/60p/100i/120i 50p/60p/100i/120i 50i/60i/50p/60p/100i/120i 50i/60i 50i/60i Output Format Analog, DS656 DS656 Analog, DS656, digital RGB/YUV Analog, ITU656 ITU656 Analog, DS656 DS656 Analog, DS656, digital RGB/YUV Analog, ITU656 ITU656 PiP PiP PiP PiP PiP PiP Package QFP80 QFP80 QFP144 QFP80 QFP80 QFP80 QFP80 QFP144 QFP80 QFP80 10 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-3: Allowed analog and digital input signals Defined for Master or Slave Input Signals CVBS/Y/C YUV (sync on Y) fH [kHz] 15.6 15.6 31.2 Remark Standard TV (PAL, NTSC, SECAM) DVD (EIA770.1) Progressive DVD (EIA770.2) DVD VGA SVGA XGA Table 2-2: Master/Slave building blocks Function Defined for Master Defined for Slave Color decoder Letterbox Temporal noise reduction Film mode detector Data-slicer Comb-filter CTI/LTI/adaptive peaking Noise measurement (blanking) Noise measurement (picture content) H/V-prescaler H-panorama postscaler V-panorama postscaler Preframe generator Mosaic mode generator Global motion detection Global still detection Digital contrast improvement RGB+CVBS/ RGB+sync RGB+H+V 15.6 31.5 37.9 48.3 Limit values for analog inputs Digital 656 15.6 (Only single-scan possible) 53 2.3.1. Double CVBS Frontend The CVBS and Y/C decoding is done by two CVBSfrontends working in parallel. Normally, the comb-filter is connected to the first frontend, giving the main picture whereas the second frontend generates an uncombed picture for the PiP channel. The input of frontend 1 is selected by COMBUSEM, the input for frontend 2 is selected by COMBUSES (refer to Figure 2-1). As two CVBS-ADC are not sufficient for any combination of input signals, RGB-ADCs can be used as well for CVBS, Y/C conversion. When using these ADCs, the signal must be switched/connected on the PCB accordingly. At least two solutions are possible: - When using Y/C for main channel, PiP channel can be connected to G_ADC. An external device must be used to switch one CVBS output and the G-signal to GIN1. If only one RGB/YUV input is required, one CVBS out can be directly connected to GIN2. - When two Y/C inputs are required, Y1 and Y2 can be connected to CVBSIN4 and CVBSIN6, C1 and C2 can be connected to RIN1 and RIN2 (please refer to "Source Select" on page 20).To make use of the 'Y/C to CVBS adder', C1 and C2 should be additionally connected to CVBSIN5 and CVBSIN7. Micronas Nov. 28, 2002; 6251-576-3PD 11 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET from G_ADC from R_ADC REMDEL1 from B_ADC CVBS_ADC1 9 0 CVBS1/Y1 CVBS/C1 C Y CVBS_ADC2 9 1 CVBS2/Y2 YCSEL REMDEL2 0 1 2 INCOMB from G_ADC 0 1 2 COMBUSE1 YCBYR Color Decoder master (CD1) 9 Y UV 9 adaptive 4H combfilter Ycomb Ccomb C Y Color Decoder slave (CD2) 9 Y UV 9 COMBUSE2 YCBYB from B_ADC from R_ADC from G_ADC from B_ADC INCOMBC from R_ADC Fig. 2-1: Double CVBS frontend Table 2-4: Input signal combinations COMBUSEM 0 Y_CD1 CVBS1 C_CD1 CVBS/C (YCBYR=0) R_ADC (YCBYR=1) 1 CVBS2 CVBS2 (YCBYR=0) B_ADC (YCBYR=1) 21) 3 Ycomb G_ADC Ccomb G_ADC (YCBYR=0) R_ADC (YCBYR=1) COMBUSES 0 Y_CD2 CVBS1 C_CD2 CVBS/C (YCBYB=0) R_ADC (YCBYB=1) 1 CVBS2 CVBS2 (YCBYB=0) B_ADC (YCBYB=1) 22) 3 Ycomb G_ADC Ccomb G_ADC (YCBYB=0) B_ADC (YCBYB=1) 1) 2) When using COMBUSEM=2, BGSHIFTM must be set to 1, otherwise 0. When using COMBUSES=2, BGSHIFTS must be set to 1, otherwise 0 12 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B If CVBSEL1 and CVBSEL2 are switched to the same input, a superimposing of clamping pulses and clamping values occur. This case must be avoided. If it is desired to display one source on both channels, disable ADC2 (CVBSEL2='1111') and distribute output from ADC1 to master and slave CD by COMBUSEM and COMBUSES. Figure 2-3 shows the analog frontend. 0 0 -5 Attenuation [dB] -10 -15 -20 -25 -30 -35 -40 Fsig [MHz] 5 10 15 20 25 30 35 2.3.2. Analog CVBS and Y/C Inputs Source Select The analog CVBS signal can be fed to the inputs CVBS1...7 (or 3x CVBS and 2x Y/C) of VSP 94x7B (amplitude 0.5...1.5 Vpp). In P-MQFP144 package, 9 CVBS inputs (or 5x CVBS and 2x Y/C) are possible and 3 CVBS outputs are available. One signal is selected via CVBSEL1 and fed to first ADC. A second signal is selected via CVBSEL2 and fed to the other ADC. Although every input CVBS1...CVBS9 can handle CVBS/Y or C signals, CVBS4&5 or CVBS6&7 are intended to be used as separate Y/C inputs (YCSEL). After clamping to the back porch (switchable to synctip clamping by CLPSTGY) both signals are AD-converted with an amplitude resolution of 9 bit. The conversion is done using a 20.25 MHz free-running crystal stable clock. Before this the signals are lowpass filtered by antialias filter. Three inputs can be looped back to output CVBSO1-3 (CVBOSEL1, CVBOSEL2, CVBSELO3). A signal addition is performed to output a CVBS signal even when separate Y/C signals are used at input. Inputs that are not used by ADC are roughly clamped to fit in the allowed voltage region. For stand-by operation (power-save mode), A/D and D/A converter can be switched off by STANDBYxxx keeping the sourceselector operational. Fig. 2-2: Default characteristic of analog CVBS/Y/C antialias filter CVBSEL1 CVBSEL2 CVBOSEL1 CVBOSEL2 CVBOSEL3 CVBS 1 CVBS 2 CVBS 3 CVBS 4 / Y1 CVBS 5 / C1 CVBS 6 / Y2 CVBS 7 / C2 C C C C C C C 1 / 11 1 / 11 1 / 11 1 / 11 1 / 11 CVBS 8 CVBS 9 C C MQFP144 only Clamping pulse of ADC_CVBS1 or ADC_CVBS2. Shifting of signal to required input voltage range for CVBSO1..3 Filter Filter Buffer Buffer Buffer ADC_CVBS1 ADC_CVBS2 CVBSO1 CVBSO2 CVBSO3 Fig. 2-3: Input selection Micronas Nov. 28, 2002; 6251-576-3PD 13 VSP 94x5B, VSP 94x7B 2.3.2.1. Signal Magnitudes and Gain Control To adjust to different CVBS input voltages a digitally working automatic gain control is implemented. Input voltages in the range between 0.6 to 1.8 Vpp can be applied to the CVBS inputs. The AGC behavior can be chosen from four possible AGCMD modes (see Table 2-5). When using the sync height, the A/D gain rises or falls depending on the sync-height of the incoming signal. When using overflow detection only, the gain is set to maximum and is reduced whenever an "overflow" occurs. The signal is lowpassed so that chrominance and noise are not used for detection. The threshold can be adjusted by PWTHD. A setting of '11' equals 511 and means an overflow of the ADC. Other settings react for a lower level. The gain only becomes higher when a change of the channel is detected or is manually reset by AGCRES. AGCFRZE holds the current AGC value. With AGCADJ1 and AGCADJ2, both ADCs are gain controlled manually. 1.9 1.8 1.7 1.6 1.5 Conversion Range [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 8 16 24 PRELIMINARY DATA SHEET Gain Control Characteristic 32 40 48 56 64 AGCADJ1, AGCADJ2 (IC) Fig. 2-4: CVBS, Y and C amplitude characteristics Table 2-5: AGC modes AGCMD 00 AGC Operation Mode AGC uses the height of the sync pulse as a reference and additionally reduces amplification when ADC overflows AGC uses the height of the sync pulse as a reference AGC uses only ADC overflows AGC is disabled and the ADC fits to the values given in AGCADJ 01 10 11 511 442 SRY(1V nom.) 144 16 0 upper headroom white CR (1.2V nom.) 511 446 SRC(0.89 V nom.) upper headroom 100% chroma 75% chroma burst 256 black Fig. 2-5: CVBS ADC characteristic burst 64 0 lower headroom 14 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B CD2.The separate clamp-signal for blue ADC is only used when this mode is selected by BLUESEL. 2.3.3. CVBS Frontend The CVBS frontend consists of the color-decoding circuit itself, a sync processing circuit for separating H/V sync out of the CVBS signal, and the luminance processing. Separated H/V syncs are given to pins H50 and V50. In contrast to previous versions of VSP 94xxB, H50 pin can be used to synchronize other ICs (e.g. text controller), if H50SKEW is set to 1. The main task of the luminance processing is to remove the color carrier by means of a notch filter (no comb mode). For PAL and SECAM operation a baseband delay line is used for U and V signals. This can be used as comb filter in NTSC operation (only for chrominance). The RGB input can either be used as an overlay for the CVBS channel (RGB+FBL) or as a full master channel (RGB+H/V, RGsyncB). The overlay is done by means of a soft-mix and can be used e.g. for "SCART" connector. This block contains a matrix (for RGB signals) which is switched off for YUV (e.g. YsyncPbPr) input signals. A CBS (contrast, brightness, saturation) control makes the input signal adjustable. 2.3.4. Synchronization After elimination of the high frequency components of the CVBS signal by a low pass filter, horizontal and vertical sync pulses are separated. Horizontal sync pulses are generated by a digital phase locked loop. The time constant can be adjusted between fast and slow behavior in four steps (PLLTC) to accommode different input sources (e.g. VCR). The time-constant can be changed during normal operation without visible picture degradation. Additionally weak input signals from a satellite dish ("fish") become more stable when SATNR is enabled. Vertical sync pulses are separated by integration of equalizing pulses. A vertical flywheel mode improves vertical sync separation for weak signals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs may be gated by to reject invalid v-syncs, separately adjustable for 50 Hz (VTHRL50, VTHRH50) and 60 Hz (VTHRL60, VTHRH60) signals. If no input signal is connected the device switches to a free-running mode. The device can be configured to switch-on background color when no or only a weak signal is applied (NOSIGB). 50 Hz or 60 Hz operation for sync separation may be forced separately (e.g NTSC only chassis) or selected to work automatically (FLNSTRD). 2.3.2.2. Clamping The clamp timing for the analog inputs is generated from its corresponding CVBS/sync signal. Clamping can be suppressed for some lines by CLMPLOW and CLMPHIGH to ignore copyprotection information. Both color-decoder generate two sets of clamping signals each (signals 1 and signals 2). Signals 1 are intended to be used for CVBS ADCs, signals 2 are intended to be used for RGBF ADCs. The start and length of each signal is adjustable. For adjustment, please refer to application note. 2.3.2.3. Double Frontend Adjustments CVBS and RGBF ADCs receive gain and clamping signals from the color decoder. For flexibility reasons, these can be selected according to the following figures: CLMPSIG1 to CVBS ADC1 0 1 2 3 CLMPSIG2 AGCADJ2M AGC CD1 AGC CD2 AGCADJ1M to CVBS ADC2 AGCADJ1S AGCADJ2S Fig. 2-6: Selection of cvbs gain control CLMPSIG1 to CVBS ADC1 0 1 2 3 CLMPSIG2 to RGBF ADC SELSM to Blue ADC BLUETWO CD1: Clamp-Signals 1 CD1: Clamp-Signals 2 CD2: Clamp-Signals 1 CD2: Clamp-Signals 2 to CVBS ADC2 Fig. 2-7: Selection of clamp signals For normal conditions, CLMPSIG1=0 and CLMPSIG2=2 allow to select "signals1" from master and slave color-decoder. To connect CVBS ADC1 with CD2 and CVBS ADC2 with CD1, use CLMPSIG1=2 and CLMPSIG2=0. For "Chrominance on Blue", the clamping for this ADC must be selected separately (BLUETWO), dependent on whether Y is on CD1 or Micronas Nov. 28, 2002; 6251-576-3PD 15 VSP 94x5B, VSP 94x7B The center frequency of the frontend PLL can be adjusted in a range up to 52 kHz with FHFRRN. PRELIMINARY DATA SHEET 2.3.7. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell filter characteristic. For SECAM mode, the de-emphasis filter can be adjusted by DEEMPFIR and DEEMPIIR. The bell filter can be adjusted by BELLFIR and BELLIIR. A wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. S-VHS signal or when comb-filter is enabled. The chroma bandwidth can be adjusted by CHRF. The value of CHRF has no linear dependency on effective bandwidth. The proper constellations are shown in Figure 2-8. 20250kHz f = ---------------------------------------------384 + 4 FHFRRN 2.3.5. Color Decoder The digital multistandard chroma decoder is able to decode NTSC and PAL signals with a subcarrier frequency of 3.58 MHz and 4.43 MHz (PAL B1)/M/N/602), NTSC M/44) as well as SECAM signals with automatic standard detection. Alternatively a standard can be forced. The demodulation is done with a regenerated color-carrier. For use of non-standard crystals or factory adjustment, the frequency of the free-running regenerated subcarrier can be adjusted between 270 ppm via SCADJ. For this purpose the crystal deviation (SCDEV) can be read out via IC after chroma PLL locking (indicated by SCOUTEN) and can be stored in C ROM for SCADJ. For test purposes, CPLLOF allows a loop opening of the chroma PLL. The delay between Y and C is well aligned and can also be adjusted in steps of 50ns (YCDEL). No picture shifting occurs when switching between different color standards (e.g. SECAM PAL). A delayline is implemented for PAL and SECAM signals. It acts as a simple chrominance comb-filter for NTSC and can be disabled by COMB. This improves the vertical chroma resolution, but cross-color remains. 2.3.6. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Five different settings (IFCOMP) of the IF-compensation are possible: - Flat (no compensation) - 6 dB/octave - 12 dB/octave - 4.4 MHz prefiltering (with or without prefiltering) 5 0 5 Damping (dB) 10 15 20 25 30 35 40 0 0.5 Chroma filter CHRF=9 CHRF=57 CHRF=12 CHRF=14 2.5 3 3.5 4 CHRF=8 1 1.5 2 Frequency (MHz) Fig. 2-8: Chroma filter characteristics 2.3.8. Automatic Standard Recognition For adjustment to the specific operational area an automatic norm detection is selectable. Available 50 Hz color standards are PAL B, PAL N and SECAM. Available 60 Hz color standards are NTSC M, PAL M, PAL60 and NTSC44. For each line standard, one or more color standards can be chosen for automatic standard detection. In addition, a standard can be forced as well. Within each line standard, the standard is detected by consequently switching from one to another. This standard detection process can be set to slow or fast behavior (LOCKSP). In slow behavior, 25 fields are used to detect the standard, whereas 15 fields are used in fast behavior. If unsuccessful within this time period the system tries to detect another standard. AMSTD50 selects whether PAL B or SECAM is tried first in the automatic routine. AMSTD60 selects whether NTSC44/PAL60 or NTSC M is tried first. Both bits can also be set for automatic detection, then the last detected chroma standard will be used. For SECAM detection, a choice between different recognition levels is possible (SCMIDL, SCMREL) and the evaluated burst position is selectable (BGPOS). 1 PAL B is representative for PAL B/G/H/I/N 2 PAL60 and NTSC44 are nonstandard signals which are generated by some VCR or DVD player Color standard (STDET), line standard (LNSTDRD) and color killer status (CKSTAT) can be read out. 16 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.3.9. Color Saturation Control In the PAL/NTSC system the burst is the reference for the color signal. An Automatic Chroma Control (ACC) produces a stable output for input chroma variations from (approximately) -30 dB to +6 dB compared to nominal burst value. The ACC reference value is programmable for NTSC and PAL independently (NTSCREF, PALREF) to ensure correct color saturation. With ACCFIX, the ACC is disabled and a constant value (dependent on NTSCREF and PALREF) is used instead. ACCFRZ holds the current ACC value. The maximum amplification of the ACC can be limited by ACCLIM. This results in a smooth attenuation of color intensity for weak color carrier (see Fig. 2-9). Table 2-6: Allowed combinations for 60 Hz standards Standard (60 Hz) None PAL60 PAL M NTSC M NTSC44 Automatic PAL M/NTSC M Automatic NTSC M/NTSC44/PAL60 CSTAND D6 0 0 0 0 1 0 1 D5 0 0 0 1 0 1 1 D4 0 0 1 0 0 1 0 D3 0 1 0 0 0 0 0(!) U,V +0dB U,V CONS CON +0dB Table 2-7: Allowed combinations for 50 Hz standards color off +6dB -4dB color off Standard (50 Hz) None PAL N PAL B SECAM Automatic PAL B/SECAM CSTAND D2 0 0 0 1 1 D1 0 0 1 0 1 D0 0 1 0 0 0 CKILL ACCLIM attenuation of color-carrier +6dB -4dB attenuation of color-carrier CKILLS PAL, NTSC operation SECAM operation Fig. 2-9: Color killer adjustment 2.3.10. Color Killer If the chrominance signal is below an adjustable threshold (CKILL (PAL; NTSC) or CKILLS (SECAM)) the color is switched off. To prevent on/off switching, a hysteresis is given by CON or CONS which is the value of switching on the color. COLON switches on the color under any circumstance. The output of the color decoder can be set to UV or CrCb data by CRCB. For NTSC only, the color impression (tint) can be adjusted by the huecontrol between -88 and 90 in steps of 0.7 (HUE). Micronas Nov. 28, 2002; 6251-576-3PD 17 VSP 94x5B, VSP 94x7B 2.3.11. Luminance Processing A luminance notch filter is implemented to reject the chroma information from luminance. Depending on the color standard, one of three different notch characteristics is chosen (PAL, NTSC, SECAM). For PAL and SECAM standards, five different characteristics are available. For NTSC standard, four different characteristics are available. They can be selected by NTCHSEL. Alternatively, when NOTCHOFF is set to 1, notch is disabled or enabled when necessary automatically. TNOTCHOFF disables notch-filter under any circumstance. A simple lowpass-filter can be enabled by LPPOST to further reduce high-frequency noise component from the CVBS signal. For applications for which a black offset is not desired, controlling may be done using LMOFST. The positive or negative offset is added to the Y signal before scaling. The filter characteristics can be found in Fig. 2-10 to Fig. 2-11 and Fig. 2-13 to Fig. 2-14. Table 2-8: Notch-filter NOTCHOFF 0 0 1 1 PRELIMINARY DATA SHEET TNOTCHOFF 0 1 0 1 Notch-filter Always enabled Always disabled Dependent on mode Always disabled Fig. 2-12: Adjustment of Black- to Blankingvalue at analog output 5 5 0 5 attenuation [dB] 10 15 20 25 30 characteristic for SECAM (4.25 MHz) 4.25 characteristic for NTSC NTCHSEL= 3.58 NTCHSEL= 0 'x01' 'x00' 5 attenuation [dB] '100' '000' '001' '010' '011' 'x10' 'x11' 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 frequency [MHz] frequency [MHz] Fig. 2-10: Filter characteristics for NTSC, PAL M and PAL N Fig. 2-13: Filter characteristics for SECAM (SECNTCH='01', 4.25 MHz) 5 0 5 attenuation [dB] 10 15 20 25 30 characteristic for PAL NTCHSEL= '000' '010' attenuation [dB] 4.43 5 0 5 characteristic for Y/C LPPOST=0 LPPOST=1 '100' 10 15 20 '011' '001' 25 30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 frequency [MHz] frequency [MHz] Fig. 2-11: Filter characteristics for PAL B/G, NTSC44 and PAL60 Fig. 2-14: Filter characteristics for Y/C mode 18 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B In order to obtain the best-suited picture quality, the user has the possibility to influence the behavior of the adaption algorithm going from moderate combing to strong combing. Therefore, the following three parameters may be adjusted: - HDG (horizontal difference gain) - VDG (vertical difference gain) - DDR (diagonal dot reducer) HDG typically defines the comb strength on horizontal edges. It determines the amount of the remaining cross-luminance and the sharpness on edges respectively. As HDG increases, the comb strength, e. g. cross luminance reduction and sharpness, increases. VDG typically determines the comb filter behavior on vertical edges. As VDG increases, the comb strength, e. g. the amount of hanging dots, decreases. After selecting the comb-filter performance in horizontal and vertical direction, the diagonal picture performance may further be optimized by adjusting DDR. As DDR increases, the dot crawl on diagonal colored edges is reduced. 2.3.12. Adaptive Comb-filter As only one comb-filter is included, the selection whether master or slave color decoder uses the combfilter is done by SELCOMB. The comb-filter input can be selected by INCOMB. First or second CVBS ADC or green ADC can be used. DISCOMB disables the comb-filter without changing the vertical or horizontal delay. The benefit is, that on/off switching of comb-filter can be done without picture jumping. When setting YCTCOMB, a Y/C signal is fed through line delays without combing, allowing same vertical delay for Y/C signals also. The origin of C signal is given by INCOMBC (refer to Fig. 2-1 on page 12). The comb-filter incorporates a detection circuit, whether standard TV sources or unstable non-standard sources (e.g. VCR) are applied. Although the adaption logic does not allow combing for unstable signals, it is recommended to disable comb-filter by DISCOMB when TVMODE indicates a non-standard signal. The 4H adaptive comb-filter is used for high quality luminance/chrominance separation for PAL or NTSC composite video signals. The comb-filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color. The adaptive algorithm eliminates most of the mentioned errors without introducing new artifacts or noise. The filter uses four line delays to process the information of three video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the digital data is fractionally locked to the color subcarrier. This allows the processing of all color standards and sub-standards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb-filter uses the middle line as reference, therefore, the comb-filter delay is two lines. If the comb-filter is switched off, the delay lines are used to pass the luma/chroma signals from the A/D converters to the luma/chroma outputs. Thus, the processing delay is always two lines. Micronas Nov. 28, 2002; 6251-576-3PD 19 VSP 94x5B, VSP 94x7B 2.3.13. Analog RGB/YUV Inputs 2.3.13.1. Source Select Two RGB/YUV inputs are available. The choice between the first or second input is made by RGBSEL. Additionally, RIN1 and RIN2 (or RIN1 and BIN1 or RIN2 and BIN2) can be used as two separate C inputs for Y/C operation. PRELIMINARY DATA SHEET Table 2-9: RGB input selection RGBSEL BLUESEL R_ADC G_ADC B_ADC 0 0 RIN1 GIN1 BIN1 FIN1 RGB/ YUV input 1 or C 1 0 RIN2 GIN2 BIN2 FIN2 RGB/ YUV input 2 or C 0 1 RIN1 GIN1 RIN2 FIN1 C1 and C2 1 1 RIN1 GIN2 RIN2 FIN2 C1 and C2 0 0 -5 -10 Attenuation [dB] -15 -20 -25 -30 -35 -40 5 10 15 20 25 30 35 40 F_ADC Fsig [MHz] Fig. 2-15: Default characteristic of analog RGB/FBL antialiasfilter 255 229 upper headroom 255 229 upper headroom 80 16 0 255 229 lower headroom 16 0 255 229 lower headroom upper headroom upper headroom 80 16 0 lower headroom 16 0 lower headroom Fig. 2-16: Y/RGBF (w/ or w/o sync) and UV amplitude characteristics 20 CRY = 0.84 Vpp CRY = 1.2 Vpp SRY = 0.7 Vpp SRY = 1 Vpp CRY = 0.84 Vpp CRY = 1.2 Vpp SRY = 0.7 Vpp SRY = 1 Vpp Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.3.13.3. Clamping When using the dynamic softmix-mode with fast-blank, clamping of fast-blank input must be disabled by DCLMPF. The analog clamping value of red and blue input (V and U resp.) can be adjusted by CLMPVRB. The analog clamping value of green input (Y resp.) can be adjusted by CLMPVG. Depending on the input signal format (YUV, RGB, sync signal or not) these bits must be set accordingly. On the digital side, a correction of the analog clamping value must be performed to reconstruct the blacklevel. This is achieved by RBOFST and GOFST. 2.3.13.2. Signal Magnitudes and Gain Control Each ADC can be gain adjusted by AGCADJR, AGCADJG, AGCADJB, AGCADJF. 1.6 1.5 1.4 1.3 Conversion Range [V] 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0 8 16 Gain Control Characteristic 24 32 40 48 56 64 AGCADJR, AGCADJG ,AGCADJB, AGCADJB (IC) Fig. 2-17: RGBF ADC characteristic DC Gain Control Characteristic 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 ADC output=255 conversion range Conversion Range [V] ADC output=0 0 8 16 24 32 40 48 56 64 AGCADJF (IC) Fig. 2-18: Fast-blank ADC characteristic without clamping (DCLMPF=1) Table 2-10: Configurations of input signals Mode YUV, sync on Y YUV, sync on H,V, or CVBS RGB, sync on G RGB, sync on RGB RGB, sync on H,V, or CVBS RGB with fast-blank, synchron to CVBS CLMPVG 80 16 80 80 16 16 CLMPVRB 128 128 16 80 16 16 GOFST 64 0 64 64 0 0 RBOFST 128 128 0 64 0 0 DCLMPF Don't care 0 Don't care Don't care 0 1 Micronas Nov. 28, 2002; 6251-576-3PD 21 VSP 94x5B, VSP 94x7B 2.3.14. RGB-Frontend An analog RGB input port for an external RGB or YUV source is available. The incoming signal is clamped to the back porch by a clamping pulse. As the memory is only able to store a 4:2:2 picture, the YUV input signal is downconverted to 4:2:2 format. There are two operation modes available. The first one uses this input as an overlay input (soft mix). The RGB or YUV signal must then be synchronized to the main CVBS signal. The so called independent mode uses RGB / YUV including sync or H/V signals. This can be used, for PRELIMINARY DATA SHEET example, for a DVD player or set-top-box. When using H sync from a non CVBS input (e.g. separate H-sync) this must be indicated by HINP. The usage of separate V-sync must be set by VINP. With the readable information of number-of-lines (LPFLD), pixel-per-line (NRPIXEL), H and V polarity (DETHPOL, DETVPOL), the applied PC-signals can be distinguished. The delay of luminance and fastblank can be adjusted by YFDEL, and chrominance can be delay adjusted by UVDEL. If necessary, fastblank can be adjusted fine by FBLDEL. Table 2-11: Possible input signals for RGB frontend Input Signal RGB / YUV RGB / YUV RGB RGB YUV 1) FBLIN CVBS1) Ha FBL VIN Sync Separation Sync on CVBS HINP 0 1 0 1 1 VINP 0 1 0 0 0 V Sync on H Synchron to CVBS Sync on G Sync on Y Instead of FBL input, CVBS input can be used from VINP pin from CVBS Source select ADC2 AGCADJ2 Data 2 256 HINP AGCADJ1 AGCMD 0 1 from CVBS Source select ADC1 CLMPV1 CLAMPSIGNALS 1 ADCSEL Sync processing VINP from RGB Source select ADCR AGCADJR CLMPVRB 0 1 DATAR R Processing to soft-mix RBOFFSET CLAMPSIGNALS2 AGCADJG DATAG CLMPVG from RGB Source select ADCG G Processing to soft-mix GOFFSET from RGB Source select ADCB AGCADJB DATAB CLMPVRB B Processing to soft-mix RBOFFSET from RGB Source select ADCF AGCADJF DATAF DCLMPF F Processing to soft-mix Fig. 2-19: Signal and clamping organization 22 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.3.17. Component YCrCb Control The VSP 94xxB supports the following picture adjustment parameters on the component signal: - 0 contrast 63/32 (CONADJ) - -128 brightness 127 (BRTADJ) - 0 saturation Cr 63/32 (VSAT) - 0 saturation Cb 63/32 (USAT) - -45 tint +45 (TINT) 2.3.18. Soft Mix 3 2.3.15. Digital Prefiltering A digital prefiltering can be enabled. This reduces the bandwidth of very steep input signals, such as a display of characters. A band limitation is required, because the succeeding de-skewing filter performs best below 14 MHz. The filtering is performed in all four channels and frequency characteristic can be selected by AASEL. It can be disabled by AABYP. For signal conversion to 4:2:2, an additional chrominance lowpass can be enabled by CHRSF. 10 RGB-prefiltering 0 attenuation [dB] 10 AASEL=0 AASEL=1 The softmixer circuit consists of a Fast Blank (FB) processing block supplying a mixing factor k (0... 128) to a high quality signal mixer achieving the output function: 20 30 40 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] YUV main ( 128 - k ) + YUV inserted k YUVmix = -------------------------------------------------------------------------------------------128 Fig. 2-20: Digital prefiltering of RGB input 2.3.16. RGB/YPbPr to YCrCb Matrix RGB or YPbPr signals are converted to the YCrCb format by a matrix operation (YUVMAT). In case of YCrCb input the matrix is bypassed (YUVSEL). k="0" means that only the main signal is fed through to the output. k="128" means that only the inserted signal becomes visible. The mixing is done once for the luminance and once for the chrominance in the subsampled domain (4:2:2). The softmixer supports four modes that are selected by MIXOP and SMOP. Table 2-12: RGB operation modes Y R 0,299 0,587 0,114 Cb = G - 0,147 - 0,289 0,436 Cr B 0,615 - 0,515 - 0,100 MIXOP 00 SMOP 0 1 x x x Softmix-mode Dynamic Soft-Mix (DECTWO must be set to "1") Static Soft-Mix (DECTWO must be set to "1") Only RGB/YUV path visible Only CVBS path visible (Reserved) Fig. 2-21: RGB to YCrCb matrix (CCIR) 4RGB to YCrCb matrix 00 01 Y Pr 0,191 1 0,075 = Y - 0,108 0 0,991 Cb Cr Pb 0,991 0 - 0,054 10 11 Fig. 2-22: YPbPr to YCrCb matrix (BTA) 2.3.18.1. Static Switch Mode In its simplest and most common application the softmixer is used as a static switch between YUVmain and YUVinsert. This is for instance, the adequate way to handle a DVD component signal. By using MIXOP, k is internally set to 0 or 128 respectively. Y Pr 0,196 1 0,102 Cb = Y - 0,111 0 0,991 Cr Pb 0,988 0 - 0,073 Fig. 2-23: YPbPr to YCrCb matrix (CCIR) Micronas Nov. 28, 2002; 6251-576-3PD 23 VSP 94x5B, VSP 94x7B 2.3.18.2. Static Mixer Mode The signal YUVmain and the component signal YUVinsert may also be statically mixed. In this environment, k is manually controlled via FBLOFFSET and MIXGAIN. PRELIMINARY DATA SHEET For a detailed SCART signal ident analysis by the microcontroller, the fast blank monitor provides additional status information (see Fig. 2-24): - FBSTAT: FB status at register read - FBRISE: set by FB rising edge, reset by register read - FBFALL: set by FB falling edge, reset by register read k = MIXGAIN ( 31 - FBLOFFST ) + 32 All necessary limitation and rounding operations are built-in to fit the range: 0 k 128. Considering MIXGAIN=3, k is obtained by: analog fast blank input FBLSTAT FBLRISE 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 0 k = 158 - 3 FBLOFFST k limited to 0 and 128 FBLFALL FBLACTIVE Fig. 2-24: Fast Blank Monitor The mixing is only controlled by FBLOFFST. In the static mixer mode as well as in the previously mentioned static switch mode, the softmixer operates independently of the analog fast blank input. 2.3.18.3. Dynamic Mixer Mode In the dynamic mixer mode, the mixer is controlled by the Fast Blank signal. The VSP 94xxB provides a linear mixing coefficient. PFBL, PG, PR, PB indicate an overflow of the corresponding ADC (upper limit: ADC=511) exceeding 5 clock cycles duration. 2.3.20. Digital 656-Input/-Output The IC decodes a digital 8bit@27 MHz data stream according to ITU.BT656 standard. Four modes are supported: Table 2-13: 656 modes MIXGAIN ( FB - FBLOFFST 2 ) k = ----------------------------------------------------------------------------------- + 64 2 IMODE 00 656 Operation Full ITU mode (automatic). Information about active picture is taken from data-stream. Full ITU mode (manual). Information about active picture is taken from APPLIPI, NAPPLIPI, ALPFIPI, NALPFIPI. ITU656 only data, H/V-sync according PAL/NTSC. ITU656 only data, H/V-sync according ITU656. The dynamic mode is used for mixing which is dependent on FB input. FB is the preprocessed digitized fastblank input in the range from 0...127. FBL manipulation is done both for luminance and chrominance FBL signal. Fast blank is delay adjustable by FBLDEL in the range of -2...4 clock cycles. 2.3.19. Fast Blank Activity and Overflow Detection It is important to know whether the FBL input is used or not. Therefore a detection circuit gives information via the IC bus to the microcontroller. The circuit uses the digitized FBL as input. If it is greater than a threshold for one or five clock cycles (FBLCONF), the IC bit FBLACTIVE is set. This bit is reset when it is read by the microcontroller. 01 10 11 24 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.3.22. Indication of New Data The sliced and possibly filtered data is available in DATA_USWSS1/DATA_USWSS2/DATAUS_WSS3 (closed-caption and WSS625) and DATA_CCWSS1/ DATACCWSS2 (WSS525). The corresponding status bits are DATAVUSWSS/DATAVCCWSS and SLFIELDUSWSS/SLFIELDCCWSS. When new data were received, DATAVxx becomes "1" and the controller must read DATA_xx1, DATA_xx2 (DATA_xx3) and the status information. After the data bytes were read DATAVxx becomes "0" until new data arrives. It must be ensured that the data polling is activated once per field (16.7 or 20 ms) or every second field (33.3 or 40 ms), depending on the slicer configuration and line standard. The data in DATA_xx is not deleted after reading. If the slicer does not get new data, the old data is still readable in DATA_xx, even if this is not valid any more. The field number of the data in DATAxxx can be found in SLFIELDxx. If one or more XDS-class filter are activated for closed caption, SLFIELDxx contains always "1". Additionally pin h50/irq may flag that new data is received. At default this pin outputs the 50 Hz separated h-sync. It can be configured by IRQCON to output a single short pulse when new data is available or behave equal to DATAV. In the last case the output remains active until the two data registers DATA1/ DATA2 are read. Both modes are useful to avoid continuos polling of the IC bus. The micro-controller then initiates IC transfers only when required. while (1){ i2c_read VSP94xxB_adr, status_reg_adr, status if (status & data_valid_mask) { i2c_read_inc VSP94xxB_adr, data_reg_adr, data1, data2, status process_data data1, data2, status } } To adjust the input to sources, which deviate from the standard, the field information may be inverted (FPOL) and the chrominance format can be chosen between unsigned and 2's complement format (CFORMAT). The polarity of H an V can be inverted by HPOL and VPOL respectively. The port selection (pin 656ioX or i656iX) is done by ITUPRTSEL. 2.3.21. Data-Slicer Two slicer working in parallel are implemented. One can be selected to slice either CC or WSS625, the other is only capable of WSS525. Depending on SERVICE, Closed Caption data ("Line 21") or WSS (Widescreen signalling) is sliced. Sliced data can be read out from IC interface (DATA_CCWSS and DATAUSWSS). The line number of the sliced data is selectable with SLNCW (CC and WSS625) and SLNRUW (WSS525). Therefore WSS and CC can be processed in different regions (e.g. CC with PAL M). The Closed Caption data is assumed to conform with the ITU standards EIA-608 and EIA-744A. WSS data is assumed to conform with ETS 300 294 (2nd edition, May 1996) for 625 lines or IEC61880 for 525 lines standards. SLSRC selects between slicing of master or slave data. Table 2-14: Data slicer configuration IC Commands Configuration each Data Service CC (NTSC) XDSCLS XDSTPE SERVICE SLNCW SLNRUW DATA_CCWSS DATA_USWSS As required As required 0 16 (=line 21) x Data (Not valid) WSS625 (PAL, SECAM) x 0 1 21 (=line 23) x Data (Not valid) WSS525 (NTSC) x 2 1 x 15 (=line 20) (Not valid) Data Fig. 2-25: Example in pseudo-code for reading data Micronas Nov. 28, 2002; 6251-576-3PD 25 VSP 94x5B, VSP 94x7B 2.3.23. Closed Caption The closed caption data stream contains different data services. In field 1 (line 21) the captions CC1 and CC2 and the text pages T1 and T2 are transmitted whereas in field 2 (line 284) caption CC3, CC4, text T3, T4 and the XDS data are transmitted. For more information please refer to the above mentioned standards. Raw CC as well as prefiltered data is provided alternatively. With the built-in programmable XDS-Filter (XDSCLS), the program rating information (V-chip) as well as others can be filtered out. The XDS filter reduce traffic on the IC bus and save calculation power of the main controller. If no class filter is selected, all incoming data (both fields) is sliced and provided by the IC interface. If one or more class filters are chosen, only data in field 2 is sliced. Any combination of class filters is allowed. Each "CLASS" is divided into "TYPES" which can be sorted out by the XDS-secondary filter (XDSTPE). Any combination of type filter is allowed. Some type filter require an appropriate class filter. PRELIMINARY DATA SHEET 2.3.24. Violence Protection The rating information is sent in the program rating packet of the current (sometimes future) class in the XDS data stream. If only this information is desired the corresponding XDS filter (class 01h, type 05h) should be used to suppress other data. The class/packet bytes (0105h) precede the 2 bytes rating information. Each sequence is closed by the end-of-packet byte (0fh) and a checksum. This checksum complements the byte truncated sum of all bytes to 00h. Except comparison of the received rating with the adjusted user rating threshold the micro-controller should check the parity of each byte and validate the checksum to avoid miss-interpretation of wrong received data. The IC offers some alternatives to blocking the master or slave channel completely by switching it off (see Fig. 2-26 on page 26). The Mosaic mode (FRCMMOD) hides details of the picture by reduced sharpness and increased aliasing. The picture looks scrambled and is less perceptible. "Warning Message" THIS PROGRAM CONTAINS VIOLENT SCENES "Blue Screen" "Mosaic" Fig. 2-26: Possibilities of master or slave channel blocking ("warning message" from external OSD controller) 26 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.3.25. Widescreen Signalling (625 lines WSS) In WSS mode (SERVICE="1"), no content filtering is possible. All sliced data is passed to the output registers. In this case XDSTPE selects the field number of the data to be sliced (usually XDSTPE=0 for first field). In Europe WSS (ETS 300 294) carries for instance information about aspect ratio and film-mode. Table 2-15: WSS-625 bit coding (according to ETS 300 294) IIC read D0 Group WSS bit b0 Code Meaning [0001] = Full format 4:3 [1000] = Letterbox 14:9 centre D1 Aspect ratio b1 [b0 b1 b2 b3] b2 [0100] = Letterbox 14:9 top [1101] = Letterbox 16:9 centre [0010] = Letterbox 16:9 top [1011] = Letterbox > 16:9 centre DATA_CCWSS1 (low byte) D2 D3 b3 [0111] = Full format 4:3 (shoot and protect 14:9 centre) [1110] = Full format 16:9 (anamorphic) D4 b4 0 1 Camera mode Film mode Standard PAL Motion adaptive coding No helper Modulated helper (Reserved) D5 Enhanced services D6 b5 0 1 b6 0 1 D7 D0 b7 0 b8 1 No subtitles (Teletext) Subtitles (Teletext) [00] = No open subtitles DATA_CCWSS1 (high byte) D1 Subtitles b9 [01] = Subtitles on active image area [b9 b10] [10] = Subtitles out of image area D2 b10 [11] = (Reserved) 0 No surround sound information Surround sound mode (Reserved) (Reserved) D3 Others D4 D5 D6 (Not defined) D7 b11 1 b12 b13 Micronas Nov. 28, 2002; 6251-576-3PD 27 VSP 94x5B, VSP 94x7B 2.3.26. Widescreen Signalling (525 lines WSS) Processed data can be read out by DATAVUSWSS Table 2-16: WSS-525 bit coding (according to IEC61880) IIC read D0 Word 0 Aspect Ratio D1 DATA_USWSS1 D2 D3 D4 D5 D6 Word 1 Copy Control 2 [11] = (Reserved) 3 4 [b3 b4 b5 b6] 5 6 [1111] no copy control Group WSS bit 1 Code Meaning PRELIMINARY DATA SHEET [00] = 4:3 normal display format [01] = 16:3 normal display format [b1 b2] [10] = 16:9 letter box [0000] copy control information in Word 2 [00] = Copying is permitted without restriction 7 [01] = No used [b7 b8] [10] = One generation of copies may be made D7 8 [11] = No copying is permitted [00] = PSP off D0 Word 2 D1 DATA_CCWSS2 Copy Control 10 [11] = PSP on, 4-line split burst on 0 D2 D3 D4 D5 D6 D7 D0 CRCCC D1 DATA_CCWSS3 D2 D3 D4 D5 Not defined D6 D7 18 19 20 11 1 12 13 14 15 16 17 [b15 b16 b17 b18 b19 b20] CRCC error check (Reserved) Analogue pre-recorded packaged medium Not analogue pre-recorded packaged medium 9 [01] = PSP on, split burst off [b9 b10] [10] = PSP on, 2-line split burst on 28 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B The linelocked display PLL (LL-PLL) is connected to the color decoder input or color decoder output (parallel or serial operation) or to ITU656 input, see Table 2- 17 and Table 2-47 on page 67). Automatic switching to freerun (AUTOFRRN) and automatic switching to colored background (NOSIGB) must be disabled for the channel, which uses ITU656 input. 2.3.27. Channel Mux Any input signal can be connected to master channel and slave channel independently. SELMASTER and SELSLAVE select whether CD1 (colordecoder 1), CD2, 656 decoder of soft-mixed signal is connected to master and slave. If the softmix output is used, SELSM selects between CD1 and CD2 for combination with the RGB input. Which color decoder is used as master can be found in the Table 2-17. Table 2-17: Master input and reference for LL_PLL and automatic freerun ARTSYNC ITUSYNC SELMASTER SELSM Signal on Master Reference for AUTOFRRN and NOSIGBM (LL_PLL operation) 0/1 0/1 0/1 0 0 0 00 01 10 x x 0 1 CD1 CD2 Softmix RGB/CD1 Softmix RGB/CD2 ITU656 CD1 (parallel / serial) CD2 (parallel / serial) CD1 (parallel / serial) CD2 (parallel / serial) set AUTOFRRN=NOSIGBM=0 (ITU656) 1 1 11 x SELMASTER CD1in CD2in 1 0 delay delay 00 01 10 11 MUX Master out SELSM Y Y2RGB RGBin Soft Mix Y C 00 01 10 MUX Slave out 656in 11 SELSLAVE Fig. 2-27: Channelmux Micronas Nov. 28, 2002; 6251-576-3PD 29 VSP 94x5B, VSP 94x7B 2.4. Input Processing PRELIMINARY DATA SHEET 2.4.2. Horizontal Prescaler The main application is the conversion of the data coming from the 40.5/20.25 MHz pixel clock domain down to the number of pixels stored in the memory (factor 2/3). Generally the number of incoming pixels can be decimated by a factor between 1 and 64 in a granularity of 2 output pixels. The horizontal scaler reduces the number of incoming pixels by subsampling. To prevent the introduction of alias distortion low pass filters are used for luminance and chrominance processing controlled by HAAPRESC (bypass, weak, strong and automatic). Fig. 2-30 shows the luminance characteristic. In case of automatic the filter characteristic is calculated in relation to HSCPRESC and HDCPRESC. The horizontal prescaler is controlled by HSCPRESC (fine steps from 1 to 2) and HDCPRESC (integer decimation factors 1, 2, 3, ...). For full-screen display of digital 656 input, the scaler must be bypassed (HSCPRESC=0 and HDCPRESC=0). The start of the horizontal prescaler is defined by the NAPPLIP (Not Active Pixel Per Line Input) register, the amount of pixels is defined by the APPLIP (Active Pixel Per Line Input) register. HSYNC NALPFIP (not active lines input) Complete picture area VSYNC Active picture APPLIP (active pixel per line input) Fig. 2-28: Image format before memory 2.4.1. Mosaic Mode Generator The mosaicmode generator scrambles the displayed picture. The main application is the conversion of the fine input resolution to a very crude output resolution. This may be used in combination with violence protection systems (V-chip) or conditional access systems (pay-per-view). The segmentation of the picture suppresses fine details and thus makes the recognition of the picture content very vague. The input picture is divided into very few segments compared to the large amount of input pixels. The mosaicmode generator is enabled by FRCMMOD. 5 0 5 Attenuation [dB] 10 15 20 25 30 35 40 0 1.25 2.5 Y-decimation filter 3.75 5 Frequency [MHz] 6.25 7.5 8.75 10 Original Mosaic Mode Attenuation (dB) 10 5 0 5 10 15 20 25 30 UV decimation filter 3 Fig. 2-29: Example of scrambled picture 35 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (MHz) Fig. 2-30: Y and C decimation filter characteristic for standard operation (1.5) 30 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B The detected FILMMODE information is a four bit signal. The 4th bit gives a security information about the detected filmmode (means whether the FILMMODE is generated synthetically or is really detected). If it is set to 1, the FILMMODE value is insecure. That means the film mode detector can not recognize a stable mode and the integrated mode generator is switched on. If it is set to 0, the FILMMODE value is secure. That means the film mode detector can find a defined mode. The 3 LSB of the FILMMODE value define the detected mode (see Table 2-18). This FILMMODE value will be used in the frame rate conversion block to switch between different algorithms. Furthermore this value can be read by the IC bus. FMSTATUS indicates new data for FILMMODE. When one of the film mode read registers contains updated data which was not read so far, FMSTATUS is set. FMSTATUS is reset when read. Table 2-18: Filmmode detection results FILMMODE 0000 0001 Description Video mode Film mode PAL, Phase 0 Film mode PAL, Phase 1 Film mode NTSC, Phase 0 Film mode NTSC, Phase 1 Film mode NTSC, Phase 2 Film mode NTSC, Phase 3 Film mode NTSC, Phase 4 Insecure, (3 LSB still show the current detected mode) 2.4.3. Vertical Prescaler The vertical prescaler is controlled by VSCPRESC (fine steps from 1 to 2) and VDCPRESC (integer decimation factors 1, 2, 3, ...). The number of output lines after the scaling process can be controlled with the use of the ALPFIP (active lines per field input) signal. The vertical scaler allows to shift the picture content in vertical direction. The IC register NALPFIP (not active lines per field input) controls the shift in vertical direction. The delay elements needed for integer decimation are shared with the motion detector. In case of active motion detection (MOTON=1), only weak filtering or line-dropping for master channel is possible. An optional prefiltering can be disabled by VAAPRESC. (VAAPRESC enables or disables an anti alias filter by adding a zero in the Y channel). VPKPRESC allows to adjust the amount of vertical peaking. The chrominance may be shifted one line upwards by VCRPRESC. This may give a better picture for VCR sources. Prescaler can be bypassed by VPREBYP to overcome limited capacity of line delays in slave channel (usable for stockticker mode). 2.4.4. Filmmode Detection Image sequences occur at various picture rates. Source material exists in 24p, 25p, 30p, 50i and 60i Hz formats, whereas video is broadcasted at 50 and 60 Hz, respectively. If the content is shot and broadcasted at 50i Hz or 60i Hz, it is called "video mode". If the video is shot at 24p, 25p or 30p Hz and broadcasted as 50i or 60i Hz, it is called "film mode". For video mode and film mode different scan rate conversion algorithms are required. Therefore the information about video mode or film mode is necessary to adapt the processing. The information is provided by the FILMMODE signal. Film mode means, that the signal source was progressive e.g. 25p Hz, which was translated into a e.g. 50i Hz interlaced signal (2-2 pull down). Therefore two consecutive fields called A and B have the same motion phase. Normally field "An" and field "Bn" belong to the same phase. But it is also possible, depending on the translation process, that field "Bn-1" and field "An" belong to the same motion phase (FILMMODE=1 or 2). The translation process is different for 50i or 60i Hz output signals. For 60i Hz the signal looks like: An Bn An Bn+1 An+1 Bn+2 An+2 Bn+2 An+3 Bn+3 etc. This is also called 3-2 pull down. So always three and two fields belong to the same motion phase (FILMMODE=3, 4, 5, 6 or 7). For video mode FILMMODE = 0. Fig. 2-31 and Figure 2-32 on page 32 show the film scanning process for the 2-2 (3-2) pulldown. 0010 0011 0100 0101 0110 0111 1xxx Micronas Nov. 28, 2002; 6251-576-3PD 31 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Original Film Frames 25p Scanned film frames 25p Interlaced video fields 50i Original Film Frames 24p Scanned film frames 24p Interlaced video fields 60i Fa Pa A0a odd lines Fa Pa A0a odd lines odd+even lines B0a even lines odd+even lines B0a even lines Fb Pb A1b odd lines A1a Fb Pb odd lines odd+even lines B1b even lines B1b odd+even lines even lines Fc Pc A2c odd lines A2b odd lines odd+even lines B2c even lines Fc Pc B2c even lines Fd Pd A3d odd lines odd+even lines A3c odd lines odd+even lines B3d even lines B3c Fd Pd even lines Fig. 2-31: Scan process from 25p to 50i (2-2 pulldown) A4d odd+even lines odd lines B4d even lines Fig. 2-32: Scan process from 24p to 60i (3-2 pulldown) 2.4.5. Motion Detection for Scan-Rate Conversion The motion detection calculates a motion value for each pixel. The motion values are stored in the main memory block and used for the scan rate conversion. The motion detection works by comparing different fields of the input signal. 2.4.6. Global Motion and Global Still Detection The result of the global motion detection block are IC readable signals GMOTION and GSTILL. GMOTION (GSTILL) equal zero means, the complete picture is not moving (not still), GMOTION (GSTILL) equal one means, there is motion in the picture or the complete picture is moving (there is a still picture). These values are used internally to switch between different scan rate conversion algorithms. They may additionally be used, to control parameters adaptively per software, e.g. noisereduction. When one of the global motion and still read registers contains updated data which was not read so far, GMDSTATUS is set. GMDSTATUS is reset when read. 32 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B The letter box detection block works only at a data rate of 13.5 MHz. Due to the fact, that the input data rate at channelmux output can be 13.5 MHz, 20.25 MHz or 40.5 MHz, the input signal has to be downsampled. Depending on the IC bus register LBSUB different modes are possible (Downsample 1, 1.5, 3). 2.4.7. Letterbox Detection A drawback of wide screen 16:9 TV sets are the black bars at the left and the right side on the screen, if displaying a 4:3 source on a 16:9 screen with correct aspect ratio. In case of letter box source material, black bars at the top and bottom also exist. With the help of an expansion algorithm it is possible to expand the letter box picture vertically and horizontally in such a way, that the letter box picture will fill the complete screen without loosing information. To do so, the information about the active part of the letter box picture is necessary. Active part means the information about the first active line and the last active line of the letter box picture. The figure below shows the principle of this idea. Hardware (940x) LBSLAA measurement part LBELAA LBFORMAT LBSUBTITLE LBTOPTITLE zooming parameters horizontal and/or vertical Resizing Software controller part Y YUVin YUVout Fig. 2-34: HW/SW partitioning of letterbox detection 4:3 Letterbox Picture HSYNC 2*LBVWSTUP VSYNC 2* LBVWENDUP 2*LBVWSTLO 2* LBVWENDLO 4*LBHWST 4* LBHWEND Expanded Letterbox Picture Fig. 2-35: Measurement windows Fig. 2-33: Handling of letterbox pictures on 16:9 tubes As digital 656input data is already in 13.5 MHz format, no downsampling should be used (LBSUB=0). For CVBS, YUV and RGB signals (if DEC2=1) a downsampling of 1.5 (LBSUB=2) is required. In principle the input picture is separated in one upper and one lower part. The measurement windows are defined by the parameters LBVWSTUP, LBVWENDUP (upper vertical measurement window), LBVWSTLO, LBVWENDLO (lower measurement window) and LBHWST, LBHWEND (horizontal measurement window). Note: A controller software and its description is available upon request. The WSS (Wide Screen Signal) signal contains some information about the picture format (4:3 or 14:9 or 16:9), but not all existing formats are covered and not all signals contain WSS. Therefore, it is necessary a separate algorithm, which delivers the necessary information. The Fig. 2-34 on page 33 shows the concept of the letter box detection algorithm. One part of the algorithm is dedicated hardware and located in the VSP 94x5B, another part is software and located in the RAM of the TV microcontroller. The part located in VSP 94x5B is called measurement part. The measurement part delivers 5 signals to the controller part. Based on the delivered information the controller part calculates an expansion and a vertical pan factor and sends these values back to the VSP 94x5B for manipulation of the video signal. The IC bus parameter LBMASLA can be used to switch between the master and slave channel for the letter box analysis. Micronas Nov. 28, 2002; 6251-576-3PD 33 VSP 94x5B, VSP 94x7B 2.4.7.1. Visualization of Letterbox Results For optimizing of the parameters, it is advantageous to make the decision of the algorithm visible. The figure below shows different possibilities. The visibility can be switched on or off with the IC bus parameter LBVISUON. PRELIMINARY DATA SHEET 2.4.8. Preframe Generator The preframe generator's task is to fill the memory with a colored background before storing of decimated pictures into the memory. The parameter FRC_BGND enables the preframe generator. The color is given by the parameters YBORDER, UBORDER and VBORDER. The preframe generator is able to add up to 30 active pixels with background color at the end of every picture line. The number of pixels to be added is calculated with the use of a "modulo 16 operation" applied to the number of input pixels APPL. Additionally with the parameter MPFBPR (multi picture force background pixels right) up to 3 blocks of 16 colored pixels can be appended to the input picture (or 32 colored pixels if DISPMODEM is "0", "1", "6" or "7". 16 is always valid for slave channel). The parameter MPFBPL (multi picture force background pixels left) with a resolution of 2 pixels allows to overwrite 0...62 pixels of the active picture content from the left of the picture. In vertical direction up to 15 lines can be appended to the active area of the input picture colored with background color. This is controlled via MPFBLB (multi picture force background lines bottom). In vertical direction up to 15 lines of the active area of the input picture can be overwritten with background color. This is controlled via MPFBLT (multi picture force background lines top). Where "0" means that no lines are appended and "15" means that 15 lines are appended with background color. Fig. 2-37 on page 34 gives an overview of the possible adjustments. PANATV PANATV LBSLAA=0 LBFORMAT=0 this is a letter box LBSLAA LBFORMAT=1 this is a letter box LBELAA=0 LBELAA PANATV PANATV LBSLAA TOPTITLE=1 LBFORMAT=1 this is a letter box letter box LBSLAA LBFORMAT=1 LBELAA this is a letter box LBELAA SUBTITLE=1 Fig. 2-36: Visibility of LBX detection parameters APPL MPFBPL MPFBPR=0 MPFBPR=1 MPFBPR=2 MPFBPR=3 MPFBLT ALPF YBORDER UBORDER VBORDER MPFBLB Fig. 2-37: Overview of background settings 34 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Start Condition: Input Data Stream frame in memory APPL mod(APPL,16) Third Step: Overwrite old picture position with Background frame in memory write position APPL Memory Row mod(APPL,16) mod(APPL,32) (decimated) 2*ALPF (decimated) 2*ALPF YBORDER UBORDER VBORDER Memory Column YBORDER UBORDER VBORDER Background Generator YBORDER UBORDER VBORDER Right Border Generator Right Border Generator First Step: Write 1 Frame of Background color frame in memory APPL mod(APPL,16) Fourth Step: Write New Decimated Picture frame in memory write APPL (decimated) position Memory Row Memory Column mod(APPL,16) mod(APPL,32) 2*ALPF (decimated) 2*ALPF YBORDER UBORDER VBORDER YBORDER UBORDER VBORDER Right Border Generator Background Generator Right Border Generator Second Step: Write 4 (6/9/12/16 ...) Decimated Pictures write position Memory Row Fifth Step: Repitition of Step Three and Four write position frame in memory APPL (decimated) mod(APPL,16) mod(APPL,32) frame in memory APPL (decimated) mod(APPL,16) Memory Row 2*ALPF (decimated) Memory Column YBORDER UBORDER VBORDER Right Border Generator 2*ALPF (decimated) Memory Column YBORDER UBORDER VBORDER Right Border Generator Fig. 2-38: Multipicture generation with colored background/frame Micronas Nov. 28, 2002; 6251-576-3PD 35 VSP 94x5B, VSP 94x7B 2.4.9. Noise Measurement As noise reduction algorithms usually decrease the quality of pictures with little noise, it is highly desirable to apply a noise adaptive mechanism, which makes strong corrections in pictures with poor quality, and little corrections in pictures with good quality. To control this mechanism, it is necessary to measure the extent of noise. The noise measurement algorithm can be used to change the parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. This is done by the TV- microcontroller which reads the noise level (NOISEME) and sends different parameter sets to the temporal noise reduction registers of the VSP 94x2A depending on this value (0=no noise, 126=strong noise). Value 127 indicates an overflow status which means that the measurement failed. The value is determined by averaging several fields. The line taken for noise measurement is selected by NMLINE. If NOISEME contains updated data which was not read so far, NMSTATUS is set. NMSTATUS is reset when read. The NMLINE parameter determines the line, which is used in the VSP 94x5B for the measurement. In case NMLINE=0, line 2 of the field A and line 315 of the field B is chosen. In case of NMLINE=3, line 5 of the field A and line 318 of the field B is chosen. The measurement position can be adjusted (NMPOS) as well as the sensitivity (NMSENSE). PRELIMINARY DATA SHEET 2.4.10. Noise Reduction The Fig. 2-39 shows a block diagram of the motion adaptive temporal noise reduction. The structure of the temporal motion adaptive noise reduction is the same for luminance as for chrominance signal. Noise reduction is enabled by NRON. Ydelay_field Ydelay_frame Yin Ydelay_field Ydelay_frame TNRMD4Y TNRABS TNRCLC UVin UVdelay_field UVdelay_frame TNRNR4C TNRSxC TNRSEL Motion Detection C 6 TNRNR4Y Motion Detection Y 6 LUT Y 4 Yin Ky Noise Reduction Y Yout TNRCLY TNRSxY NRON LUT C 4 UVin Kuv Kc Noise Reduction C UVout Fig. 2-39: Temporal noise reduction Depending on the motion in the input signal, the K-factor Ky (Kuv) is adjustable between 0 (no motion) and 15 (motion) by the motion detector. The K-factor for the chrominance filter can be either Ky (output of the luminance motion detector, TNRSEL=0) or Kuv (output of the chrominance motion detector, TNRSEL=1). The delay of the feedback path is a field or frame delay (TNRNR4YM, TNRNR4CM). The motion detector for master channel of luminance and chrominance can be field or frame based (TNRMD4YM). The recursive filtering should be set to the same algorithm (TNRNR4YM, field- or framebased filtering). The chrominance motion detection uses always the delay of the noise reduction (TNRNR4CM). For slave channel, delay of motion detection and noise reduction can not be selected separately for luminance and chrominance. TNRNR4YS selects whether field or frame delay is used. Table 2-19: Allowed combinations for Master NR Y Noise Reduction Field based Field based Frame based Frame based C Noise Reduction Field based TNRMD4YM=1 Frame based Field based TNRMD4YM=0 Frame based TNRNR4YM=0 TNRNR4YM=1 Settings Y C uses C Motion Detection TNRNR4CM=1 / TNRSELM=1 TNRNR4CM=0 / TNRSELM=1 Not available TNRNR4CM=1 / TNRSELM=1 TNRNR4CM=0 / TNRSELM=1 TNRNR4CM=0 / TNRSELM=0 C uses Y Motion Detection TNRNR4CM=1 / TNRSELM=0 36 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-20: Allowed combinations for Slave NR Y Noise Reduction Field based Field based Frame based Frame based C Noise Reduction Field based Frame based Not allowed Field based Frame based TNRNR4YS=0 TNRSELS=1 TNRSELS=0 Settings Y TNRNR4YS=1 C uses C Motion Detection TNRSELS=1 C uses Y Motion Detection TNRSELS=0 The output of the motion detector is weighted using the parameters TNRCLC and TNRCLY. The look-up table input value range is separated into 8 segments. It is possible to define a predefined curve characteristic for each segment. The curve characteristics can be programmed by the parameters TNRYSx for luminance and TNRCSx for chrominance. The curve-start is defined by TNRYSS (TNRCSS) at the end of the last segment. The overall curve is now constructed by connecting the end of segment 6 to the beginning of segment 7 and so on. Negative values of Ky (Kuv) are not possible and clipped to zero. A continuous mapping of 64 motion values to 16 Ky (Kuv) values is the result. TNRSx=0000 TNRSx=0001 TNRSx=0010 TNRSx=0011 TNRSx=0100 TNRSx=0101 TNRSx=0110 TNRSx=0111 TNRSx=1000 segment 4 segment 5 segment 6 segment 7 Ky/Kc segment 0 segment 1 segment 2 segment 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0001 1111 1111 0100 0100 0100 0000 0000 1 0 0 4 8 12 20 28 36 48 TNRSx=1001 TNRSx=1010 TNRSx=1011 TNRSSY, TNRSSC TNRSx=1100 TNRSY , TNRSC 64 motion TNRSx=1101 TNRSx=1110 TNRSx=1111 Fig. 2-40: Predefined curve characteristics for LUT Fig. 2-41: Segments of LUT Micronas Nov. 28, 2002; 6251-576-3PD 37 VSP 94x5B, VSP 94x7B 2.5. Output Processing 2.5.1. Vertical Postscaler The main task of the vertical postscaler is the expansion or decimation of the master channel in vertical direction. That means rational subsampling and upsampling factors. The vertical post scaler is able to operate in progressive scan or interlace mode. The range of the vertical distortion is from 0.5 to 32 in relation to the original vertical picture size. The scaling of the picture is controlled via the value of VSCPOSC. When displaying a progressive picture in interlace format (e.g. 480p 960i) it might be necessary to adjust VOFPOSC to prevent interlace flickering. In case of interlace output, VDOUBLE should be set to 0. VDOUBLE=1 should be used in case of progressive output. Dependent on the operation mode, some restrictions are given for vertical postscaling (picture distortions will occur outside these ranges). Table 2-21: Allowed vertical expansion factors VSCPOSC Vertical Filter Expansion 32 PRELIMINARY DATA SHEET 2.5.1.1. Vertical Panorama Mode For the adjustment of the expansion process, the picture is divided into 5 segments. For each of these segments the increment value for the expansion factor can be defined separately. Each end of a segment can be defined individually. For every segment an increment value can be defined (VINC0...VINC4) which indicates the amount of decimation/expansion. One LSB is equivalent to an offset of 0.125 to VSCPRESC per lines. This means that with VINC, VSCPRESC is altered in the range from -32...31.875 per line. The segments (equal or unequal sizes) are distributed among the number of lines available. The first four segments are defined by (VSEG1...VSEG4). The last one goes from VSEG4 until the end of the picture. 31.875 VINC0 VINC1 VINV2 0 VINC3 VINC4 -32 0 VSEG1 VSEG2 VSEG3 VSEG4 max. output lines Fig. 2-42: Visualization of vertical panorama segments 256 Interlace output (FMODE=0) 8192 8900 256 Progressive output (FMODE=1) Field-jam mode 8192 16383 8192 Table 2-22: Examples of vertical panorama modes 1 0.92 32 1 0.5 1 VSCPOSC VSEG1 VSEG2 VSEG3 VSEG4 VINC0 VINC1 VINC2 VINC3 VINC4 Input Output 288 576i/576p Panorama Lens 240 i 480i/480p Panorama Lens 5200 58 115 173 230 -128 -64 0 64 128 7050 58 115 173 230 128 64 0 -64 -128 48 96 144 192 -128 -64 0 64 128 48 96 144 192 128 64 0 -64 -128 38 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.5.2.1. Horizontal Panorama Mode For an improved impression in the case of expansions of 4:3 pictures to a 16:9 ratio tube, the picture can be geometrically distorted in horizontal direction. It is enabled by HPANON. The idea behind this panorama mode is to keep the middle part of the picture in a 4:3 ratio and to stretch the left and the right to fill the entire width of the 16:9 screen. The picture is divided into 5 segments of selectable size, in order to adjust the expansion process. The increment value for the expansion factor can be defined separately for each of these segments. Each end of a segment can be defined individually in a granularity of two output pixels. For every segment an increment value can be defined (HINC0...HINC4) which indicates the amount of decimation/expansion. One LSB is equivalent to an offset of 0.125 to HSCPRESC per double pixel. This means that with HINC, HSCPRESC is altered in the range from 32...31.875 per double pixel. The first four segments are defined by (HSEG1...HSEG4). The last one goes from HSEG4 to HORWIDTH. Examples are given in Table 2-24 on page 40. 2.5.2. Horizontal Postscaler After the main memory, the display processing is performed using a different clock.The conversion to the display clock is done by an interpolation filter. This can be used for horizontal expansion in the range of 1...4 in steps of 2 pixels (HSCPOSC). Due to increased clock frequency in the backend part, the realized horizontal scaling factor depends on backend clock frequency. 4095 - 27MHzHSCALE = ----------------------- --------------------HSPOSC CLKB36 Usually (36 MHz operation), the horizontal expansion factors result as 0.75...16. This ensures that the factor 0.75 gives no loss of resolution (to show a 4:3 picture on a 16:9 tube). When using DS656 output, neither horizontal compression nor horizontal panorama is possible due to 27 MHz clock. Because of the nonlinear characteristic and integer number of pixel, sometimes different HSCPOSC values result in the same decimation factors. Table 2-23: Horizontal expansion factors INC_VAL HSCPOSC Horizontal Filter Expansion Overall Expansion CLKB36= 27 MHz CLKB36= 36 MHz 31.875 HINC0 HINC1 HINC2 0 HINC3 HINC4 -32 output pixels 256 (minimum) 3072 4095 (maximum) 16 1.33 1 16 1.33 1 12 1 0.75 0 HSEG1 HSEG2 HSEG3 HSEG4 max. Fig. 2-44: Visualization of horizontal panorama segments 3.5 1024 3 Overall Expansion 2.5 2 1.5 1 0.5 Horizontal Postscaler 4095 3 0.75 0 1000 2000 HSCPOSC(IC) 3000 4000 Fig. 2-43: Expansion factor of horizontal postscaler dependent on HSCPOSC Micronas Nov. 28, 2002; 6251-576-3PD 39 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Table 2-24: Examples of horizontal panorama modes Function Panorama Extreme Panorama Lens HSCPOSC HSEG1 HSEG2 HSEG3 HSEG4 HINC0 HINC1 HINC2 HINC3 HINC4 HORWIDTH 2099 96 192 288 384 40 20 0 492 472 960 1023 96 192 288 384 85 43 0 469 427 960 3999 96 192 288 384 472 492 0 20 40 960 Fig. 2-46: Stock-ticker application in FSM mode 2. SSC1 mode (Split-Screen): In split-screen mode, two pictures can be shown side by side. Alternatively, a multi-PiP display with two live sources is possible. Both channels are displayed with field based upconversion algorithms. 3. SSC2 mode (Split-Screen): Same functionality like SSC1 mode. In this case only the memory configuration is different. This enables Joint Line Free Display of 50i and 60i input sources at 50/60p output display frequency. 2.5.3. Application Modes A still field can be displayed using FREEZE command. Dependent on the desired picture arrangement, an appropriate display (or application) mode has to be chosen. One of 9 display modes can be chosen by DISPMODE: 1. FSM mode (Full-Screen-Mode): In Full-screenmode, two independent asynchronous input channels (master and slave channel) are processed. The master channel is displayed with a frame-based upconversion algorithm. The slave channel shows a high resolution PiP. Fig. 2-47: SSC1 mode 4. SPS mode (SnaP-Shot): In snap-shot-mode, a still field can be hidden in the memory. A switch between running picture and still field can be done. This may be used to store a picture (e.g. displayed phone number). This picture can then be shown at any time later. Before snapshot, a frame-based display is possible, after snapshot a field-based display is possible only. The slave channel shows a high resolution PiP. Fig. 2-45: FSM mode By means of PIXPLINS, the slave picture size can be modified to enable stock-ticker mode. In this case, a stock-ticker from one channel is displayed in another channel 5. PCE mode (PC extern mode): In PC extern mode, a PiP is generated, which is synchronized to an external signal. E.g. when a PC or HDTV signal is directly connected to the backend IC, the PiP can be overlaid to this. 40 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 6. PCF mode (PC Full Screen mode): In PC fullscreen mode, a PC signal is shown as master channel. No PiP is available. The display raster is locked to the PC signal or is freerunning to achieve a decoupling between input and display (e.g. to display a XGA signal on a VGA screen). 7. PCP mode (PC + PIP mode): The PC PiP mode is equal to the PCF mode, but the displayed picture size for master is smaller in order to have memory capacity for the slave channel. ML a) SL MS MS MS MS MS MS SL MS ML MS MS f) MS MS MS MS MS MS MS MS MS MS MS MS SS SS b) SS SS SS SS SL SS SS SS ML SL MS MS g) MS ML SS SS MS MS MS ML MS c) MS SL MS MS ML SL h) MS MS MS MS SL d) ML SS SS SS SS SILICON FOR THE SENSES www.micronas.com SS ML SS SS SS SL SS SS SS i) Fig. 2-48: PCE mode 8. MUP1 mode (Multipicture mode 1): MUP1 is the recommended multi-picture mode for most applications. It is possible to show up to 2 live pictures. If interlace output, the master live picture should not be decimated in vertical direction to avoid joint-lines. The slave picture size is limited to 256 pixels x 106 lines and is jointline-free. The display is framebased in master and slave with high resolution. 9. MUP2 mode (Multipicture mode 2): Multi-picture display with up to two live and manifold still pictures. The display is field-based without restriction in picture size. Jointlines in live-pictures are not rejected. The display is only field-based. e) ML SL ML SL SS SS SS SS k) ML= master live // MS= master still // SL= slave live // SS= slave still Fig. 2-49: Some multipicture examples Similar arrangements for 16:9 tubes are possible. Micronas Nov. 28, 2002; 6251-576-3PD 41 VSP 94x5B, VSP 94x7B Table 2-25: Preferred modes for multi-picture examples Picture a b c d e f g h i k Preferred Mode MUP1 SSC1 MUP2 SSC1 SSC1 MUP1 MUP1 MUP1 SSC1 FSM Remark PRELIMINARY DATA SHEET This configuration can be achieved by horizontal expansion of slave picture over whole screen by postscaler. A slightly reduced horizontal resolution in slave channel occurs. Master jointlinefree for progressive output. Jointline visible in master channel, when interlace output Stock-ticker-application with still pictures. INTPROGS must be set to "1" Table 2-26: Display modes: Picture sizes Display Mode Master Channel Stored Fields YC 2 Supplied Fields YC 2 Max. Picture Size [Pixels x Lines] 704 x 288 (PIXPLINM=0) 832 x 240 (PIXPLINM=1) 768 x 288 448 x 292 768 x 288 768 x 288 Not available 2 2 1 2 2 1 768 x 340 (PIXPLINM=2) 864 x 292 (PIXPLINM=0) 768 x 288 448 x 292 3 3 2 2 Stored Fields YC 3 Slave Channel Supplied Fields YC 2 Max.Picture Size [Pixels x Lines] 256 x 106 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) 768 x 34 (PIXPLINS=2) 256 x 106 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) 432 X 292 256 x 106 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) 768 x 288 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) 256 x 106 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) Not available 256 x 106 (PIXPLINS=0) 432 x 60 (PIXPLINS=1) 432 x 292 FSM (0) SPS (1) SSC1 (2) MUP1 (3) MUP2 (4) PCE (5) PCF (6) PCP (7) SSC2 (8) 1 live / 1 shot 2 2 1 1 1 2 1 3 2 3 1 3 2 1 2 1 2 42 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-27: Capabilities of display modes Mode Input Master1) 50i Input Slave 50i 60i PC signal 60i 50i 60i PC signal SSC1 50i 50i 60i PC signal 60i 50i 60i PC signal SSC2 50i 50i 60i PC signal 50i 60i PC signal 60i 50i 60i PC signal 50i 60i PC signal 120i 60p, (60i) 100i 50p, (50i) 120i, 60p, (60i) 100i, 50p, (50i) 120i, 60p, (60i) Output Display2)3)4) 100i, 50p, (50i) MC Jointline Free Strong flickering in slave Master channel is joinlinefree only, if NOT decimated or expanded vertically. Strong flickering in slave SC Jointline Free Comment FSM/SPS/ MUP1 Micronas Nov. 28, 2002; 6251-576-3PD 43 VSP 94x5B, VSP 94x7B Table 2-27: Capabilities of display modes, continued Mode Input Master1) 50i Input Slave 50i 60i PC signal 50i 60i PC signal 60i 50i 60i PC signal 50i 60i PC signal FSM/PCP/ SPS/MUP1/ SSC1 PCF PCE 1) PRELIMINARY DATA SHEET Output Display2)3)4) 50p, (50i) MC Jointline Free SC Jointline Free Comment MUP2 Master channel is joinlinefree only, if NOT decimated or expanded vertically. 100i 60p, (60i) 120i PC signal 50i, 60i Allowed PC standards Allowed PC standards Allowed PC standards PC signal PC signal (not visible) - 50i, 60i Slave channel not available Master channel not visible 50i=625 lines / 50 Hz interlaced (normal PAL), 60i=525 lines / 60 Hz interlaced (normal NTSC) 50p=625 lines / 50 Hz progressive, 60p=525 lines / 60 Hz progressive (e.g. progressive YPbPr from DVD) in brackets belong to single-scan version, 2) Values 3) 4) No single-scan output possible with double-scan input // Please refer to Table 2-33 on page 53 for upconversion details 44 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-28: Application mode capabilities FSM MC SC SPS MC SC SSC MC SC MUP1 MC SC MUP2 MC SC PCE MC SC PCF MC SC PCP MC SC Frame rate conversion Motion adaptive Simple frame based Simple field based Image analysis Motion adaptive temporal noise reduction Field Frame Film mode detector Global motion detector Motion detector Image Scaler DCI V pre-scaler (linear) V post-scaler (nonlinear) 1) 1) Not usable in "Inverse 3-2 pull down" mode 2.5.4. Write/Read Positioning The picture position, where the picture is written into the memory is given by WRPOSX for horizontal and WRPOSY for vertical direction. The accuracy of positioning is one line in vertical direction. The slave can be positioned horizontally in 16 pixel, whereas the master is positioned only in MUP-modes with 16 pixel resolution. All other modes allow only bigger steps. The picture position, where the picture is read out of the memory is given by RDPOSX for horizontal and RDPOSY for vertical direction. The accuracy of reading is one line in vertical direction, whereas in horizontal direction the accuracy is 2 pixel (master) or 32 pixel (slave) 2.5.5. Multi-Picture Display For the programming of a multi picture display it must be considered that the addressing of horizontal positions is restricted to a raster of 16 pixels. Therefore only a few configurations have an exact symmetrical structure. The following figures Fig. 2-50 and Fig. 2- 51 on page 46 show two alternative configurations for 9 x 1/9 and 16 x 1/16 multi picture displays, respectively. The Fig. 2-52 on page 46 deals with the configurations for 24 x 1/24 and 36 x 1/36 multi picture displays. Configurations with other picture sizes or combinations of different picture sizes are also possible, when the mentioned addressing restrictions are considered. Corresponding considerations must be done for 16:9 picture tubes. In Fig. 2-50 on page 46 symmetrical borders on the left and right side are achieved for a border width of 32 pixels when the active line length is enlarged to 720 pixels. Micronas Nov. 28, 2002; 6251-576-3PD 45 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET 0 3 6 48 208 1 4 7 208 720 2 5 8 208 48 0 6 12 18 24 30 32 96 1 7 13 19 25 31 96 2 8 14 20 26 32 96 3 9 15 21 27 33 96 4 10 16 22 28 34 96 5 11 17 23 29 35 96 64 704 0 3 6 64 192 1 4 7 192 704 2 5 8 192 64 01234 56789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 128 128 128 704 128 128 32 Fig. 2-50: Examples of 9 x 1/9 multi picture Fig. 2-52: Example of 25 x 1/25 and 36 x 1/36 multi picture Using 704 active pixels the border width becomes 64 pixels when symmetry is desired. 0 4 8 12 32 160 1 5 9 13 160 704 2 6 10 14 160 3 7 11 15 160 32 0 4 8 12 64 144 1 5 9 13 144 704 2 6 10 14 144 3 7 11 15 144 64 Fig. 2-51: Examples of 16 x 1/16 multi picture 46 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.5.6. PiP Processing The PIP engine performs the upconversion of the slave data path. For a multitude of modes joint line free display is possible. In Table 2-29 and Table 2-30 on page 48) all supported display modes are listed. Table 2-29: Supported interlaced display modes DISPMODE FSM (0) SPS (1) MUP1 (3) PCE (5) PCP (7) SSC2 (8) 100 101 110 111 SSC1 (2) 000/001/010 011 100 101 110 111 MUP2 (4) 000/001/011/101/111 010/100/110 STOPMOS 001 010 011 Display Raster AA*B*B, intra field interpolation AABB, field repetition () AABB, field repetition () X BBBB, field repetition AA*B*B, intra field interpolation AABB, field repetition AAAA, field repetition BBBB, field repetition Displayed Fields ABAB, frame repetition AABB, field repetition AAAA, field repetition Joint Line Free X Micronas Nov. 28, 2002; 6251-576-3PD 47 VSP 94x5B, VSP 94x7B Table 2-30: Supported progressive display modes DISPMODE FSM (0) SPS (1) MUP1 (3) PCE (5) PCP (7) SSC2 (8) 101 110 100 STOPMOS 001 010 011 Display Raster a+b Displayed Fields PRELIMINARY DATA SHEET Joint Line Free X A+B, A+B, frame repetition A+A, B+B, line doubling A+A, A+A, line doubling, field repetition A+A*, A+A*, intra field interpolation, field repetition B+B, B+B, line doubling, field repetition B+B*, B+B*, intra field interpolation, field repetition 111 SSC1 (2) 000/001/010 011 100 A+A*, B*+B, intra field interpolation A+A, B+B, line doubling A+A, A+A, line doubling, field repetition A+A*, A+A*, intra field interpolation, field repetition 101 110 B+B, B+B, line doubling, field repetition B+B*, B+B*, intra field interpolation, field repetition 111 MUP2 (4) X A+A*, B*+B, intra field interpolation A+A B+B, line doubling X 48 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B video mode (two consecutive fields belong not to the same motion phase) or film mode (means two consecutive fields belong to the same motion phase for 2-2 pull down mode or two and three consecutive fields belong to the same motion phase for 3-2 pull down mode. Please refer to "Filmmode Detection" on page 31. The video mode material can be further separated. The separation is based on the motion range of the picture content, which is displayed. For the different source materials optimized scan rate conversion methods exists. Film mode material created by 2-2 pulldown (25p to 50i) is converted to 100i should be displayed in ABAB or BABA mode depending on the film mode phase. 60i film mode sources (3-2 pulldown) normally are converted to 60p whereas the "inverse 32 pulldown" is the best way for creating the progressive output. For the video mode material the optimized scan rate conversion method depends on the picture content. 2.5.7. Basic Upconversion Concept The upconversion creates a temporary progressive output image. This progressive output is used afterwards for vertical scaling. The scaled image now can be interlaced again or remains progressive. The upconversion itself can be divided into three steps. In the first step the decision is made which of the two available motion phases (motion phase from field A or from field B) should be displayed. This process is called motion phase selection. The original lines from the selected field are copied into the progressive output. In a second step the missing lines for the progressive output are created. Several interpolation methods are available. Now, the progressive image is ready to be scaled vertically. After the scaling the decision about the line scan pattern is made. Interlaced outputs or progressive outputs are possible. The scan rate conversion algorithm concept is based on the assumption that the video input signal can be in Local Motion Method Inverse 3-2 pull down Inverse 2-2 pull down Local Motion Method (ABAB/) or (BABA/) pixel based switch by motion detector NTSC Film Mode Local Still Method (ABAB/) PAL Film Mode Local Still Method (ABAB/) Video Mode Local Still Method (ABAB/) field based switch by global still detector IC: GSTILLENA switch by film mode detector IC: FMFORCE Local Motion Method (programmable, e.g. AA*B*B/) IC: DYNOPSMXX field based switch by global motion detector IC: GFBON Global Motion Method (programmable, e.g. AABB/) Global Still Method (programmable, e.g. ABAB/) XX = GM = Global Motion XX = GS = GLOBAL STILL XX = V = VIDEO XX = P0-1 = FILM PAL PHASE 0-1 XX = N0-4 = FILM NTSC PHASE0-4 Fig. 2-53: Upconversion concept Micronas Nov. 28, 2002; 6251-576-3PD 49 VSP 94x5B, VSP 94x7B 2.5.8. General Upconversion Parameters Fig. 2-54 explains the used wording for the following explanations. PRELIMINARY DATA SHEET FRAME/FIELD FRAME FIELD A odd lines The figure below describes the data flow in the VSP 94x5B. The input fields are stored in the internal memory. Maximum two fields (three fields in case of inverse 3-2 pull down) are available for upconversion. The generated output fields belong to four different phases in case of interlaced output or two different phases in case of progressive output, respectively. The delay between the input field and the corresponding output fields depends on the OPDEL parameter. If OPDEL is not set correctly, a static jointline may occur in the picture. Two input fields are used to generate one output field or frame. Therefore first an internal progressive frame is generated. The motion phase of this internal progressive frame is programmed by the parameter DYNOPMSXX (MS - Motion Sequence value, XX is the abbreviation as defined in Fig. 2-52 on page 46). FIELD B even lines Content of picture DISPLAY LINE-SCANNING PATTERN TV odd lines Display linescanning pattern Display linescanning pattern Display linescanning pattern Input fields An Bn Input fields Tube, Display linescanning pattern IpolType Interpolation Type values (DYNOPITXX) SoftMixEnable (DYNOPSMXX) Output field MotSeq Motion Sequence values (DYNOPMSXX) motion phase IpolType Interpolation Type values (DYNOPITXX) SoftMixEnable (DYNOPSMXX) Fig. 2-54: Explanation of field and display linescanning pattern Phase i Phase i Output field A B B The interlaced input signal (e.g. 50 Hz PAL/SECAM or 60 Hz NTSC) is composed of a field A (odd lines) and a field B (even lines). An - Input signal, field A at time n, Bn - Input signal, field B at time n The field information describes the picture content. The output signal, which could contain different picture contents (e.g. field A, field B), can be displayed with the display line-scanning pattern or . Examples: (An, ) - Output signal, field A at time n, displayed as line-scanning pattern , (An, ) - Output signal, field A at time n, displayed as line-scanning pattern , ((A*)n, ) - Output signal, field A raster interpolated into field B at time n, displayed as line- scanning pattern (An Bn-1, +) - Output signal, frame AB at time n, displayed as progressive line-scanning pattern + LspSeq Line Scan Pattern values (DYNOPLSXX) Fig. 2-55: Explanation of output field generation The interpolation of the missing lines for the internal frame can be programmed by the parameters DYNOPITXX and DYNOPSMXX. The first parameter defines the Interpolation Type (e.g. linear filter) and the second enables the Soft Mix method. Soft Mix means using the motion values from the Motion Detector to switch soft between the programmed Interpolation Type mode and the local fall back Interpolation Type Frame display. The Line Scan Pattern of the generated output fields are programmed using the parameter DYNOPLSXX. 50 mau03 even lines Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 100i output: Four motion phases must be generated from two consecutive input field motion phases A and B. For each output field it has to be decided which motion phase (A or B) should be generated. i.e. for a still input the sequence ABAB is a good 100i output. The VSP 94x7B has a full frame memory for the chrominance. It is possible to define a static Motion sequence for chrominance by the parameter StatOpMsC. 2.5.8.1. Motion Phase (MotPh) and Motion Sequence (MotSeq) The input signal usually contains two different fields, an A field with a line scan pattern (Aa) and a B field with b line scan pattern (Bb). The field content (A or B) called motion phase (called MotPh) and the line scan pattern (a or b) are separately handled. E.g. the content of an input Aa field can be displayed as Aa or can be displayed in a b line scan pattern Ab. The formerly coupling of A/a and B/b is now broken. The continuous output signal can be defined as a sequence of motion phases. The worst case is the Table 2-31: MotSeq and LspSeq description (xx is placeholder for the specific dynamic operation case) 100/120 Hz Interlaced 2V/2H Output Phase 0123 Motion Sequence (MotSeq) DYNOPMSxx 0 - MotSeqAAAA 1 - MotSeqBBBB 2 - MotSeqAABB 3 - MotSeqABBA 4 - MotSeqBBAA 5 - MotSeqBAAB 6 - MotSeqABAB 7 - MotSeqBABA Line scan pattern sequence (LspSeq) DYNOPLSxx 0 - LspSeqAAAA 1 - LspSeqBBBB 2 - LspSeqAABB 3 - LspSeqABBA 4 - LspSeqBBAA 5 - LspSeqBAAB 6 - LspSeqABAB 7 - LspSeqBABA AAAA BBBB AABB ABBA BBAA BAAB ABAB BABA 50/60 Hz Progressive 1V/2H 50/60 Hz Interlaced 1V/2H 50/60 Hz Interlaced 1V/1H Phase 02 AA BB AB AB BA BA AA BB (progressive) (progressive) (interlaced) (interlaced) (interlaced) (interlaced) (progressive) (progressive) Micronas Nov. 28, 2002; 6251-576-3PD 51 VSP 94x5B, VSP 94x7B 2.5.8.2. Line Scan Pattern (Lsp) and Line Scan Pattern Sequence (LspSeq) According to the motion phase each output image will be assigned an line scan pattern (Lsp). The combination of 4 line scan patterns is called Line Scan Pattern Sequence (LspSeq). The line scan pattern sequence can be adjusted by a list of parameters including the key word DYNOPLS followed by the sequence. The combination of four motion phases is called Motion Sequence (in the following marked as MotSeq). The motion sequence can be adjusted by a list of parameters including the key word DYNOPMS followed by the indicator of the dynamic operation case (e.g. DYNOPMSGM for the motion sequence for the global motion case). 8 (progressive: 4) different motion sequences are allowed which represent all necessary combinations. 2.5.8.3. Interpolation Type Values (IpolType) If the picture content does not fit to the line scan pattern or in case of de-interlacing (creation of missing lines in the progressive output frame), these picture content or missing lines must be created by interpolation. Four different techniques can be selected by setting the interpolation type value IpolType. The interpolation type can be adjusted by a list of parameters including the key word DYNOPIT followed by the indicator of the dynamic operation case (e.g. DYNOPITP0 for the IpolType for the first 2-2 pulldown case). The different values are described in the following table. Table 2-32: IpolType description DynOpIt 0 - IpolTypeAB Description Frame based de-interlacing using original A and B lines for displaying still sequences Field based de-interlacing using line doubling Field based de-interlacing using linear interpolation Field based de-interlacing using modified line doubling PRELIMINARY DATA SHEET 2.5.8.4. SoftBlend Enable Switch (SoftBlendEna) In still areas of the input fields the upconversion uses the SoftBlend functionality to switch soft and pixelwise the interpolation type from the adjusted IpolType to the IpolTypeAB. The SoftBlend feature can be enabled by the SoftBlendEna switch. If disabled, the selected IpolType is used for the whole picture. The soft blend switch can be adjusted by a list of parameters including the key word DYNOPSM followed by the indicator of the dynamic operation case (e.g. DYNOPSMGS for the SoftBlendEna for the global still case). 2.5.8.5. Filmmode Handling The IC bus read register FILMMODE consists of 4 bits. The 3 LSBs indicate the current film type and phase, the MSB indicates whether the 3 LSBs were generated synthetically inside the film mode detector (phase flywheel mode on unsecure input sources) or if the film mode detection result was securely detected (see chapter 2.4.4. "Filmmode Detection" on page 31 for details). This signal is used as input for the Upconversion-Modified Filmmode Generator (UMF). The generator is controlled by the IC bus FmForce and FmForceTrig signals and has as output a modified filmmode signal. Three general possibilities exist to modify the incoming FILMMODE signal. Please refer to Table 2-33 on page 53). FmForce = 15 disables the UMF and uses the original unmodified FILMMODE signal for further processing. It is also possible to discard the original information and to generate ("force") an artificial filmmode signal. This is helpful for test purposes or when having film type and phase information available from external. Three different film types can be forced: Video mode (formerly called Camera mode), 2-2 pulldown mode (FM PAL) or 3-2 pulldown mode (FM NTSC). Adjusting 2-2 pulldown mode the two film phases AnBn (FmForce = 1) or BnAn+1 (FmForce = 2) can be adjusted. Forcing a mode requires to set FmForceTrig. Switching to FmForce = 3...7, the film phases 0, 1, 2, 3 and 4 are generated cyclically starting with the adjusted FmForce. To change the 3-2 pulldown mode film phase again, FmForce must be changed and at the same time FmForceTrig must be set (and released). A usually used modification restricts the FILMMODE signal to selected film types. It is possible to limit the allowed film types only to Video mode, to 2-2 pulldown mode, or only to 3-2 pulldown mode. A combination of two modes can also be selected. 1 - IpolTypeLineDb1 2 - IpolTypeLin2 4 - IpolTypeLin4 52 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-33: Upconversion modified film mode generator Fm Force 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Allow all modes 15 Use unmodified film mode detector result Allow VIDEO only Allow FM PAL only Allow FM NTSC only Allow VIDEO and FM PAL only Allow VIDEO and FM NTSC only Allow FM PAL and FM NTSC only If secure detection result, synchronize phase, otherwise use internal phase generator Force FM NTSC UMF Output Mode Force VIDEO mode Force FM PAL With phase AnBn With phase BnAn+1 Starting with phase 0 Starting with phase 1 Starting with phase 2 Starting with phase 3 Starting with phase 4 Phase For all modes FmForce = 8...14 the following rules are valid: - Once one of the allowed film types is detected, all excluded film types cannot be reached anymore (until switching to other FmForce values). - If the FILMMODE signal indicates an allowed film type and the detection result is "secure", the original film phase is used. - If the FILMMODE signal indicates any excluded film type, the last detected and allowed film type is hold. - If the FILMMODE signal indicates "unsecure" in any film type, the last detected and allowed film type is hold. - Directly after activating one of the modes FmForce = 8...14 described above, one of the two scenarios can occur: * The current UMF output film type already is one of the allowed film types. In this case the UMF output is transfered seamless to the actual mode. * The current UMF output is one of the film types which are not allowed. Now the original FILMMODE signal is used unmodified, as long as the FILMMODE signal does not indicate one of the allowed film types. To avoid undetermined behavior after switching, it is recommended to use a two step switching approach. First switch to FmForce = 0 to force Video mode (to establish a stable state), then switch to your desired mode (e.g. FmForce = 11). Micronas Nov. 28, 2002; 6251-576-3PD 53 VSP 94x5B, VSP 94x7B 2.5.8.6. Dynamic Operation Table (DynOpTable) The DynOpTable transforms the programmed IC bus parameter into internal signals which determine the current output sequence behavior. The global motion signal GMotion, the global still signal GStill and the modified film mode signal UMF are generated inside the IC. Depending on these input signals the programmed motion sequence MotSeq, the line scan pattern LspSeq, the interpolation type IpolType the soft blend enable switch SBlendEna and the inverse 3-2 pull down position FJPos are selected. The parameter are coded as follows: DYNOPYYXX The description for YY and XX is described in Table 2- 34. For example: DYNOPMSGM means Motion Sequence value for the Global Motion Fall Back Mode. PRELIMINARY DATA SHEET Table 2-34: DYNOPYYXX description YY MS IT SM LS GM GS V P0 P1 N0 N1 N2 N3 N4 XX Description Motion Sequence value Interpolation Type value Soft Blend Enable value Line Scan Pattern value Global Motion Fall Back mode Global Still Fall Back mode Video mode 2-2 pulldown mode (FM PAL) (phase 0) 2-2 pulldown mode (FM PAL) (phase 1) 3-2 pulldown mode (FM NTSC) (phase 0) 3-2 pulldown mode (FM NTSC) (phase 1) 3-2 pulldown mode (FM NTSC) (phase 2) 3-2 pulldown mode (FM NTSC) (phase 3) 3-2 pulldown mode (FM NTSC) (phase 4) 54 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 2-35: Dynamic operation table GMotFlag 1 0 0 0 0 0 0 0 0 0 GStillFlag x 1 0 0 0 0 0 0 0 0 UMF x x 000 001 010 011 100 101 110 111 MotSeq DynOpMsGm DynOpMsGs DynOpMsV DynOpMsP0 DynOpMsP1 DynOpMsN0 DynOpMsN1 DynOpMsN2 DynOpMsN3 DynOpMsN4 IpolType DynOpItGm DynOpItGs DynOpItV DynOpItP0 DynOpItP1 DynOpItN0 DynOpItN1 DynOpItN2 DynOpItN3 DynOpItN4 SBlendEna DynOpSmGm DynOpSmGs DynOpSmV DynOpSmP0 DynOpSmP1 DynOpSmN0 DynOpSmN1 DynOpSmN2 DynOpSmN3 DynOpSmN4 FJPos DynOpFjGm DynOpFjGs DynOpFjV DynOpFjP0 DynOpFjP1 DynOpFjN0 DynOpFjN1 DynOpFjN2 DynOpFjN3 DynOpFjN4 LspSeq DynOpLsGm DynOpLsGs DynOpLsV DynOpLsP0 DynOpLsP1 DynOpLsN DynOpLsN DynOpLsN DynOpLsN DynOpLsN The GMotFlag indicator is the combination of the parameters GFBON and GmFmFbEna and the global motion indicator bit GMOTION (Table 2-36). Table 2-36: GMotFlag combination GMOTION 0 1 1 1 1 GFBON x 0 1 1 1 GmFmFbEna x x 0 0 1 UMF x x 0 1...15 x GMotFlag 0 0 1 0 1 In the same way the GStillFlag is combined. See Table 2-37 for details. Table 2-37: GStillFlag combination GSTILL 0 1 1 1 1 GStillEna x 0 1 1 1 GsFmFbEna x x 0 0 1 UMF x x 0 1...15 x GStillFlag 0 0 1 0 1 Micronas Nov. 28, 2002; 6251-576-3PD 55 VSP 94x5B, VSP 94x7B The parameter GFBON activates the global fall back switch. When activated, the setting for "global motion" is used, if the readable bit GMOTION is set. This is used to switch for example in case of 100 Hz interlaced to AABB in case of big motion in the picture. If activated the GMOTION flag has the highest priority. The second priority has the GSTILL flag, which can be activated with GSTILLENA. This can be used for example in case of 100 Hz interlaced to switch to ABAB mode in case of a complete still picture. The last priority has the UMF flag, which selects between the detected mode camera or the different film phases. By using GmFmFbEna and GsFmFbEna, the decision for film-mode can be priorized. In this case, the fall back processing is disabled. PRELIMINARY DATA SHEET 2.5.8.7. Inverse 3-2 Pull Down For progressive output sequence with single V frequency a special mode for displaying film mode sources without interpolation and in frame resolution can be used. This mode is called inverse 3-2 pull down mode. To enable this feature some restrictions are valid. - Vertical expansion or decimation can not be used. For special exceptions, please refer to applicationnote. - Vertical locked mode must be used. - Horizontal locked mode must be used and LL-PLL must be in locked condition (STABLL=1). The inverse 3-2 pull down mode can be activated by the IC bus register FJMode. The motion sequence (MotSeq), the line scan pattern (LspSeq), the interpolation type value (IpolType), the softmix enable switch (SoftMixEna), and the inverse 32 pull down position switch (FJPos) must be programmed by IC bus in the dynamic operation table (DynOpTable). 2.6. Display Processing The display processing part contains an integrated triple 9-bit DAC and performs digital enhancements and manipulations of the digital video component signal. Fig. 2-56 shows the block diagram of the display processing part. 2.6.1. Digital Contrast Improvement (DCI) There is a strong demand on picture contrast, but each video display has a limited dynamic range. Especially the flat display panels like LCD and PDP (plasma display panel) have a lower dynamic range compared to CRT. The picture contrast can't be increased by simply increasing the video signal amplitude, because exceeding the display dynamic range causes unwanted effects. An efficient use of display dynamic range depending on the picture contents increases picture contrast and quality. The basic function of DCI is to analyze the picture framewise and adjust the parameters of a dual segment transfer function depending on the analysis results for the best subjective picture quality. Therefore, each image frame is analyzed for three different characteristics. The image average brightness, the dark sample distribution, and the frame peak value. These parameters control the transfer function. The dual segment transfer function consists of two segments with an adaptive pivot point. A lower segment for dark samples and an upper segment for light 56 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B imum value in order to avoid unnatural effects. DCION enables or disables DCI function. When modifying the contrast of the picture (luminance), a chrominance compensation is also performed, in order to avoid wrong color saturation. This feature may be disabled by CSCON. Independent from the actual display region, image analysis is done within a user-defined window. It is defined by start pixel (SPIXEL), end pixel (EPIXEL), start line (SLINE) and end line (ELINE). samples. The gain of the lower segment is adaptive to the dark sample distribution. A higher gain results from fewer dark samples and a lower gain from a higher number of dark samples. The gain is limited in the range as given below. The gain of the upper segment is adaptive to the frame peak value. It is computed in the way that the detected peak value lower than the nominal, will be moved to nominal peak value. If the detected peak value is equal or higher than the nominal peak value then, a gain of 1.0 is used (no change). The computed theoretical gain is limited then to a max- Master/Slave Frame Generator Curtain Generator Pattern Generator LTI Adaptive Peaking Delay Pixel Mixer MUX YUV RGB Coarse Delay Master DCI CTI 8:8:8 Fine Delay 3x DAC ayout auout avout 656out ITU656 Encoder 8 LTI Adaptive Peaking Delay MQFP144 package only 9 Formatter 444 422 9 8 bit 9 9 Slave CTI dgout dbout drout Fig. 2-56: Block diagram of display processing Fig. 2-57: DCI basic function Y_OUT [IRE] 100 90 80 70 60 50 40 30 20 Minimum pivot point Y_IN [IRE] 100 Maximum pivot point 40 IRE Pivot point is adaptive to average brightness Segment_2 gain is adaptive to frame peak value Segment_1 gain is adaptive to dark sample distribution Each image frame is analyzed for three different characteristics like average brightness, dark sample distribution and peak value. The sensitivity of the average brightness analysis is determined by the setting of SENSWS. A higher value reduces and a lower value increases the sensitivity. The sensitivity is also a function of the analyzed picture size which is defined by analysis window settings. If a desired sensitivity is adjusted and after that the analyzed picture size is changed, then the sensitivity will also be changed. If it is desired to keep the same sensitivity for different analysis window settings, then the SENSWS value has to be matched by linear interpolation to the new size (see the example given below). 7 00 7 20 30 40 50 7 IRE 60 70 80 90 Micronas Nov. 28, 2002; 6251-576-3PD 57 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Pixelperline analyzed Linesperframe analyzed SENSWS = -----------------------------------------------------------------------------------------------------------------9112 ERRORCOMP = 32 SENSES ------------------------------DYTC (integer part only) 680 536 SENSWS = --------------------- = 40 9112 The contribution of peaks with small size to the total frame peak value is controlled by PEAK_SIZE. A lower value for PEAK_SIZE increases, and a higher value reduces the contribution of peaks in the image. The sensitivity of the dark sample distribution analysis is determined by the setting of SENSBS. A higher value reduces and a lower value increases the sensitivity. The sensitivity is also a function of the analyzed picture size which is defined by analysis window settings. If a desired sensitivity is adjusted and after that the analyzed picture size is changed, then the sensitivity will also be changed. If it is desired to keep the same sensitivity for different analysis window settings then the SENSBS value has to be matched by linear interpolation to the new size as described for SENSWS. Dark sample distribution analysis considers for the measurement the size of dark areas related to the total size of analysis window so that small dark parts in the image do not influence the measurement too much. The sensitivity to small dark areas is adjustable by DYTC. Lower value for DYTC means high sensitivity and higher value low sensitivity. The basic function of average brightness analysis is the measurement of light sample and dark sample contribution difference. The contribution of light sample is weighted by LSWF value. The LSWF setting determines which picture will be considered as light and which as dark. A lower value for LSWF reduces and a higher value increases the measured result of average brightness. LSWF=0 turns the contribution of light samples off and every picture will be considered as dark. SCANID gives information about interlace/progressive input and should be set equal to FMODE. Image analysis is done frame by frame. Depending on the analysis results a suitable transfer function is used for video processing. The analysis results are filtered with a time constant determined by the settings ABFTC for average brightness, DSFTC for dark sample distribution and PK_FTC for peak analysis. A shorter time constant results from a higher setting and a longer time constant from a lower setting for XX_FTC. ERRORCOMP is used to increase the analysis precision in dark sample distribution part by taking the remainder value in temporal register at the end of analysis into consideration. The value of ERRORCOMP is determined by the settings of SENSBS and DYTC. The equation below should be used to determine the proper value. 58 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Additional to adaptive peaking, a luminance transition improvement (LTI) circuit may be enabled by LTI. 2.6.2. Adaptive Peaking The luminance peaking filter improves the overall frequency response of the luminance channel. It consists of two filters working in parallel. They have high pass (HP) and band pass (BP) characteristics. The peaking filter clock frequency is CLKB36 (usually 36 MHz). The maximum signal frequency of the picture stored in the memory is 6.75 MHz. Due to a peaking after postscaler, the frequency range of the peaking filter varies with the expansion factor of the postscaler. Amount of bandpass peaking APK2BP Peaking APK1BP Table 2-38: Peaking filter frequencies Expansion Factor of Postscaler Corresponding Frequency of Input Signal for Center Frequency Bandpass (BP) 0.75 ... 1 ... 3 2.66 MHz ... 3.55 MHz ... 10.65 MHz Highpass (HP) 6.75 MHz ... 9 MHz ... 27 MHz Amount of highpass peaking Denoising Damping Max. Bandpass-filtered input signal ATH1BP ATH1BP + ATH2BP APK2HP Peaking The peaking is picture-content adaptive. APK1HP Damping 15 Peaking filter characteristic Denoising Max. Highpass-filtered input signal 10 gain[dB] 5 ATH1HP ATH1HP + ATH2HP Fig. 2-59: Adaptive peaking segments (BP and HP) 0 5 0 1 2 3 4 5 6 7 frequency [MHz] Fig. 2-58: Bandpass/highpass filter characteristic In a first region, adjustable by ATH1BP and ATH1HP for bandpass and highpass, respectively, the signal is damped for to reduce noise (denoising). The second region is adjusted by ATH2BP (ATH2HP). For this region, the amount of peaking is given by APK1BP (APK1HP). The peaking value for the last part is given by APK2BP (APK2HP). Micronas Nov. 28, 2002; 6251-576-3PD 59 VSP 94x5B, VSP 94x7B 2.6.3. Color Transition Improvement (CTI) A digital algorithm is implemented to improve horizontal transitions of the chrominance signals resulting in a better picture sharpness. A highpass/bandpass frequency peaking of the signal usually produces broad overshoots. To eliminate "wrong colors", which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically. The amount of peaking for the bandpass is adjusted by PKCTIBPM, for the highpass by PKCTIHPM. PRELIMINARY DATA SHEET Table 2-39: Pixelmixer layer naming conventions Layer Master channel Slave channel Master frame Slave frame Curtain Background and testpattern Suffix M S G F C P a) CrCb input The size of the background layer determines the size of the picture. This means, that the background must have at least the size of the picture to be displayed. Every layer is determined by the position of the upper left edge (HORPOSx, VERPOSx) and a stretch in horizontal and vertical direction (HORWIDTHx, VERWIDTHx). Additionally, the frame-size is defined by HORFRAMEx and VERFRAMEx. While in the default case of interlace (FMODE=0), the parameters VERPOSx and VERWIDTHx are directly used, in the case of progressive (FMODE=1) the parameters VERPOSx and VERWIDTHx are multiplied by 2. This is necessary for avoiding additional changes after switching from interlace to progressive or vice versa in order to display all picture elements at the same position. b) Ampl. t t c) Cr out Cb out H-SYNC HORPOSP HORWIDTHP HORWIDTHC HORFRAMEG VERPOSC V-SYNC VERPOSP VERFRAMEG Fig. 2-60: Principles of CTI 2.6.4. Pixel Mixer The aim of the pixel mixer is the combination of the different paths of video sequences to one final video stream being shown by the display unit. Thereby 6 different sources (layer) are possible which are listed in the following table: VERWIDTHP VERPOSG a) CrCb input of CTI b) CrCb input + correction signal c) sharpened and limited CrCb t HORPOSC HORPOSG/M HORWIDTHG/M HORPOSF/S HORFRAMEF HORWIDTHF/S VERPOSF VERWIDTHG VERWIDTHC G VERWIDTHF Master M VERFRAMEF master frame S slave S Frame Background Curtain Fig. 2-61: Example of pixel mixer output 60 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B The components of this virtual overblending channel can be the master and the slave without frame ((PRIOF The master frame and the slave frame can additionally be taken into consideration (PRIOG=PRIOM+2=PRIOF+4=PRIOS+6 or PRIOF=PRIOS +2=PRIOG+4=PRIOM+6). Table 2-41: Suggested priorities for pixel mixer Show PiP PRIOF PRIOS PRIOG PRIOM Fig. 2-62: Overblending PRIOC PRIOP The blending can be enabled by OBSOFT. The temporal dynamic version is enabled by OBTEMP. In this temporal overblending mode TBLEND specifies how long the soft switching from master components to slave components or vice versa will take. In the static mode (OBTEMP=0), TBLEND gives the proportion of master and slave channel. Table 2-40: Static and dynamic blending OBTEMP 0 TBLEND 00 01 10 11 1 00 01 10 11 Ratio of Lower/Higher Priority 25/75 50/50 62.5/37.5 75/25 100/0...fast...0/100 100/0...medium...0/100 100/0...slow...0/100 100/0...very slow...0/100 Y U V Hide PiP 8 6 12 10 2 0 Use Curtain 8 6 12 10 2 14 12 10 8 6 2 0 2.6.4.2. Background and Testpattern Component Displaying the background trivially uses constant values for the Y, U, and V components. However, also nontrivial background images can be generated. How they look like can be seen in the following figure. The used pattern is defined by the IIC-bus parameter PATTERN_MODE having 3 bits. For the trivial background '000' is used. Fig. 2-63: Possible testpattern Micronas Nov. 28, 2002; 6251-576-3PD 61 VSP 94x5B, VSP 94x7B All patterns have a length of 288 lines. The chroma is always in 4:4:4 format. In horizontal direction 960 pixels are generated. If the displayed picture size differs from (288/960), blank picture is added or picture content is cut. The trivial background pattern takes for Y the constant luminance YBAGR, for U and V the constant chrominance UBAGR and VBAGR. The Yramp gives only a ramp to the luminance channel. The U and V channel are "0". The ramp starts at 0 and with every clock cycle the output increases. After 255 the output starts at 0 again. So nearly four ramps will be seen with 960 pixel resolution. The Yrampsoft is only one ramp over the whole screen. It starts at black and is increases every forth pixel. Maximum amplitude is reached after 960 pixel. The YUVrampsoft equals the Yrampsoft having a ramp on U and V additionally. The colorbar equals an ITU100/75/75 color bar. The crosshatch is used to adjust the geometry of the picture. Some vertical and horizontal lines with white and are inserted into a black picture. The chroma is always 0. 2.6.4.3. Window Generator PRELIMINARY DATA SHEET close window open window Fig. 2-65: Vertical windowing All settings are also available in vertical direction. All IC parameters exist for both directions (e.g. WINDHON and WINDVON for horizontal and vertical window enabling). Combinations of both window functions (horizontal and vertical) are also possible. close window open window Fig. 2-66: Horizontal and vertical windowing 2.6.5. Coarse and Fine Delay This generator is able to realize an automatic closing and opening of the displayed picture. This means that with every picture the displayed curtain, defined by UCUR, VCUR and YCUR will get bigger or smaller. The original picture data will be replaced by the curtain values and vice versa. 4096 different colors are available. The Fig. 2-64 shows the functionality of the horizontal window function. The window can be closed or opened. Before digital-to-analog conversion an adjustment of the phase of the luminance is performed. A coarse delay from -8 to +7 in steps of 1 pixel CLKB36 (~28 ns) are possible (COARSEDEL). FINEDEL shifts the luminance one CLKB72 (~14 ns) pixel. This can be used to compensate delays, when Y and UV are externally processed differently (e.g. lowpass filtered). 2.6.6. YCrCb Control for Digital Output The VSP 94xxB supports the following picture adjustment parameters on the master and slave signal: - 0 contrast 63/32 (DPCON) - -15 brightness 48(DPBRT) open window close window - 0 saturation Cr 63/32 (DPVSAT) - 0 saturation Cb 63/32 (DPUSAT) These adjustments should only be used, if there is no other adjustment possible in the system (e.g. flat-panel application). In case of analog display (tube), these adjustments should be done in backend device. Fig. 2-64: Horizontal windowing The windowing feature can be enabled by the WINDHON parameter. The WINDHST and the WINDHDR parameter determine, what status (opened or closed) the window has, and what can be done with the window (open or close). With each enabling of the window function by the WINDHON parameter, the status of the window will be as defined by WINDHST and WINDHDR. To change from close" to open" or vice versa only the WINDHDR parameter has to be toggled. The speed of the window can be defined by the WINDHSP parameter. The Figure 2-65 shows the functionality of the vertical window function. 62 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.6.8. Oversampling and DAC After conversion into 8:8:8 format (CLKB72=72 MHz), three 9-bit digital-to-analog converters are used for analog YUV output. This twofold-oversampling generates 1920 active pixels per line (when using recommended settings) and simplifies the external postfiltering. Output voltage is determined by PKLY, PKLU and PKLV in a range of 0.4 ...1.9 V (fullscale). The maximum output amplitude calculates as follows: 2.6.7. RGB Matrix The yuv_rgb block converts video data from yuv-format to rgb-format by means of a free programmable matrix. This RGB signal is intended to be used as digital 3*9bit RGB signal, but may also be used on analog outputs. C1...C6 are signed integer values in the range from -511...511. The color saturation may be influenced by "S" in the range about 0.5 RGB-matrix Tint, Saturation Voltage = 1, 56V PKLx + 0, 36V signal ------------ 256 1 ( SK rb + SaK rr ) ( - SaK rb + SK rr ) Y R = 1 ( SK gb + SaK gr ) ( - SaK gb + SK gr ) * C b G B Cr 1 ( SK bb + SaK br ) ( - SaK bb + SK br ) max. 1.9 V max. 0.95 V max. 1.9 V CHROMAAMP =0 'no color' The following matrix is obtained by default parameters. Y R 10 1, 4 G = 1 - 0, 34 - 0, 71 * C b B 1 1, 77 0 Cy ;;;;;;; OFFSTDUV 0V Fig. 2-67: DAC output signals 8 bits of the luminance D/A converter are used for the entire signal. The 9th bit is used for over- and undershoots caused by the peaking to prevent or reduce clipping artifacts. As the CTI block seldomly produces such overshoots, a full-scale operation can be activated by CHROMAMP. For luminance, full-scale operation can be activated by LUMAMP. Micronas 9 bit conversion range C11 -------128 R C3G = 1 -------128 B C51 -------128 C2-------128 Y C4 -------- * C b 128 Cy C6-------128 ;;;;;; ;;;;;; ;;;;;; ;;;;;; 16 LSB 'black' 128 LSB lower headroom for peaking OFFSETDY 240 LSB normal signal range 9 bit conversion range 0V max. 0.8 V ;;;;;; ;;;;;; 128 LSB upper headroom for peaking PKLY CHROMAAMP =1 PKLU PLLV Nov. 28, 2002; 6251-576-3PD 63 VSP 94x5B, VSP 94x7B 2.6.9. Output-Data Controller The output data controller generates horizontal and vertical syncs. Both sync-generators have a so called "locked-mode" and "freerunning-mode". The Table 2- 42 shows all configurations. Table 2-42: HOUT and VOUT generator configurations Mode "H-and-V-locked" mode "H-freerunning/ V-locked" mode "H-locked/ V-freerunning" mode "H- and V-freerunning" mode HOUTFR 0 1 0 1 VOUTFR 0 0 1 PRELIMINARY DATA SHEET 2.6.9.2. VOUT Generator The VOUT generator has two operation modes, which can be selected by the parameter VOUTFR. In the freerunning-mode (VOUTFR=1) the VOUT signal is generated depending on the LPFOP parameter. In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal derived from CVBS, delayed by some lines (OPDEL). OPDEL must be adjusted for different input signals and different IC adjustments. During one incoming V-Sync signal, two VOUT pulses have to be generated. The polarity of the VOUT signal is programmable by the parameter VOUTPOL. The VOUT signal is active high for two output lines Table 2-43: Display line scanning pattern sequence 1 Display sequence --- 1. to 2. (lines) 312 313 312 312.5 313 312.5 312.5 312.5 625 625.5 2. to 3. (lines) 313 312 312.5 313 312.5 312 312.5 312.5 625 624.5 3. to 4. (lines) 312 313 313 312.5 312 312.5 312.5 312.5 625 625.5 4. to 5.(1.) (lines) 313 312 312.5 312 312.5 313 312.5 312.5 625 624.5 For freerun mode the backend part works stand alone without analyzing the input signal. The clock domains, input data part and output data part of the IC, are not related to each other. If the output processing works in the freerun mode, the output signals of the ODC are generated depending on IC-bus settings. For locked mode the backend part works with a line locked clock. This means that the frontend and the backend of the IC depend on each other. The generation of the controlling signals depends on output signals from the frontend. This mode will be the default and the most used mode for standard TV applications. When no or very weak signal is connected to the CVBS input, the IC can be configured to automatically switch into freerunning mode. This stabilizes the display which may contain OSD information, e.g. during channel-tune. The configuration, whether the IC switches to H-freerun, V-freerun or both can be configured by AUTOFRRN. 2.6.9.1. HOUT Generator The HOUT generator has two operation modes, which can be selected by the parameter HOUTFR. The HOUT signal is active high for 64 clock cycles (CLKB36). In the freerunning-mode the HOUT signal is generated depending on the PPLOP parameter. In the locked-mode the HOUT signal is locked on the incoming H-Sync signal derived from CVBS. The polarity of the HOUT signal is programmable by the parameter HOUTPOL. --- --- --- --- --- --- --- - - 2.6.9.3. BLANK Generator The BLANK signal is used to horizontally and vertically mark active picture area. It is enabled by BLANEN and its polarity can be chosen by BLANPOL and VBLANPOL. Referred to hsync, the start is given by BLANDEL and its length is given by BLANLEN, both adjustable in 4 pixel resolution. Referred to vsync, the start is given by VBLANDEL and its length is given by VBLANLEN, both adjustable in 1 lines resolution.The blank information can be supplied to pin "656vio/blank" (656BLANK) or pin "vout50/blank" (V50BLANK). 64 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.6.13. Digital YUV/RGB Output 4:4:4 RGB as well as 4:4:4 and 4:2:2 YUV signals with either 8 or 9 bits are supported. 2.6.10. Static Pin Switching It is possible to set the pin "h50/irq" to static 0 or 1 by GPH50. It is possible to set the pin "vin" to static 0 or 1 by CPUIRQ2V. In 144 package only, three pins (GP0...2) can be controlled individually by IC commands (GP0, GP1, GP2). dgout8 dgout7 dgout6 dgout5 dbout8 dbout7 dbout6 dbout5 dbout4 dbout3 dbout2 dbout1 dbout0 drout8 drout7 drout6 drout5 drout4 drout3 drout2 drout1 drout0 MSB MSB C800 1 0 CD1 1 VIN/INTR static '0' static '1' dgout4 VOUT dgout3 dgout2 dgout1 dgout0 V100IN 9 bit output LSB 0 1 2 3 0 V100IN CPUIRQ output CD2 DP RGB 4:4:4 G B R YUV 4:4:4 Y U V CPUIRQ2V YUV 4:2:2 Fig. 2-68: VIN/INTR and VOUT switching 2.6.11. VSP 94xxB in PiP Operation Only Y U/V 656 ITU656output (8 bit only) Fig. 2-69: Possibilities of digital output connections The IC can be used to produce a PiP only (PCE mode), which is synchronized to external H/V signals. This can be used i.e. to insert a PiP into a PC-signal which is directly connected to the RGB/deflection stage. For this, the vout-pin can be set to input by V100IN and hout to tristate by H100TR. Additionally, the incoming H signal must be connected to any CVBS, GIN or FBLIN pins. The BLANK signal indicates the valid PiP picture in order to switch between the main-signal and the PiP in the backend. 2.6.12. Digital 656 Output The output data format corresponds to ITU656 (8-bit bus at a data rate of 27 MHz). Timing reference codes (SAV, EAV) are inserted according to the specification. The output can be enabled by DPOUT656. The display clock should be set to linelocked-clock (HOUTFR) with 27 MHz (PPLIP) and 720 pixels per line (HORWIDTHP). 656 output data is available at pins 656io0...7. In QFP144 versions, 656 output is available at green output (dgout0...7) additionally. The clock output (pin 656clk) is CLKB72 always (usually 27 or 54 MHz) and can be inverted by CLK656OUTINV. Table 2-44: Digital output configuration in QFP144 M422 RGB 4:4:4 8 bit 9 bit YUV 4:4:4 8 bit 9 bit YUV 4:2:2 8 bit 9 bit 656 8 bit 0 0 0 0 1 1 x DWO 0 1 0 1 0 1 x TO1RGB 1 1 0 0 0 0 x DPOUT656 0 0 0 0 0 0 1 Micronas 8 bit output LSB Nov. 28, 2002; 6251-576-3PD 65 VSP 94x5B, VSP 94x7B 2.7. Clock Concept A single 20.25 MHz crystal at fundamental mode is used as clock reference. All other clocks are derived from this source. The CVBS frontend works with 20.25 MHz, the RGB frontend and input processing operates at 40.5 MHz, the oversampling DACs use 72.0 MHz and the memory and all parts behind the memory are clocked with 36 MHz. Three different clock concepts are supported. The difference is the behavior in clocking the memory output. The frontend part of the VSP 94x5B uses a free-running but crystal-stable clock (CLKF). After deskewing, an orthogonal picture is written into the memory. The read out is done using the (CLKB) clock. The horizontal sync-signal output (HOUT) is derived from a counter running with CLKB. The VOUT is directly derived from the input vertical signal, which is generated by the sync-separation block. This "H-freerunning-V-locked mode" is only possible together with a DC coupled deflection controller. In "H-and-V-locked mode" CLKB is line-locked to the incoming signal. The freerunning YUV picture data and the internal H signal are converted to the linelocked domain. Now HOUT and the sync signal in the 1fH domain are directly coupled. PRELIMINARY DATA SHEET In case of "H-and-V-freerunning mode" the HOUT and VOUT signals are derived from counters running with CLKB. There is no connection to the incoming signal. This mode can be used for stable pictures when no signal is applied (e.g. channel search with OSD insertion). The clock output can be disabled by CLKOUTON. CLKOUTINV inverts the clock. HOUT and VOUT are in line with the sampling clock CLKB27, CLKB36 or CLKB72. Even when clkout is not used in the system, CLKOUTSEL72, CLKOUT72 and CLKOUTSEL must be set properly to obtain correct HOUT, VOUT and BLANK signals. Table 2-45: Clock output and hout/vout/blank clock reference CLKOUT SEL72 CLKOUT 72 CLKOUT SEL CLKOUT (HOUT, VOUT, BLANK derived from) 0 0 1 0 0 1 0 1 0 CLKB27 CLKB36 CLKB72 Table 2-46: Clock output and hout/vout clock reference clock system (FR=free-running; LL=line-locked) Name Clock Nominal Frequency H- and Vlocked Mode FR FR LL H-freerunning V-locked Mode FR FR FR H- and Vfreerunning Mode FR FR FR CLKF20 CLKF40 CLKB36 CVBS frontend RGB frontend, input processing Output and display processing 20.25 MHz 40.5 MHz 9407: 36 MHz (analog out) 9417: 27 MHz (digital out) 9437: 18 MHz (analog out) 9447: 13.5 MHz (digital out) 9407: 72 MHz 9417: 54 MHz 9437: 36 MHz 9447: 27 MHz 9407: 27 MHz 9417: 20.25 MHz 9437: 13.5 MHz 9447: 10.125 MHz CLKB72 Oversampling, DAC LL FR FR CLKB27 Pins "clockout", "hout", "vout" LL FR FR 66 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 2.7.1. Line-locked Clock Generator The clock generation system derives all clocks from one 20.25 MHz crystal oscillator clock source. Linelocked horizontal sync pulses are generated by a digital phase locked loop. The time constant can be adjusted between fast and slow behavior (KPL, KIL) to accommodate different backend ICs. The PLL control can be frozen up to 15 lines before v-sync (FION) for a duration up to 15 lines (FILE). This may be used to reduce disturbances by h-phase errors which are produced by VCR's. The output frequency for the 100/ 120 Hz version dependent on IICINCR is nominal 50 Hz operation (analog out) 13.5 18 27 36 MHz nominal 50 Hz operation (digital out) nominal 100 Hz operation (analog out) nominal 100 Hz operation (digital out) Fig. 2-70: Allowed operation area for clock generation f display = IICINC 103Hz The number of pixels generated by the PLL is given by PPLIP. For linelocked clock generation the following equation must be fulfilled: A freerunning frequency is also generated which may be selected alternatively. The freerunning frequency for the double-scan versions dependent on FRINC is PPLIP = PPLOP f displayfr = FRINC 103Hz Dependent on ARTSYNC and ITUSYNC, the LL-PLL input is different (see Table 2-47). Table 2-47: LL-PLL input ARTSYNC 0 1 1 ITUSYNC x 0 1 LL_PLL Input CD input (parallel operation) CD output (serial operation) ITU656 input Normally, IICINCR and FRINC are equal or nearly the same. The display frequency is internally divided by two for the single-scan versions. Table 2-48: LL-PLL settings Operation Double-scan (analog out) Double-scan (digital out) Single-scan (analog out) Single-scan (digital out) Input 50 Hz 60 Hz 50 Hz 60 Hz 50 Hz 60 Hz 50 Hz 60 Hz 1728 864 262144 2304 1152 349525 1728 864 262144 PPLIP*4 2304 PPLOP*4 1152 IICINCR 349525 FRINCR 349525 351953 262144 263892 349525 351953 262144 263892 CLKB36 [MHz] 36 36.25 27 27.18 18 18.125 13.5 13.59 fH[kHz] 31.250 31.468 31.250 31.468 15.625 15.734 15.625 15.734 Micronas Nov. 28, 2002; 6251-576-3PD 67 VSP 94x5B, VSP 94x7B 3. IC Bus 3.1. IC Bus Slave Address When pin ADR/TDI is connected to Vss, VSP 94xxB reacts on first IC address. The second address is active, when pin ADR/TDI is connected to Vdd. Table 3-1: IC slave address Write Address 10110000=B0h 10110010=B2h Read Address 10110001=B1h 10110011=B3h ADR/TDI=0 ADR/TDI=1 S 3.2. IC Bus Format The VSP 94x7B IC bus interface acts as a slave receiver and a slave transmitter and provides two different access modes (write, read). All modes run with a subaddress auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission. VSP 94x7B has 16 bit IC registers only. The two bytes per register are referred as Byte_A and Byte_B. They are either read_only or write_only registers. Byte A is the higher byte and is transmitted first. It is always transmitted if the register is addressed. Byte B is the lower byte. It need not be transmitted if only byte A is of interest. Table 3-4: Write sequence examples S S S SAW SAW SAW A A A SBR SBR SBR A A A D_A D_A D_A A A A STP D_B D_B A A STP D_A A SAW SAR SBR D_A D_B STP START ADR/TDI=0 ADR/TDI=1 PRELIMINARY DATA SHEET Byte A has always to be transmitted before byte B can be accessed. All read and write registers are auto increment registers. However, the auto increment function can be disabled by the control bit AUTOINC_OFF in register DAh. If the auto increment function is switched off, the bytes A and B of write registers will be updated (overwritten) cyclically every second data byte. The bytes A and B of read registers will be polled cyclically every second byte. Table 3-2: 16 bit IC format A7, A6, A5, A4, A3, A2, A1, A0 Byte_A: MSB B7, B6, B5, B4, B3, B2, B1, B0 Byte_B: LSB Table 3-3: Index of IC abbreviations ACKNOWLEDGE SLAVE ADDRESS WRITE SLAVE ADDRESS READ SUBADDRESS DATA BYTE A DATA BYTE B STOP ... A STP Table 3-5: Read sequence examples S S S SAW SAW SAW A A A SBR SBR SBR A A A S S S SAR SAR SAR A A A D_A D_A D_A NA A A STP D_B D_B NA A STP D_A ... NA STP The transmitted data is internally stored in registers. The registers are located in different clock and func- tional domains. The clock domains can be found in Table 3-6. 68 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-8: Store Commands Clock CLKF20 CLKF40 CLKB3, CLKB72 CLKB36 CLKF20 CLKF40 CLKF40 CLKB36 CLKB36 CLKF27, CLKF40 CLKF36 CLKF40 CLKB36 CLKB36 CLKB36 The IC parameter VS1_20stat, VS2_20stat, VSM1_40stat, VSM2_40stat, VSS1_40stat, VSS2_40stat, VSRGB_40stat, VSBM1_36stat, VSBM2_36stat, VSBS_36stat, VSDCI_36stat and VS656_27stat reflect the state of the register values. If these bits are read as 1, then the store command was sent, but the data is not made available yet. If these bits are 0, then the data was made valid and a new write or read cycle can start. These registers may be checked before writing or reading new data, otherwise data can be lost if different data is written too fast to a register. Table 3-9: IC bus register types Register Types W R Rrstyp Write register Read register Reset register after reading Hand-shake mechanism The registers are grouped into update-domains. The update of each domain must be enabled by setting the corresponding bit in the store command word. The update domain, where the data are made valid with the V-sync signal of the 20.25 MHz domain are indicated in the register overview by VS1_20 or VS2_20 respectively. The others update domains are called VSM1_40, VSM2_40, VSS1_40, VSS2_40, VSRGB_40, VSBM1_36, VSBM2_36, VSBS_36, VSDCI_36 and VS656_27. For immediate update (no wait for V-sync), IM1_20, IM2_20, IMM1_40, IMM2_40, IMS1_40, IMS2_40, IMRGB_40, IMBM1_36, IMBM2_36, IMBS_36, IMDCI_36 and IM656_27 can be used. The update status of the registers can be checked by read register F7h. S SAW A 'FFh' A VS_high A VS_low A STP Table 3-6: IC bus clock domains Domain CP1 IP1 DP1 OP1 CP2 FP IP2 DP2 OP2 ITU PP C800 MEM MAUS ODC Description CVBS frontend Master Input Processing Master Display Processing Master Output Processing Master CVBS frontend Slave RGB processing Input Processing Slave Display Processing Slave Output Processing Slave ITU656 processing LL-PLL C800 Memory Controller Motion adaptive upconversion Output Data Controller 3.3. Modification of IC Write Registers Modified register data becomes effective - After being activated by a store command (nearly all registers). - In some cases immediately after writing, if the register is marked by "NTO" (=no take over mechanism) There are two types of store commands: - Immediately after store command specified for this register domains (FEh) Table 3-7: Store Commands S SAW A 'FEh' A IM_high A IM_low A STP HS - At the next rising edge of the V-sync signal specified for this register domains (FFh) Both store commands should not be used in the same IC telegram. Micronas Nov. 28, 2002; 6251-576-3PD 69 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Table 3-10: IC bus register characterization Take-over Mechanism NTO VS1_20 VS2_20 VSSLI_20 VSRGB_40 VSM1_40 VSM2_40 VSS1_40 VSS2_40 VSBM1_36 VSBM2_36 VSBS_36 VS656_27 No take-over mechanism CVBS frontend master CVBS frontend slave Data slicer RGB frontend Input processing master before V-scaler Input processing master behind V-scaler Input processing slave before V-scaler Input processing slave behind V-scaler Master behind memory Master behind v-scaler Slave behind memory ITU656 input / ITU656 output Take-over with V-sync in 27.0 MHz domain Take-over with V-sync in backend 36.0 MHz domain Take-over with V-sync in 40 MHz domain Take-over with V-sync in 20 MHz domain 3.4. Update of IC Read Registers The read process does not make use of store commands. The update of read register data is done - By the sync signals as described for the write registers, but the direction of the data flow is opposite ("normal" read registers). The update status of the registers can be checked by read register F7h. - Immediately (NTO read registers) - With reset after read (RS read registers) RS type registers behave like a RS flip flops. Whenever the corresponding signal has a high level it sets the register bit to "1". After being read by the IC bus master, the whole register will be automatically reset (means value 0) . For example the register NMSTATUSM belongs to the "rs typ" read registers. NMSTATUSM signalizes a new value for NOISEMEM. So if NMSTATUSM is read as 0 the current noise measurement has not been updated. If the NMSTATUSM is read as 1 a new noise measurement value can be read. All other "rs typ" read registers work in the same way. The "rs typ" read registers will be marked in the overview with the short cut "rstyp" or will have the additional hint "Note: reset automatically when read/write" in the detailed IC bus command description. Registers which need a hand-shake mechanism between the IC bus interface and the different blocks are marked with the shortcut HS (Hand shake mechanism). This means that all bits of the registers are used when the last register is written. After IICINCR18-3 is written, IICINCR2-0 must be written to allow these bits to have effect. The registers for the write parameter RMODE are directly connected to the read registers of the parameter RMMIRROR. So it is possible to check the IC bus protocol by writing and reading to the register RMODE and RMMIRROR, respectively. 70 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 3.5. Miscellaneous I2C Register OPTIMUS After switching on the IC, all bits of the VSP 94x2A are set to defined states. POR is set after reset to pin 24. It stays 1, until it is canceled via software PORCNCL. This can be used to detect a reset on pin 24. During TV operation, it can be used to decide whether to program all registers (e.g. after power failure reset) or only altered ones (normal TV operation). Writing to or reading from a non -existent register is permitted but does not generate a fault by the IC. Two counters (0...15) are available, which are incremented with every vertical pulse of input processing master (FCIM) or output processing master (FCBM). They can be used for software synchronization. 3.6. Important Hints 00h-5Ch 60h-62h WRITE MASTER WRITE COMMON WRITE SLAVE WRITE COMMON READ MASTER READ SLAVE READ COMMON STORE COMMAND 63h-97h 98h-DAh DBh-E4h E5h-E9h EAh-FCh FDh-FFh Fig. 3-1: IC bus address overview The signal FJMODE can be found in 57h and 5Eh (same position). Do always write the same values to FJMODE in 57h and FJMODE in 5Eh. The signal LPFOPOFF can be found in BBh and BFh (different position). Do always write the same values to LPFOPOFF in BBh and LPFOPOFF in BFh. Micronas Nov. 28, 2002; 6251-576-3PD 71 VSP 94x5B, VSP 94x7B 3.7. IC Bus List in Alphabetical Order Table 3-11: IC bus list in alphabetical order Name 656BLANK AABYP AASEL AB_FTCM ACCFIXM ACCFIXS ACCFRZM ACCFRZS ACCLIMM ACCLIMS ADATA0 ADATA1 ADATA2 ADATA3 ADATA4 ADATA5 ADATA6 ADATA7 ADCSEL ADINS ADLCKCCM ADLCKCCS ADLCKM ADLCKS ADLCKSELM ADLCKSELS ADLINE ADR_RDY AFPROC AGCADJ1M Address 9Ch A7h A4h 4Eh 01h 65h 01h 65h 0Eh 72h F9h F9h FAh FAh FBh FBh FCh FCh A7h 9Fh 0Fh 73h 0Fh 73h 0Fh 73h 9Fh F7h C1h 0Bh PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name AGCADJ1S AGCADJ2M AGCADJ2S AGCADJB AGCADJCV1 AGCADJCV2 AGCADJF AGCADJG AGCADJR AGCFRZEM AGCFRZES AGCMDM AGCMDS AGCPWRESM AGCPWRESS AGCRESM AGCRESS AGCTHDM AGCTHDS ALPFIPI ALPFIPM ALPFIPS AMMON AMSTD50M AMSTD50S AMSTD60M AMSTD60S APENSELM APENSELS APK1BPM APK1BPS Address 6Fh 0Ch 70h A8h DDh E7h A9h A9h A8h 0Ch 70h 0Bh 6Fh 5Fh 63h 0Ch 70h 5Fh 63h A2h 26h 88h 2Dh 5Fh 63h 5Fh 5Fh63h 22h 84h 49h 95h 72 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name BLANLEN BLANPOL BLUESEL BLUETWO BRTADJ C1 C2 C3 C4 C5 C6 C800 C800 CDELHPOSM CDELHPOSS CFORMAT CHRFM CHRFS CHROMAMP CHROMSIGN656 CHRSFM CHRSFR CKILLM CKILLS CKILLSM CKILLSS CKSTATM CKSTATS CLK656OUT CLK656OUTINV CLKF2PAD Address D5h D4h AAh AAh A4h C2h/C5h C2h/C5h C3h/C5h C3h/C5h C4h/C5h C4h/C5h D9h FDh 33h 8Ah A3h 04h 68h C9h C1h C1h A4h 05h 69h 06h 6Ah DCh E6h 9Eh C1h A5h Table 3-11: IC bus list in alphabetical order Name APK1HPM APK1HPS APK2BPM APK2BPS APK2HPM APK2HPS APPLIPI APPLIPM APPLIPS ARSDIS ARTSYNC ATH1BPM ATH1BPS ATH1HPM ATH1HPS ATH2BPM ATH2BPS ATH2HPM ATH2HPS AUTOFRRN AUTOGAP AUTOINC_OFF BELLFIRM BELLFIRS BELLIIRM BELLIIRS BGPOSM BGPOSS BGSHIFTM BGSHIFTS BLANDEL Address 4Ah 96h 49h 95h 4Ah 96h A1h 23h 85h BFh 3Fh 49h 95h 4Ah 96h 49h 95h 4Ah 96h 45h 20h DAh 11h 75h 11h 75h 12h 76h 60h 63h D4h Micronas Nov. 28, 2002; 6251-576-3PD 73 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name CLKOUT72 CLKOUTINV CLKOUTON CLKOUTSEL CLKOUTSEL72 CLKT1 CLMPD1M CLMPD1S CLMPD1SM CLMPD1SS CLMPD2M CLMPD2S CLMPD2SM CLMPD2SS CLMPHIGHM CLMPHIGHS CLMPLOWM CLMPLOWS CLMPSIG1 CLMPSIG2 CLMPST1M CLMPST1S CLMPST1SM CLMPST1SS CLMPST2M CLMPST2S CLMPST2SM CLMPST2SS CLMPVG CLMPVRB CLPSTGYM Address D4h D4h D4h D4h D5h ACh 01h 65h 0Fh 73h 02h 66h 0Fh 73h 0Dh 71h 0Eh 72h 98h 98h 03h 67h 0Ch 70h 04h 68h 0Dh 71h A7h A8h 01h PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name CLPSTGYS CLRANGEM CLRANGES COARSEDEL COLONM COLONS COMBM COMBS COMBUSEM COMBUSES CONADJ CONM CONS CONSM CONSS COR CORONM CORONS CPLLOFM CPLLOFS CPLLRESM CPLLRESS CPUDISABLE CPUIRQ2V CRCBM CRCBS CSC_ONM CSTANDM CSTANDS CVBOSEL1 CVBOSEL2 Address 65h 12h 76h D8h 01h 65h 05h 69h 02h 66h A4h 02h 66h 01h 65h 9Ah 4Ah 96h 01h 65h 0Ch 70h DAh DAh 03h 67h 4Ch 05h 69h 99h 99h 74 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name DETVPOLS DIGOUTEN DISALLRESM DISALLRESS DISCHCHM DISCHCHS DISCOMB DISPMODE DISRES DPBRT DPCON DPOUT656 DPUSAT DPVSAT DSFTCM DT DTFDT DWO DYNOPFJGM DYNOPFJGS DYNOPFJN0 DYNOPFJN1 DYNOPFJN2 DYNOPFJN3 DYNOPFJN4 DYNOPFJP0 DYNOPFJP1 DYNOPFJV DYNOPITGM DYNOPITGS DYNOPITN0 Address E6h C1h 07h 6Bh 01h 65h 9Bh BFh ACh 42h 42h C1h 83h 82h 50h 9Ah 2Eh C1h 58h 58h 59h 59h 5Ah 5Ah 5Bh 55h 5Bh 55h 58h 58h 59h Table 3-11: IC bus list in alphabetical order Name CVBOSEL3 CVBSEL1 CVBSEL2 DATA_CCWSS1 DATA_CCWSS2 DATA_USWSS1 DATA_USWSS2 DATA_USWSS3 DATAVCCWSS DATAVUSWSS DBDHPOSM DBDHPOSS DBDPICIM DBDPICIS DC DCI_CORM DCIONM DCLMPF DCR DDR DDR_CC DEC2 DEEMPFIRM DEEMPFIRS DEEMPIIRM DEEMPIIRS DEEMPSTDM DEEMPSTDS DETHPOLM DETHPOLS DETVPOLM Address 99h 98h 98h EAh EAh ECh EBh EBh ECh ECh 33h 8Ah 4Ah 96h 9Ah 4Dh 4Ch A7h 9Ah 9Ah 60h A5h 10h 74h 10h 74h 11h 75h DCh E6h DCh Micronas Nov. 28, 2002; 6251-576-3PD 75 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name DYNOPITN1 DYNOPITN2 DYNOPITN3 DYNOPITN4 DYNOPITP0 DYNOPITP1 DYNOPITV DYNOPLSGM DYNOPLSGS DYNOPLSN DYNOPLSP0 DYNOPLSP1 DYNOPLSV DYNOPMSGM DYNOPMSGS DYNOPMSN0 DYNOPMSN1 DYNOPMSN2 DYNOPMSN3 DYNOPMSN4 DYNOPMSP0 DYNOPMSP1 DYNOPMSV DYNOPSMGM DYNOPSMGS DYNOPSMN0 DYNOPSMN1 DYNOPSMN2 DYNOPSMN3 DYNOPSMN4 DYNOPSMP0 Address 59h 5Ah 5Ah 5Bh 55h 5Bh 55h 56h 56h 57h 56h 56h 56h 58h 58h 59h 59h 5Ah 5Ah 5Bh 55h 5Bh 55h 58h 58h 59h 59h 5Ah 5Ah 5Bh 55h PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name DYNOPSMP1 DYNOPSMV DYTCM EIA770M EIA770S ELINEM EN_656 ENA_DEMOM ENLIMM ENLIMS EPIXELM ERRORCMPM EXTRD F_OFFS F2F1F0 FBLACTIVE FBLCONF FBLDEL FBLOFFST FEMAGM FEMAGS FETHD FHDETM FHDETS FHFRRNM FHFRRNS FIELDBINV FILE FILMMODEM FINEDEL FIOFFOFF Address 5Bh 55h 51h 0Fh 73h 4Dh A3h 4Ch 11h 75h 4Ch 51h C0h 9Fh 9Ah EDh A6h A5h AAh 19h 7Bh B2h 02h 66h 06h 6Ah 45h ACh DFh D8h C1h 76 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name FRAFION FRAMEDIMM FRAMEDIMS FRCBGNDM FRCBGNDS FRCMMODM FRCMMODS FREEZE_ANLM FREEZEM FREEZES FREQSELL FRFIX FRINC FRZLIMLR FSWFTL GAINSEG1FRCM GAINSEG2FRCM GAPM GCMON GFBON GMAMM GMASM GMDSTATUSM GMFMFBENA GMOTIONM GMOTREGM GMSTEN GMSTSL GMSTSS GMSTTH GMSTTHV Address 2Fh D2h D2h 21h 83h 22h 84h 4Dh 13h 77h AFh 5Dh 5Dh 5Eh C1h E3h E4h 32h 5Ch BDh 29h 28h E2h 54h E1h E1h 29h 29h 28h 28h/29h 21h Table 3-11: IC bus list in alphabetical order Name FION FJMODE FJSELLNV FKOI FKOIHYS FLDINVM FLDINVS FLINEM FLINES FLNSTRDM FLNSTRDS FMATH FMDCTH FMDSON FMDTH FMFORCE FMFORCETRIG FMMEMHIS FMOD FMODE FMOTREGM FMREGION FMRES FMSCALEL FMSCALEU FMSTATUSM FMSYN FMSYNUNS FMTHRON FMTHYON FPOL Address AEh 57h/5Eh 54h AFh AFh 01h 65h 01h 65h 11h 75h 2Ch 2Bh 2Bh 2Ch 57h 57h 2Ch ADh BDh E0h 2Bh 2Bh 2Bh 2Bh E2h 14h 14h 2Bh 2Bh 9Fh Micronas Nov. 28, 2002; 6251-576-3PD 77 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name GMTHLM GMTHUM GOFST GPH50 GPP0 GPP1 GPP2 GRADELAA GRADISSTABLE GRADSLAA GSFMFBENA GSTHLM GSTHUM GSTILLENA GSTILLM H50SKEW HAAPRESCM HAAPRESCS HDCPRESCM HDCPRESCS HDG HDTOTEST HINC0M HINC0S HINC1M HINC1S HINC2M HINC2S HINC3M HINC3S HINC4M Address 29h 28h A5h DAh 20h 24h 24h F5h F3h F2h 54h 2Ah 2Ah 54h E1h 5Fh 23h 85h 23h 85h 99h ACh 34h 8Bh 35h 8Ch 36h 8Dh 37h 8Eh 38h PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name HINC4S HINCR_EXT HINPM HINPS HORFRAMEF HORFRAMEG HOROFFS HORPOSF HORPOSG HORPOSM HORPOSNM HORPOSP HORPOSS HORWIDTHF HORWIDTHG HORWIDTHM HORWIDTHNM HORWIDTHP HORWIDTHS HOUTDEL HOUTFR HOUTPOL HOUTTR HPANONM HPANONS HPE1OFF HPE2OFF HPEXOFF HPOL HPOLM HPOLS Address 8Fh ADh 03h 67h CBh D0h 91h/92h CAh CEh 45h 27h C6h 91h CBh CFh 47h 27h C7h 93h BCh BCh D4h C1h 33h 8Ah C0h C0h C0h A3h 02h 66h 78 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name IMBS_36 IMDCI_36 IMM1_40 IMM2_40 IMODE IMRGB_40 IMS1_40 IMS2_40 IMSLI_20 INCOMB INCOMBC INITLINESEL INTM INTPROGM INTPROGS INTS INVSKEW IRQCON ISHFTM ISHFTS ITUPRTSEL ITUSYNC JLCRES KD2 KIL KINL KOIH KOIWID KPL KPNL LB43SENS Address FEh FEh FEh FEh 9Fh FEh FEh FEh FEh 9Ch 5Fh 57h DCh 13h 77h E6h 3Fh 9Ch 11h 75h A3h 3Fh BFh ADh AFh B1h ADh ADh B1h B1h B4h Table 3-11: IC bus list in alphabetical order Name HPS1OFF HPS2OFF HRES HSCPOSCM HSCPOSCS HSCPRESCM HSCPRESCS HSEG1M HSEG1S HSEG2M HSEG2S HSEG3M HSEG3S HSEG4M HSEG4S HSPPL HSWIN HTESTW HUEM HUES HWID IFCOMPM IFCOMPS IFCOMPSTRM IFCOMPSTRS IICINCR IM1_20 IM2_20 IM656_27 IMBM1_36 IMBM2_36 Address C0h C0h AEh 33h 8Ah 22h 84h 34h/35h 8Bh/8Ch 36h/37h 8Dh/8Eh 38h/39h 8Fh/90h 39h 90h 61h ADh ADh 08h 6Ch AEh 0Eh 72h 0Eh 72h ABh/ACh FEh FEh FEh FEh FEh Micronas Nov. 28, 2002; 6251-576-3PD 79 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name LBACTIVITY LBASDEL LBELAA LBFORMAT LBFS LBGFBDEL LBGRADDET LBGRADRST LBGSDEL LBHISTBLA LBHIWHITE LBHSDEL LBHWEND LBHWST LBMASLA LBNGFEN LBSLAA LBSTABILITY LBSTATUS LBSUB LBSUBTITLE LBTHDNBNG LBTHDNBNHA LBTOPTITLE LBVISUON LBVWENDLO LBVWENDUP LBVWSTLO LBVWSTUP LIMEN LIMHI Address BAh BAh F4h F3h B8h B9h B5h B4h B9h B7h B6h B4h B6h B7h B8h B4h F4h B4h E2h B4h F3h BAh B4h F3h BAh B5h B8h B8h B9h B3h ACh PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name LIMII LIMIP LIMLR LINLENH50 LINLENH60 LMOFSTM LMOFSTS LNL LNSTDRDM LNSTDRDS LOCKSPM LOCKSPS LPBLACK LPCDELM LPCDELS LPFIPI LPFIPMD LPFLDM LPFLDS LPFOP LPFOPOFF LPPOSTM LPPOSTS LPWHITE LSWFM LTIM LTIS LUMAMP M422 MASLEX MASTERON Address B2h B0h AFh 9Bh 9Bh 03h 67h ACh DCh E6h 0Fh 73h F3h 07h 6Bh A0h 45h DBh E5h BDh/BEh BBh/BFh 01h 65h F3h 4Fh 49h 95h C8h C1h BFh BDh 80 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name MVPGM MVPGS MVPM MVPS MVREFPOS MVVISENA NALPFIPI NALPFIPM NALPFIPS NAPIPPHI NAPPLIPI NAPPLIPM NAPPLIPS NAPPLOP NEGLINESEL NMCHAN NMLINEM NMLINES NMPOSM NMPOSS NMSENSEM NMSENSES NMSTATUSM NMSTATUSS NOFHSYNC NOGRADFOUND NOISE NOISEMEM NOISEMES NOISESTATUS NOSEL Address 60h 63h 60h 63h 54h 54h A1h 25h 87h 9Fh A2h 24h 86h BBh 57h 20h 18h 7Ah 18h 7Ah 18h 7Ah E2h E9h 48h F3h DEh DEh E8h E2h 9Ah Table 3-11: IC bus list in alphabetical order Name MAXALC MAXAUC MAXGLC MAXGUC MAXHLC MAXHUC MDVFFON MIXGAIN MIXOP MOTONM MOTONS MOTVALON MPFBLBM MPFBLBS MPFBLTM MPFBLTS MPFBPLM MPFBPLS MPFBPRM MPFBPRS MVCHOLD MVCOFA0 MVCOFA1 MVCOFP0 MVCOFP1 MVDIVA MVDIVP MVDIVR MVFIXENA MVFIXVAL MVMODE Address F0h/F1h F2h EFh EEh F1h F0h 2Bh A5h A8h 24h 86h BFh 1Fh 81h 20h 82h 21h 83h 20h 82h 54h 53h 53h 53h 53h 53h 53h 53h 54h 54h 54h Micronas Nov. 28, 2002; 6251-576-3PD 81 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name NOSIGBM NOSIGBS NOSYNC NOTCHOFFM NOTCHOFFS NRONM NRONS NRPIXELM NRPIXELS NSHAP NSREDM NSREDS NTCHSELM NTCHSELS NTSCREFM NTSCREFS OBSOFT OBTEMP OFFSET OMODE OPDEL OPPHASEFR OSCPD P3DIS P4DIS PALDELM PALDELS PALDETIDLM PALDETIDLS PALDETM PALDETS Address 03h 67h BCh 11h 75h 19h 7Bh DBh E5h C1h 07h 6Bh 12h 76h 09h 6Dh D2h D2h 32h 9Eh BCh/BEh 56h AFh C0h C0h 12h 76h 3Fh 46h DDh E7h PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name PALIDL0M PALIDL0S PALIDL1M PALIDL1S PALIDL2M PALIDL2S PALIDM PALIDS PALINC1M PALINC1S PALINC2M PALINC2S PALREFM PALREFS PATTMODE PB PDGSR PEAK_SIZEM PFBL PG PIXELPLINEM PIXPLINM PIXPLINS PK_FTCM PKCTIBPM PKCTIBPS PKCTIHPM PKCTIHPS PKLU PKLV PKLY Address 0Ah 6Eh 09h 6Dh 12h 76h DCh E6h 12h 76h 12h 76h 0Ah 6Eh D2h EDh BDh 52h EDh EDh 4Eh 13h 77h 52h 49h 95h 49h 95h D7h D8h D7h 82 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name REFTRIMEN REFTRIMRD REFTRIMRGB REFTRIMRGBRD REMDEL1 REMDEL2 RESETPC1 RESETPC2 RESMODE REV RGBSEL RMMIRROR RMODE RSHIFTM RSHIFTS SATNRM SATNRS SCADJM SCADJS SCAN_IDM SCDEVM SCDEVS SCMIDLM SCMIDLS SCMRELM SCMRELS SCOUTENM SCOUTENS SDBM SDBS SDRM Address 9Bh 62h 9Dh 62h 60h 60h 9Bh 9Bh 9Bh F6h A6h F6h BCh 17h 17h 07h 6Bh 0Bh 6Fh 4Ch DCh E6h 0Dh 71h 10h 74h DCh E6h 19h 7Bh 19h Table 3-11: IC bus list in alphabetical order Name PLLTCM PLLTCS POR PORCNCL PPLIP PPLIPI PPLOFF PPLOP PR PRIOC PRIOF PRIOG PRIOM PRIOP PRIOS PWTHDM PWTHDS RBOFST RDPNTOFF RDPOSXM RDPOSXS RDPOSYM RDPOSYS READM READM2S READS REFRON REFRPER REFTRIM REFTRIMCV REFTRIMCVRD Address 04h 68h ECh 9Bh AEh 9Eh BBh BDh EDh D3h D3h D3h D3h D2h D3h 03h 67h A9h 16h 16h 79h 17h 79h 16h 77h 79h BFh BFh 9Dh 9Dh 62h Micronas Nov. 28, 2002; 6251-576-3PD 83 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name SDRS SECACCLM SECACCLS SECACCM SECACCS SECDELM SECDELS SECDIVM SECDIVS SECINC1M SECINC1S SECINC2M SECINC2S SECNTCHM SECNTCHS SELCOMB SELMASTER SELSLAVE SELSM SENSBSM SENSITIVM SENSWSM SERVICE SETSTABLL SHAPERDIS SHIFTACT SHIFTUV SKEWSEL SLAVEON SLFLDCCWSS SLFLDUSWSS Address 7Bh 0Eh 72h 10h 74h 3Fh 46h 10h 74h 10h 74h 10h 74h 02h 66h 9Bh AAh AAh AAh 50h 32h 4Fh 9Ch ADh AFh F8h C1h A9h BDh ECh ECh PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name SLINEM SLLTHDM SLLTHDS SLLTHDVM SLLTHDVPM SLLTHDVPS SLLTHDVS SLLWIN SLNCW SLNRUW SLOWVAR SLS SLSRC SMMODE SMOP SPIXELM STABLL STABM STABS STANDBYCV STANDBYDAC STANDBYRGB STATOPMSC STATOPMSCENA STATSIZE STDETM STDETS STOPMOS SUBTITLE SVALFI SVALFR Address 4Dh 0Bh 6Fh 11h 0Fh 73h 75h B2h 60h 60h 20h F6h 9Ch 54h AAh 4Ch F6h DDh E7h A5h 15h A5h 57h 57h DFh DCh E6h C0h F3h 2Dh 2Dh 84 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name TNOTCHOFFM TNOTCHOFFS TNRABSM TNRABSS TNRCLCM TNRCLCS TNRCLYM TNRCLYS TNRCS0M TNRCS0S TNRCS1M TNRCS1S TNRCS2M TNRCS2S TNRCS3M TNRCS3S TNRCS4M TNRCS4S TNRCS5M TNRCS5S TNRCS6M TNRCS6S TNRCS7M TNRCS7S TNRCSSM TNRCSSS TNRMD4YM TNRNR4CM TNRNR4YM TNRNR4YS TNRSELM Address 12h 76h 19h 7Bh 1Eh 80h 1Eh 80h 1Ch 7Eh 1Ch 7Eh 1Ch 7Eh 1Ch 7Eh 1Dh 7Fh 1Dh 7Fh 1Dh 7Fh 1Dh 7Fh 1Eh 80h 19h 19h 19h 7Bh 19h Table 3-11: IC bus list in alphabetical order Name SVALLI SWGM SWITCHTO43 SYNCFTHDM SYNCFTHDS SYNCGAINM SYNCGAINS SYNCOMB TBLEND TFDPPM TFDT TFLDDON TFON THEM THES THFI0 THFI1 THFI2 THFI3 THFR0 THFR1 THFR2 THFR3 THLI0 THLI1 THLI2 THRGM THRMOV THRSELM THRSELS TINT Address 2Fh 2Dh F3h 00h 64h 5Fh 63h 9Ah D2h E3h/E4h 2Dh 2Dh 2Eh 49h 95h 2Eh 2Fh 30h 31h 2Eh 2Fh 30h 31h 2Fh 30h 31h 2Dh 2Eh 07h 6Bh 15h Micronas Nov. 28, 2002; 6251-576-3PD 85 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name TNRSELS TNRYS0M TNRYS0S TNRYS1M TNRYS1S TNRYS2M TNRYS2S TNRYS3M TNRYS3S TNRYS4M TNRYS4S TNRYS5M TNRYS5S TNRYS6M TNRYS6S TNRYS7M TNRYS7S TNRYSSM TNRYSSS TO1RGB TOPTITLE TRAPBLUM TRAPBLUS TRAPREDM TRAPREDS TSTSHABRI TVMODE UBAGR UBORDERM UBORDERS UCUR Address 7Bh 1Ah 7Ch 1Ah 7Ch 1Ah 7Ch 1Ah 7Ch 1Bh 7Dh 1Bh 7Dh 1Bh 7Dh 1Bh 7Dh 1Eh 80h C5h F3h 12h 76h 12h 76h AFh ECh CEh 1Fh 81h C9h PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name UENINV UFRAMEM UFRAMES UPBLACK UPDATERATEM UPDATESS UPWHITE USATADJ UVCODE UVCORM UVCORS UVDEL V100IN V50BLANK V656DEL VAAPRESCM VAAPRESCS VBAGR VBLANDEL VBLANLEN VBLANPOL VBORDERM VBORDERS VCRDETHD VCRPRESCM VCRPRESCS VCUR VDCPRESCM VDCPRESCS VDELAY_BE VDETIFSM Address C5h 4Bh 97h F3h 20h 14h F3h A7h C1h 02h 66h A6h C1h 9Bh C1h 25h 87h CFh D5h/D6h D6h D4h 1Fh 81h 98h 25h 87h CAh 26h 88h DAh 0Fh 86 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name VINC2M VINC3M VINC4M VINMTHD VINPM VINPS VLENGTHM VLENGTHS VLEROFF VLEXOFF VLPM VLPS VLS1OFF VOFPOSC VOUTFR VOUTPOL VPANONM VPK VPKPRESCM VPKPRESCS VPOL VPOLM VPOLS VPREBYPM VPREBYPS VS1_20 VS1_20STAT VS2_20 VS2_20STAT VS656_27 VS656_27STAT Address 3Dh 3Eh 3Fh 45h 03h 67h DDh E7h C0h C0h 11h 75h C0h 40h/41h BCh D4h 3Ah 9Ah 25h 87h A3h 07h 6Bh 26h 88h FFh F7h FFh F7h FFh F7h Table 3-11: IC bus list in alphabetical order Name VDETIFSS VDETITCM VDETITCS VDG VDOUBLEM VERFRAMEF VERFRAMEG VEROFFS VERPOSF VERPOSG VERPOSM VERPOSP VERPOSS VERRESM VERRESS VERSION VERWIDTHF VERWIDTHG VERWIDTHM VERWIDTHP VERWIDTHS VFLYMDM VFLYMDS VFLYWHLM VFLYWHLMDM VFLYWHLMDS VFLYWHLS VFRAMEM VFRAMES VINC0M VINC1M Address 73h 10h 74h 99h 3Ah CCh D1h 94h CCh D0h 46h C8h 92h 13h 77h F6h CDh D1h 48h C9h 94h DDh E7h 0Ch 04h 68h 70h 4Bh 97h 3Bh 3Ch Micronas Nov. 28, 2002; 6251-576-3PD 87 VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name VSATADJ VSBM1_36 VSBM1_36STAT VSBM2_36 VSBM2_36STAT VSBS_36 VSBS_36STAT VSCPOSCM VSCPRESCM VSCPRESCS VSDCI_36 VSDCI_36STAT VSEG1M VSEG2M VSEG3M VSEG4M VSEL_BE VSHIFTM VSHIFTS VSIGNAL VSLPF VSM1_40 VSM1_40STAT VSM2_40 VSM2_40STAT VSREF VSRGB_40 VSRGB_40STAT VSS1_40 VSS1_40STAT VSS2_40 Address A7h FFh F7h FFh F7h FFh F7h 3Ah 27h 89h FFh F7h 3Bh/3Ch 3Dh/3Eh 40h 41h DAh 08h 6Ch A3h 61h FFh F7h FFh F7h 9Fh FFh F7h FFh F7h FFh PRELIMINARY DATA SHEET Table 3-11: IC bus list in alphabetical order Name VSS2_40STAT VSSLI_20 VSSLI_20STAT VTHRH50M VTHRH50S VTHRH60M VTHRH60S VTHRL50M VTHRL50S VTHRL60M VTHRL60S WINDHDR WINDHON WINDHSP WINDHST WINDVDR WINDVON WINDVSP WINDVST WRITEM WRITES WRITES2M WRPOSXM WRPOSXS WRPOSYM WRPOSYS XDSCLS XDSTPE Y2RGB YBAGR YBORDERM Address F7h FFh F7h 0Ah 6Eh 00h 64h 09h 6Dh 00h 64h C7h C7h C7h C7h C6h C6h C6h C6h 13h 77h 13h 13h 77h 14h 78h 9Ch 9Ch AAh CDh 1Fh 88 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Table 3-11: IC bus list in alphabetical order Name YBORDERS YCBYB YCBYR YCDELM YCDELS YCSELM YCSELS YCTOCOMB YCUR YFDEL YFRAMEM YFRAMES YUVMAT YUVSEL Address 81h 98h 98h 07h 6Bh 03h 67h 98h C8h A6h 4Bh 97h 15h AAh Micronas Nov. 28, 2002; 6251-576-3PD 89 3.8. IC Command Table Table 3-12: IC Command Table Subadd (Hex) Data Byte A A7 SYNCFTHDM CONSM CONM PWTHDM VFLYWHLMDM COMBM CKILLSM VPOLM HUEM NTSCREFM PALREFM SLLTHDM AGCRESM CLMPHIGHM IFCOMPSTR M SLLTHDVPM DEEMPFIRM DEEMPSTD M PALDELM INTPROGM WRPOSYM STANDBYDA C RDPNTOFF RDPOSYM NMLINEM FEMAGM SDRM SDBM NMSENSEM TNRABSM NRONM NMPOSM TNRSELM TNRNR4YM TNRMD4YM TNRNR4CM RDPOSXM YUVMAT FREEZEM BELLFIRM TNOTCHOFF M VERRESM WRITEM SECACCLM EIA770M VDETIFSM LOCKSPM DEEMPIIRM BELLIIRM BGPOSM WRITES2M CLMPLOWM ADLCKM VDETITCM SLLTHDVM PALINC1M PIXPLINM PALINC2M ADLCKSELM ADLCKCCM AGCFRZEM SCADJM AGCADJ2M THRSELM YCDELM CSTANDM CRCBM CHRFM 90 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Data Byte B A6 A5 VTHRH60M COLONM UVCORM LMOFSTM CPLLOFM LPPOSTM SECNTCHM VINPM ACCFIXM ACCFRZM HPOLM YCSELM NOSIGBM PLLTCM CKILLM FHFRRNM DISALLRES M VSHIFTM PALIDL1M PALIDL0M AGCMDM VFLYWHLM SCMIDLM ACCLIMM CLMPD2SM SECACCM SECDIVM SECINC1M ENLIMM CLRANGEM CLMPD1SM SECINC2M ISHFTM NTCHSELM NOTCHOFF M SCMRELM VLPM TRAPBLUM TRAPREDM CPLLRESM VTHRL50M VTHRH50M AGCADJ1M CLMPST1SM CLMPST2SM IFCOMPM SATNRM NSREDM LPCDELM FLINEM A4 A3 A2 A1 A0 B7 B6 VTHRL60M FLDINVM FHDETM HINPM B5 B4 B3 B2 B1 B0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h CLPSTGYM COMBUSEM CLMPST1M CLMPST2M DISCHCHM CLMPD1M CLMPD2M FLNSTRDM PALIDL2M WRPOSXM UPDATESS FMSYN TINT PRELIMINARY DATA SHEET FMSYNUNS READM RSHIFTM RSHIFTS Micronas 18h 19h Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 TNRYS0M TNRYS4M TNRCS0M TNRCS4M TNRYSSM YBORDERM MPFBPRM FRCBGNDM MPFBPLM HSCPRESCM HDCPRESCM GPP2 GPP1 NAPPLIPM VCRPRESC M VDCPRESCM HORWIDTHNM GMTHUM GMTHLM VSCPRESCM GMSTSS GMSTEN GSTHLM GMSTSL GMASM GMAMM ALPFIPM NALPFIPM APPLIPM MPFBLTM Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Data Byte B A6 A5 A4 A3 TNRYS1M TNRYS5M TNRCS1M TNRCS5M TNRCSSM UBORDERM GPPO GMSTTHV A2 A1 A0 B7 TNRYS2M TNRYS6M TNRCS2M TNRCS6M TNRCLYM VBORDERM B6 B5 B4 B3 TNRYS3M TNRYS7M TNRCS3M TNRCS7M TNRCLCM MPFBLBM B2 B1 B0 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h NMCHAN SLOWVAR AUTOGAP UPDATERATEM FRCMMODM APENSELM HAAPRESCM MOTONM VAAPRESCM VPKPRESCM VERBYPM HORPOSNM GMSTTH[1] GMSTTH[0] GSTHUM MDVFFON FMMEMHIS TFLDDON DTFDT[1] THRGM THRMOV FMDSON FMDCTH FMATH VSP 94x5B, VSP 94x7B FMRES FMTHYON FMTHRON FMSCALEL FMDTH FMSCALEU FMREGION SVALFI DTFDT [0] THLI0 FRAFION THFR2 THFR3 SENSITIVM THFR0 SVALFR AMMON TFON SWGM THFI0 TFDT SVALLI THLI1 THLI2 GAPM HPANONM HSEG1M[10:5] HSEG1M[4:0] DBDHPOSM THFR1 THFI1 THFI2 THFI3 OFFSET CDELHPOS M HSCPOSCM HINC0M HINC1M 91 Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 HSEG2M[10:5] HSEG2M[4:0] HSEG3M[10:5] HSEG3M[4:0] VPANONM VSEG1M[9:5] VSEG1M[4:0] VSEG2M[9:5] VSEG2M[4:0] INVSKEW VOFPOSC[7:3] VOFPOSC[2:0] DPBRT PWADJCNTM PWADJCNTS AUTOFRRN LPFIPMD VINMTHD SECDELS FIELDBINV PALDETIDLS HORWIDTHM NOFHSYNC PKCTIBPM APK1HPM[1:0] PKCTIHPM APK2HPM YFRAMEM SPIXELM SLINEM PIXELPLINEM SENSWSM SENSBSM ERRORCMPM PK_FTCM DYTCM PEAK_SIZEM DSFTCM ELINEM EPIXELM DCI_CORM AB_FTCM LSWFM LTIM VERWIDTHM APK1BPM ATH1HPM APK2BPM ATH2HPM UFRAMEM DBDPICIM ATH1BPM APK1BPM[3:2] ATH2BPM APK1HPM[3:2] VFRAMEM ENA_DEMO M SCAN_IDM CSC_ONM DCIONM FREEZE_AN LM THEM CORONM HORPOSM VERPOSM ARTSYNC ITUSYNC SECDELM PALDETIDL VSEG3M VSEG4M DPCON DPCNS MINVM MINVS VDOUBLEM VSCPOSCM VINC0M VINC1M VINC2M VINC3M VINC4M HSEG4M 92 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Data Byte B A6 A5 A4 A3 A2 A1 A0 HINC2M HINC3M HINC4M B7 B6 B5 B4 B3 B2 B1 B0 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h PRELIMINARY DATA SHEET Micronas Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 MVCOFA0 MVMODE DYNOPMSV DYNOPLSGM DYNOPLSN DYNOPMSGM DYNOPMSN0 DYNOPMSN2 DYNOPMSN4 MVREFPOS Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Data Byte B A6 A5 MVCOFA1 SMMODE MVFIXENA DYNOPITV DYNOPLSGS FMFORCETR FJMODE IG DYNOPITGM DYNOPITN0 DYNOPITN2 DYNOPITN4 MVFIXVAL DYNOPSMV DYNOPFJV DYNOPMSP0 DYNOPLSP0 INITLINESEL STATOPMSC DYNOPITGS DYNOPITN1 DYNOPITN3 DYNOPITP1 DYNOPSMG S A4 A3 A2 MVCOFP0 A1 A0 MVCOFP1 B7 B6 B5 MVDIVA GMFMFBEN A B4 B3 MVDIVP B2 B1 MVDIVR B0 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh GSFMFBENA GSTILLENA DYNOPITP0 MVVISENA FJSELLNV MVCHOLD DYNOPSMP0 DYNOPFJP0 DYNOPLSP1 STATOPMSC ENA DYNOPFJGS OPPHASEFR DYNOPLSV NEGLINESEL FMFORCE DYNOPSMG M DYNOPFJGM DYNOPMSGS DYNOPMSN1 DYNOPMSN3 DYNOPMSP1 DYNOPSMN0 DYNOPFJN0 DYNOPSMN2 DYNOPFJN2 DYNOPSMN4 DYNOPFJN4 DYNOPSMN1 DYNOPFJN1 DYNOPSMN3 DYNOPFJN3 DYNOPSMP1 DYNOPFJP1 GCMON FRINC[18:3] FJMODE INCOMBC MVPM HSPPL REFTRIMRD MVPS SYNCFTHDS CONSS CONS PWTHDS VFLYWHLMDS COMBS CKILLSS VPOLS HUES NTSCREFS PALREFS THRSELS YCDELS CSTANDS CRCBS CHRFS MVPGS BELLIIRS [2] VTHRH60S COLONS UVCORS LMOFSTS CPLLOFS LPPOSTS SECNTCHS VINPS ACCFIXS ACCFRZS HPOLS YCSELS NOSIGBS PLLTCS CKILLS FHFRRNS DISALLRESS SATNRS VSHIFTS PALIDL1S PALIDL0S VTHRL50S VTHRH50S NSREDS LPCDELS FLINES BELLFIRS[2] DEEMPIIRS [2] DEEMPFIRS [2] AMSTD50S MVPGM BELLIIRM[2] SLNCW BELLFIRM[2] DEEMPIIRM[ 2] DEEMPFIRM[ 2] AMSTD50M SLNRUW VSLPF REFTRIMCVRD AMSTD60S VTHRL60S FLDINVS FHDETS HINPS CLPSTGYS COMBUSES CLMPST1S CLMPST2S DISCHCHS CLMPD1S CLMPD2S SYNCGAINS REFTRIMRGBRD AMSTD60M FRZLIMLR FRFIX FRINC[2:0] H50SKEW BGSHIFTM AGCTHDM REMDEL2 REMDEL1 SYNCGAINM AGCPWRES M DDR_CC VSP 94x5B, VSP 94x7B AGCPWRES S BGSHIFTS AGCTHDS 93 Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 SLLTHDS AGCRESS CLMPHIGHS IFCOMPSTR S SLLTHDVPS DEEMPFIRS DEEMPSTDS PALDELS INTPROGS WRPOSYS RDPOSYS NMLINES FEMAGS TNRYS0S TNRYS4S TNRCS0S TNRCS4S TNRYSSS YBORDERS MPFBPRS FRCBGNDS FRCMMODS HAAPRESCS MOTONS VAAPRESCS VPKPRESCS VPREBYPS VDCPRESCS VSCPRESCS HPANONS HSEG1S[10:5] DBDHPOSS CDELHPOSS HSCPOSCS HINC0S MPFBPLS APENSELS HDCPRESCS NAPPLIPS VCRPRESCS NALPFIPS ALPFIPS HSCPRESCS APPLIPS MPFBLTS TNRYS1S TNRYS5S TNRCS1S TNRCS5S TNRCSSS UBORDERS SDRS SDBS TNRYS2S TNRYS6S TNRCS2S TNRCS6S TNRCLYS VBORDERS DPVSAT DPUSAT RDPOSXS NMSENSES TNRABSS NRONS NMPOSS TNRSELS TNRNR4YS TNRYS3S TNRYS7S TNRCS3S TNRCS7S TNRCLCS MPFBLBS READS FREEZES BELLFIRS TNOTCHOFF S VERRESS WRITES SECACCLS EIA770S VDETIFSS LOCKSPS DEEMPIIRS BELLIIRS BGPOSS READM2S CLMPLOWS ADLCKS VDETITCS SLLTHDVS PALINC1S PIXPLINS PALINC2S ADLCKSELS ADLCKCCS AGCFRZES 94 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Data Byte B A6 A5 SCADJS AGCADJ2S A4 A3 A2 A1 A0 B7 AGCMDS VFLYWHLS SCMIDLS ACCLIMS CLMPD2SS SECACCS B6 B5 AGCADJ1S B4 B3 B2 B1 B0 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh CPLLRESS CLMPST1SS CLMPST2SS IFCOMPS CLMPD1SS SECDIVS SECINC1S ENLIMS SECINC2S ISHFTS NTCHSELS NOTCHOFFS SCMRELS VLPS TRAPBLUS TRAPREDS FLNSTRDS PALIDL2S WRPOSXS CLRANGES PRELIMINARY DATA SHEET Micronas Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 HSEG1S[4:0] HSEG2S[10:5] HSEG2S[4:0] HSEG3S[10:5] HSEG3S[4:0] HOROFFS[10:6} HOROFFS[5:0] HORWIDTHS VEROFFS PKCTIBPS APK1HPS[1:0] PKCTIHPS APK2HPS YFRAMES CVBSEL1 CVBOSEL1 DDR LINLENH50 XDSCLS REFTRIM OMODE NAPIPPHI CLK656out F_OFFS ADLINE LPFIPI APPLIPI NAPPLIPI VSIGNAL BRTADJ CLKF2PAD YFDEL USATADJ AGCADJR VSATADJ AGCADJB FBLDEL GOFST MIXGAIN UVDEL ADCSEL MIXOP AABYP CFORMAT HPOL VPOL EN_656 ITUPRTSEL CONADJ CHRSFR AASEL ALPFIPI NALPFIPI PPLIPI FPOL IMODE ADINS VSREF F2F1F0 LINLENH60 656BLANK XDSTPE REFTRIMCV CVBSEL2 CVBOSEL2 DT DC COR LTIS VERWIDTHS APK1BPS ATH1HPS APK2BPS ATH2HPS UFRAMES CLMPSIG1 CVBOSEL3 NOSEL REFTRIMEN V50BLANK IRQCON DCR PORCNCL SYNCOMB RESETPC1 CLMPSIG2 DBDPICIS ATH1BPS APK1BPS[3:2] ATH2BPS APK1BPS[3:2] VFRAMES VCRDETHD VDG VPK RESETPC2 SERVICE REFTRIMRGB SELCOMB INCOMB DISCOMB RESMODE SLSRC YCBYR YCBYB HDG YCTOCOMB THES CORONS HSEG4S HORPOSS VERPOSS Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Data Byte B A6 A5 A4 A3 A2 A1 A0 HINC1S HINC2S HINC3S HINC4S B7 B6 B5 B4 B3 B2 B1 B0 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h VSP 94x5B, VSP 94x7B STANDBYRG STANDBYCV DEC2 B RGBSEL CLMPVG CLMPVRB FBLCONF DCLMPF 95 Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 AGCADJG FBLOFFST IICINCR[18:3] CLKT1 KOIWID HRES FREQSELL HWID HDTOTEST KOIH FION OSCPD SHAPERDIS TSTSHABRI LIMLR[2:0] FILE HTESTW PPLIP FKOI LIMIP KPNL[3:0] KPL[3:0] SLLWIN FETHD KINL[3:0] LIMII HSWIN[3] LBSUB LBGRADDET LBHIWHITE LBHISTBLA LBMASLA LBGSDEL LBASDEL PPLOFF VOUTFR GFBON OPDEL DISPMODE STOPMOS CHROMSIGN FIOFFOFF 656 C1 C3 C5 TO1RGB UENINV C6 C5 DPOUT656 SHIFTUV MOTVALON EXTRD FSWFTL P3DIS AFPROC REFRON P4DIS V656DEL REFRPER HPE1OFF CLK656OUTI HOUTTR NV C2 C4 C6 C4 C3 C2 C1 HOUTFR FMODE NOSYNC PDGSR LPFOPOFF RMODE MASTERON SLAVEON OPDEL(MSB) HOUTDEL LPFOP(8) PPLOP LBVWSTLO LBGFBDEL LBVISUON LBACTIVITY NAPPLOP LBFS LBGRADRST LBSTABILITY LB43SENS LBNGFEN LBTHDNBNHA LBVWENDLO LBHWEND LBHWST LBVWENDUP LBVWSTUP LBTHDNBNG LBHSDEL LIMLR[3] LIMEN KPNL[4] KPL[4] KINL[4] KIL[4] FKOIHYS KIL[3:0] HSWIN[2:0] LNL DISRES SETSTABLL LIMHI KD2 IICINCR[2:0] HINCR_EXT LMOD FMOD 96 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Data Byte B A6 A5 A4 A3 A2 A1 AGCADJF SELMASTER SELSLAVE SELSM YUVSEL A0 B7 B6 B5 B4 B3 RBOFST SMOP B2 B1 B0 SKEWSEL A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h Y2RGB BLUESEL BLUETWO PRELIMINARY DATA SHEET LPFOP[7:0] LPFOPOFF VLEROFF UVCODE HPS1OFF V100IN HPE2OFF DIGOUTEN HPEXOFF M422 ARSDIS VLEXOFF CHRSFM JLCRES HPS2OFF NSHAP MASLEX VLS1OFF DWO Micronas C4h C5h Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 WINDVSP WINDHSP YCUR UCUR VCUR HORFRAMEF VERFRAMEF YBAGR UBAGR VBAGR HORFRAMEG VERFRAMEG PRIOP PRIOC BLANDEL CLKOUTSEL 72 VBLANDEL[4:0] PKLY COARSEDEL C800 VDELAY_BE LPFLDM DETHPOLM VFLYMDM NOISEMEM FCIM FMOTREGM GMOTREGM GSTILLM GMOTIONM DETVPOLM VLENGTHM STDETM SCOUTENM PALIDM CKSTATM VSEL_BE NRPIXELM LNSTDRDM AGCADJCV1 NOISE STATSIZE FILMMODEM INTM SCDEVM PALDETM STABM GPH50 CPUIRQ2V CPUDISABL E AUTOINC_O FF FINEDEL VBLANDEL[9:5] VBLANLEN BLANLEN PRIOS HORPOSG HORWIDTHG VERPOSG VERWIDTHG OBTEMP PRIOF VBLANPOL OBSOFT PATTMODE PRIOM CLKOUT72 CLKOUTINV HOUTPOL TBLEND PRIOG VOUTPOL BLANPOL CLKOUTSEL CLKOUTON FRAMEDIMM FRAMEDIMS Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Data Byte B A6 A5 WINDVST WINDHST A4 WINDVDR WINDHDR A3 WINDVON WINDHON LUMAMP CHROMAMP A2 HORPOSP HORWIDTHP A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h VERPOSP VERWIDTHP HORPOSF HORWIDTHF VERPOSF VERWIDTHF VSP 94x5B, VSP 94x7B PKLU PKLV 97 Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 AM50_OM TFDPPM[8:4] TFDPPM[3:0] LPFLDS DETHPOLS VFLYMDS NOISEMES AM50_OS AM60_OS DATA_CCWSS1 DATA_USWSS2 POR FBSTAT MAXGUC MAXGLC MAXALC[8:5] MAXALC[4:0] GRADSLAA LBFORMAT LBSLAA GRADELAA VERSION ADR_RDY FCBM ADATA0 ADATA2 ADATA4 ADATA6 C800 commands ADATA1 ADATA3 ADATA5 ADATA7 FIELDCD1 FIELDCD2 SLS VSRGB_40S TAT REV VSBM2_36S TAT VSBM1_36S TAT RMMIRROR VSDCI_36ST VSBS_36STA VSSLI_20ST AT T AT CHIPID VSS2_40STA VSS1_40STA VSM2_40STA VSM1_40STA VS656_27ST T T T T AT VS2_20STAT STABLL VS1_20STAT SHIFTACT LBSUBTITLE LBTOPTITLE GRADISSTA BLE TOPTITLE SUBTITLE MAXHUC MAXHLC MAXAUC NOGRADFO UND LBELAA SWITCHTO4 3 UPWHITE LPWHITE UPBLACK LPBLACK FBFALL FBRISE TVMODE PFBL SLFLDUSWS DATAVUSWS SLFLDCCWS DATAVCCWS S S S S PG PB PR FBLACTIVE NMSTATUSS DETVPOLS VLENGTHS STDETS SCOUTENS PALIDS CKSTATS 98 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Data Byte B A6 AM60_OM GAINSEG1FRCM GAINSEG2FRCM NRPIXELS LNSTDRDS AGCADJCV2 INTS SCDEVS PALDETS STABS A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 LBSTATUS B3 B2 B1 B0 E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh NOISESTATU GMDSTATUS FMSTATUSM NMSTATUSM S M DATA_CCWSS2 DATA_USWSS3 DATA_USWSS1 PRELIMINARY DATA SHEET Micronas FCh FDh Table 3-12: IC Command Table, continued Subadd (Hex) Data Byte A A7 A6 A5 A4 IMRGB_40 VSRGB_40 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Data Byte B A3 IMBM2_36 VSBM2_36 A2 IMBM1_36 VSBM1_36 A1 IMDCI_36 VSDCI_36 A0 IMBS_36 VSBS_36 B7 IMSLI_20 VSSLI_20 B6 IMS2_40 VSS2_40 B5 IMS1_40 VSS1_40 B4 IMM2_40 VSM2_40 B3 IMM1_40 VSM1_40 B2 IM656_27 VS656_27 B1 IM2_20 VS2_20 B0 IM1_20 VS1_20 FEh FFh Note: Bits written with grey background are intended not to be user adjustable and should be set to the default value written in this data sheet or according to an updated list available from Micronas. VSP 94x5B, VSP 94x7B 99 3.9. IC Command Description 3.9.1. Master Channel Table 3-13: Master channel Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Color Decoder Master 00h W VS1_20 SYNCFTHDM x x SYNCF threshold 00: 4 lines 01: 3 lines 10: 2lines 11:1 line x x x x x x x Vertical Sync gating: Closing 60 Hz Closing=262+4*VTHRH60M 0000000: Closing in line 262 1111111: Closing in line 770 x x x x x x x Vertical Sync gating: Opening 60 Hz Opening=4*VTHRL60M 0000000: Opening in first line 1111111: Opening in line 508 Color switched on at level above CKILLS (SECAM) at level=CKILLS+CONS 000: Min value 010: Default 111: Max value x Forces color on 0: Color depends on color decoder status 1: Color always on x Opens the closed loop 0: Normal operation 1: Chroma PLL opened x Additional filtering of luminance 0: No filtering 1: Filtering x Fix ACC to nominal value 0: ACC is working 1: ACC is set to fixed value according to PALREFM/NTSCREFM x Freeze ACC 0: ACC is working 1: ACC is frozen at current value x Mode selection 0: Interlace input 1: Progressive input Description 100 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VTHRH60M VTHRL60M 01h W VS1_20 CONSM x x x COLONM CPLLOFM LPPOSTM PRELIMINARY DATA SHEET ACCFIXM ACCFRZM Micronas FLINEM Table 3-13: Master channel, continued Subadd R/W Take Over Name FLDINVM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Field inversion 0: No inversion 1: Inversion x Clamping strategy 0: Back-porch clamping 1: Sync-tip-clamping x Disable channel change signal 0: Color decoder not reset after channel-change 1: Color decoder reset after channel change x x x x Measurement duratation CD1, signals 1 Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3 s Color switched on at level above CKILL (PAL/NTSC) At level=CKILL+CON 000: Min value 010: Default 111: Max value x x Chrominance coring 00: Disabled 01: 1LSB 10: 2LSB 11: 3LSB x x Selection of notch filter behavior in SECAM mode 00: 4.406 MHz 01: 4.250 MHz 10: 4.33 MHz 11: 4.406/4.205 dependent on transmitted color x x H Polarity at HINP 00: Use Hsync 01: Use inverted Hsync 10: Autodetect polarity 11: (Reserved) x Automatic multisync capability 0: Disabled 1: Enabled x x Comb filter usage CD1 00: Use first CVBS input 01: Use second CVBS input 10: Use comb-filter 11: ADCG / ADCF (dependent on ADCSEL) Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET CLPSTGYM DISCHCHM CLMPD1M 02h W VS1_20 CONM x x x UVCORM SECNTCHM VSP 94x5B, VSP 94x7B HPOLM FHDETM COMBUSEM 101 Table 3-13: Master channel, continued Subadd R/W Take Over Name CLMPD2M A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description 102 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B x Measurement duration CD1, signals Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3 s Selection of "Peak-White" threshold 00: 448 01: 470 10: 500 11: 511 03h W VS1_20 PWTHDM x x CRCBM x x Choice of UV or CrCb output 00: UV color space 01: CrCb color space 10: Modified CrCb color space (SECAM only) x x Luminance offset in color decoder during visible picture 00: No offset (NTSC) 01: - 7.5 IRE 10: + 7.5 IRE (PAL, SECAM) 11: -3.7 IRE A 7.5 IRE offset is added during blanking in display processing. When chosing 10, the luminance offset is equal to the offset of the CVBS input as in both picture and blanking the same 7.5 IRE offset is used. x Vertical pulse detection 0: From sync signal (CVBS, Y, or G)) 1: From separate V-input pin When set to 0, no V polarity detection possible x Y/C select 0: CVBS input 1: Y/C input x No signal behavior 0: Noisy screen when out of sync 1: Colored background insertion instead LMOFSTM VINPM YCSELM NOSIGBM PRELIMINARY DATA SHEET HINPM x Synchronization input 0: Synchronization from CVBS front-end (CVBS or Y/C) 1: Synchronization via RGB front-end (green or fbl ADC) When set to 0, no H polarity detection possible x x x x x x Measurement start: CD1, Signals1 000000: 0 s 011100: 5.6 s 111111: 12.8 s CLMPST1M Micronas Table 3-13: Master channel, continued Subadd 04h R/W W Take Over VS1_20 Name VFLYWHLMDM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Description Vertical flywheel mode 00: Check for correct standard 01: 3 lines deviation allowed 10: 4 lines deviation allowed, no check for interlace 11: 5 lines deviation allowed, no check for interlace x x x x x x Chroma bandwidth Selects chroma bandwidth 011100: Nominal bandwidth x x Time constant HPLL (VCR...TV) 00: Very fast 01: Fast 10: Slow 11: Very slow x x x x x x Measurement start CD1, Signals 2 000000: 0 s 011100: 5.6 s 111111: 12.8 s Delay line 0: Use delay line 1: Do not use delay line (only suited for NTSC) x x x x x x x Color standard assignment 0000000: No color standard chosen 0000001: PAL N 0000010: PAL B 0000100: SECAM 0001000: PAL 60 0010000: PAL M 0100000: NTSC M 1000000: NTSC 44 For allowed combinations please refer to chapter "chroma decoder" 1100110: PALB/SECAM/NTSCM/NTSC44/PAL60 x x x x x x x x Chroma level for color off (PAL/NTSC) 00000000: High burst amplitude 01000000: Default 11111111: Low burst amplitude Chroma level for color off (SECAM) 00000000: Low burst amplitude 01000000: Default 11111111: High burst amplitude Behavior is opposite to CKILL (PAL/NTSC case) x x x x x x x x Free running frequency of horizontal PLL 00000000: 384 clocks (52.7 kHz) 11100100: 1296 clocks (15.625 kHz) 11111111: 1404 clocks (14.423 kHz) Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET CHRFM PLLTCM CLMPST2M 05h W VS1_20 COMBM x CSTANDM VSP 94x5B, VSP 94x7B CKILLM 06h W VS1_20 CKILLSM x x x x x x x x FHFRRNM 103 Table 3-13: Master channel, continued Subadd 07h R/W W Take Over VS1_20 VPOLM Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x V-Polarity at VINP 00: Use Vsync 01: Use inverted Vsync 10: Autodetect polarity 11: (Reserved) x H-Slicing level threshold 0: 50 % 1: 37 % x x x x x Luminance delay 10000: 800 ns 0000: no delay 01111: -700 ns x Disable all chroma resets 0: Resets allowed 1: Resets disabled May only be used if ONE color standard is selected x Noise reduction for satellite signal 0: Disabled 1: Enabled x x x Noise reduction for horizontal PLL 000: 1/8 001: 1/4 010: 1/2 011: 1 100: 2 101: 4 110: 8 111: 16 x x x Window shift for fine error calculation 100: -4 clock cycles 000: No offset 011: +3 clock cycles Description 104 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B THRSELM YCDELM DISALLRESM SATNRM NSREDM LPCDELM PRELIMINARY DATA SHEET 08h W VS1_20 HUEM x x x x x x x x Hue control (tint) 10000000: -89 00000000: 0 01111111: +88 x x x x x x x x Field detection window shift 00000000: No shift 11111111: Shifted by 2048 ACC reference adjustment (NTSC) 00000000: Low reference value 10010001: Nominal value 11111111: High reference value VSHIFTM 09h W VS1_20 NTSCREFM x x x x x x x x Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name PALIDL1M A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x PAL/NTSC identification level 1 0: Less sensitive (192) 1: More sensitive (64) x x x x x x x Vertical sync gating: Opening 5 Hz Opening=4*VTHRL50M 0000000: Opening in first line 1111111: Opening in line 508 ACC reference adjustment (PAL) 00000000: Low reference value 11110000: Nominal value 11111111: High reference value x PAL/NTSC identification level 0 0: Less sensitive 1: More sensitive x x x x x x x Vertical sync gating: Closing 50 Hz Closing=312+4*VTHRH50M 0000000: Closing in line 312 1111111: Closing in line 820 When VINPM (03h) is set, 50 Hz values are taken for opening and closing values. Slicing level threshold H 00: No offset 01: Small negative 10: Small positive 11: Large positive (adaptive) x x x x x x Subcarrier adjustment 000000: -262 ppm 001111: 0 ppm 111111: 840 ppm x x AGC method 00: Sync amplitude and peak white 01: Sync amplitude only 10: Peak white only 11: Fixed to value AGCADJ1M x x x x x x Gain adjustment ADC1 000000: 0.6 V input signal 100000: 1.2 V input signal: 111111: 1.8 V input signal AGC reset 0: No reset 1: Reset x Freeze AGC (ADC_CVBS) 0: Normal operation 1: Freeze AGC at current value Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET VTHRL50M 0Ah W VS1_20 PALREFM x x x x x x x x PALIDL0M VTHRH50M 0Bh W VS1_20 SLLTHDM x x SCADJM VSP 94x5B, VSP 94x7B AGCMDM AGCADJ1M 0Ch W VS1_20 AGCRESM x AGCFRZEM 105 Table 3-13: Master channel, continued Subadd R/W Take Over Name AGCADJ2M A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x Gain adjustment ADC2 000000: 0.6 V input signal 100000: 1.2 V input signal 111111: 1.8 V input signal x Vertical flywheel 0: Disabled 1: Enabled x Force chroma PLL reset 0: No reset 1: Reset chroma PLL After use, CPLLRESM must be set to 0 again x x x x x x Clamping start CD1, Signals 1 000000: 0 s 011100: 5.6 s 111111: 12.8 s Vertical end of clamping pulse 00000000: Line 256 00111100: Line 376 11111111: Line 766 x x SECAM identification level 00: 128 01: 64 10: 96 11: 80 x x x x x x Clamping start CD1, Signals 2 000000: 0 s 011100: 5.6 s 111111: 12.8 s 2nd IF compensation filter 0: Disabled 1: Enabled x x x Secam acceptance level 000: 100 001: 84 010: 64 011: 32 100: 70 101: 76 110: 90 Note: Has only effect if SECACCM (0Eh) is enabled x x x x Vertical start of clamping pulse 0000: Line 0 0011: Line 6 1111: Line30 Description 106 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VFLYWHLM CPLLRESM CLMPST1SM 0Dh W VS1_20 CLMPHIGHM x x x x x x x x SCMIDLM CLMPST2SM 0Eh W VS1_20 IFCOMPSTRM x PRELIMINARY DATA SHEET SECACCLM CLMPLOWM Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name ACCLIMM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x ACC limitation 00000: Limit at high color-carrier 01000: Limit at -24 dB 11111: Limit at low color-carrier x x x IF compensation filter 000: Pal prefiltering 001: Pal prefiltering + IF 010: Prefiltering 011: IF 6dB 100: Flat Vertical slicing level threshold polarity 0: Positive 1: Negative x EIA 770 support 0: Standard TV signals expected 1: Progressive signals expected Note: Timing according to EIA 770.1 or 770.2 when 1 x Vertical sync-detection slope 0: Normal 1: Slow x x Duration of chroma-PLL search 00: 25 fields 01: 20 fields 10: 17 fields 11: 15 fields x Additional lock-detection 0: No used 1: Used x Additional lock-detection selection 0: PALID 1: PALDET x Additional lock-detection color-killer 0: Do not use lock signal 1: Use lock-signal x x x x Clamping duration CD1, signals 2 (for RGBF) Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3 s Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET IFCOMPM 0Fh W VS1_20 SLLTHDVPM x EIA770M VDETIFSM LOCKSPM ADLCKM VSP 94x5B, VSP 94x7B ADLCKSELM ADLCKCCM CLMPD2SM 107 Table 3-13: Master channel, continued Subadd R/W Take Over Name CLMPD1SM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description 108 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B x Clamping duration CD1, signals 1 Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3 s Deemphase filter FIR component 0000:16 0101: 21 1111: 31 DEEMPFIRM[3] is in 5Fh 10h W VS1_20 DEEMPFIRM[2:0] x x x DEEMPIIRM[1:0] x x Deemphase filter IIR component 000: 5 001: 6 010: 7 011: 8 100: 9 101: 10 110: (reserved) 111: (reserved) DEEMPIIRM[2] is in 5Fh x x x Vertical detection integration time constant 000: 400 clock cycles 001: 375 clock cycles 010: 350 clock cycles 011: 300 clock cycles 100: 250 clock cycles 101: 225 clock cycles 110: 200 clock cycles 111: Automatic x Secam acceptance 0: Disabled 1: Enabled x Secam divider 0: Divide by 4 1: Divide by 2 x x Secam increment 1 00: 2 01: 3 10: 4 11: 5 x x Secam increment 2 00: 1 01: 2 10: 3 11: 4 VDETITCM SECACCM SECDIVM PRELIMINARY DATA SHEET SECINC1M SECINC2M Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name SCMRELM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Secam rejection level 00: 320 01: 384 10: 352 11: 1024 Deemphase filtering for standard detection 0: Weak 1: Strong x x Bell filter FIR component 000: -116 001: -113 010: -110 011: -108 100: -106 101: -104 110: -102 111: -100 BELLPFIRM[2] is in 5Fh x x Bell filter IIR component 000: 8 001: 9 010: 10 011: 11 100: 12 101: 13 110: 14 111: 16 BELLIIRM[2] is in 5Fh Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 11h W VS1_20 DEEMPSTDM x BELLFIRM[1:0] BELLIIRM[1:0] VSP 94x5B, VSP 94x7B SLLTHDVM x x x Slicing level threshold V 000: No offset 001: 4 010: 8 011: 12 101: Adaptive (limited to +-4) 110: Adaptive (limited to +-8) 111: Adaptive (limited to +-12) x x Force line standard at CVBS/RGB front-end 00: Automatic 01: Force 50 Hz 10: Force 60 Hz 11: (Reserved) x Enable limiter 0: Disabled 1: Enabled FLNSTRDM ENLIMM 109 Table 3-13: Master channel, continued Subadd R/W Take Over Name ISHFTM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x I-adjustment for horizontal PLL 00: *1 01: *16 10: *4 11: *8 x Luminance notch-filter 0: Notch-filter enabled 1: Filter bypassed for PAL/NTSC/filter enabled for SECAM To switch-off filter for SECAM, use TNOTCHOFF x x Lowpass for vertical sync-separation 00: None 01: Weak 10: Medium 11: Strong PAL/NTSC delay vs. SECAM (chrominance) 00: PAL/NTSC most left 11: PAL/NTSC most right x Luminance notch-filter 0: Notch-filter according to NOTCHOFFM 1: Notch-filter disabled x x x Burstgate delay (SECAM only) Granularity: 200 ns 000: Most left (-400 ns) 010: No delay 111: Most right (+1 us) x Pal detection: Increment 1 0: +3 1: +2 x Pal detection: Increment 2 0: -1 1: -2 Do not use PALINC2M=1 in combination with PALINC1M=1 x PAL/NTSC identification level 2 0: Less sensitive 1: More sensitive x x Chroma lock-range 00: 425 Hz 01: 463 Hz 10: 505 Hz 11: 550 Hz Description 110 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B NOTCHOFFM VLPM 12h W VS1_20 PALDELM x x TNOTCHOFFM BGPOSM PALINC1M PALINC2M PRELIMINARY DATA SHEET PALIDL2M CLRANGEM Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name NTCHSELM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Luminance notch selection 000: Sharp notch 001: Medium 1 010: Medium 2 011: Broad notch 100: Broad steep notch (PAL, SECAM only) x Notch frequency for 4,250 MHz 0: 4.25 MHz 1: 4.2 MHz Has only effect in SECAM mode x Notch frequency for 4,406 MHz 0: 4.406 MHz 1: 4.356 MHz Has only effect in SECAM mode Memory Controller Master Channel Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET TRAPBLUM TRAPREDM 13h W VSM2_40 INTPROGM x Interlaced or progressive input signal for master channel 0: Interlaced input source 1: Progressive input source (e.g. VGA) x Freeze master picture 0: Live 1: Frozen (no writing of master data) x Vertical resolution master channel for frame based MUP-Mode 0: Field resolution 1: Frame resolution x x Write mode master channel 00: All incoming fields are stored 01: Only A fields are stored 10: Only B fields are stored 11: (Reserved) For DISPMODE=0001 (Snap Shot): 0X, 1X: Writing all fields only to live channel x Write slave data to master memory 0: Slave data is written to slave memory 1: Slave data is written to master memory x x Pixels per line master channel 00: Defined by DISPMODE 01: 448 pixels/line 10: 768 (MOTVALON=0) or 704 (MOTVALON=1) pixels/line 11: 896 pixels/line FREEZEM VERRESM WRITEM VSP 94x5B, VSP 94x7B WRITES2M PIXPLINM 111 Table 3-13: Master channel, continued Subadd R/W Take Over Name WRPOSXM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x Description Horizontal writing position of master picture in the memory Position=(WRPOSXM/32) *128 pixel (FSM mode, MOTVALON=1) Position=(WRPOSXM/2) *32 pixel (FSM mode, MOTVALON=0) Position=(WRPOSXM/2) *32 pixel (SPS, PCF, PCP) Position=WRPOSXM *16 pixel (others) Note: Stepsize depends on selected mode Vertical position of master picture in the memory 00000000: Upper border position Resolution: 1 line x Update snap shot picture 0: Live picture is updated 1: Still picture (snap shot) is updated x x x Synchronisation of film mode signal 000: Synchronisation disabled 001: No delay 010: 1 field delay 101: 4 fields delay 110: (Reserved) 111: (Reserved) x Synchronisation of film mode signal when unsecure 0: Synchronisation disabled when unsecure 1: Synchronisation always active 112 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B 14h W VSM2_40 WRPOSYM x x x x x x x x UPDATESS FMSYN FMSYNUNS 15h W VSM2_40 STANDBYDAC x Standby mode DAC 0: DACs active 1: DACs in standby mode x x YUV-matrix 00: YCbCr 01: YPbPr (CCIR) 10: YPbPr (BTA) 11: (Reserved) x x x x x x x Tint control 1000000: Max negative tint 0000000: No tint 0111111: Max positive tint YUVMAT TINT PRELIMINARY DATA SHEET Micronas Table 3-13: Master channel, continued Subadd 16h R/W W Take Over VSBM1_36 Name RDPNTOFF A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Description Offset of read pointers for port P6 (neighboured lines) 00: 1 line 01: 2 lines 10: 3 lines 11: 4 lines x x x x x x x x x Horizontal read position master Pixel number indicating the start position of reading for the master channel 000000000: First left pixel Effective value: RDPOSXM*2 x x Read mode master channel 00: Reading A and B fields 01: Reading only A fields 10: Reading only B fields 11: (Reserved) For DISPMODE=0001 (Snap Shot): 00: Reading live channel 00: Reading still picture Vertical read position master Line number indicating the start line of reading for the master channel Granularity: 1 line 00000000: First line x Raster shift master Enable raster shift for master channel for joint line free SSC mode 0: Disable raster shift 1: Enable raster shift x Raster shift slave Enable raster shift for slave channel for joint line free SSC mode 0: Disable raster shift 1: Enable raster shift Noise Measurement Master Channel 18h W VSM1_40 NMLINEM x x x x x x x x x Line for noise measurement 0d: Line 2 1d: Line 3 311d: Line 1 (PAL) 261d: Line 1 (NTSC) Lines 3-260 are not standard dependent x x Noise measurement sensitivity 00: *1 01: *2 10: *4 11: *8 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET RDPOSXM READM 17h W VSBM1_36 RDPOSYM x x x x x x x x RSHIFTM RSHIFTS VSP 94x5B, VSP 94x7B NMSENSEM 113 Table 3-13: Master channel, continued Subadd R/W Take Over Name NMPOSM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Description Noise measurement analyze window position 00: 6.3 s 01: 12.6 s 10: 18.9 s 11: 23.7 s 114 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Temporal Noise Reduction Master Channel 19h W VSM2_40 FEMAGM x x x x x Fine error characteristic 00000: Smallest gain 10000: Default (equal to B11 version) 11111: Largest gain x x Secam Dr adjustment 00: 191 01: 194 10: 197 11: 200 x x Secam Db adjustment 00: -55 01: -58 10: -61 11: -64 x Motion detector works on absolute values: 0: Absolute values not calculated 1: Absolute values calculated x Temporal noise reduction 0: Disabled 1: Enabled x Chrominance motion values from: 0: luminance motion detector 1: separate chrominance motion detector x Temporal noise reduction of luminance: 0: Frame based 1: Field based x Motion detection of temporal noise reduction of luminance: 0: Frame based 1: Field based x Temporal noise reduction and motion detection of chrominance: 0: Frame based 1: Field based TNR curve characteristic of luma segment 0 0001: Default x x x x TNR curve characteristic of luma segment 1 1111: Default SDRM SDBM TNRABSM NRONM TNRSELM TNRNR4YM PRELIMINARY DATA SHEET TNRMD4YM TNRNR4CM 1Ah W VSM2_40 TNRYS0M TNRYS1M x x x x Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name TNRYS2M TNRYS3M 1Bh W VSM2_40 TNRYS4M TNRYS5M TNRYS6M TNRYS7M 1Ch W VSM2_40 TNRCS0M TNRCS1M TNRCS2M TNRCS3M 1Dh W VSM2_40 TNRCS4M TNRCS5M TNRCS6M TNRCS7M 1Eh W VSM2_40 TNRYSSM TNRCSSM TNRCLYM x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x x Description TNR curve characteristic of luma segment 2 1111: Default x TNR curve characteristic of luma segment 3 0100: Default TNR curve characteristic of luma segment 4 0100: Default TNR curve characteristic of luma segment 5 0100: Default TNR curve characteristic of luma segment 6 0000: Default x TNR curve characteristic of luma segment 7 0000: Default TNR curve characteristic of chroma segment 0 0001: Default TNR curve characteristic of chroma segment 1 1111: Default TNR curve characteristic of chroma segment 2 1111: Default x TNR curve characteristic of chroma segment 3 0100: Default TNR curve characteristic of chroma segment 4 0100: Default TNR curve characteristic of chroma segment 5 0100: Default TNR curve characteristic of chroma segment 6 0000: Default x TNR curve characteristic of chroma segment 7 0000: Default TNR start value of luma LUT 1111: Default TNR start value of chroma LUT 1111: Default TNR luminance classification: 0000: Strong noise reduction 1111: Slight noise reduction x x x x TNR chrominance classification: 0000: Strong noise reduction 1111: Slight noise reduction Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B TNRCLCM 115 Table 3-13: Master channel, continued Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Preframe Generator Master Channel 1Fh W VSM2_40 YBORDERM x x x x Y border value of display Granularity: 16 0000: 0 0001: 16 1111: 240 x x x x U border value of display Granularity: 16 0000: 0 0001: 16 0111: 112 1000: -128 1111: -16 x x x x V border value of display Granularity: 16 0000: 0 0001: 16 0111: 112 1000: -128 1111: -16 x x x x Multi picture force background lines bottom Number of lines of background color to be appended 0000: 0 lines 1111: 15 lines Multi picture force background pixels right Number of pixels of background color to be appended 00: 0 pixels 01: 16 pixels 10: 32 pixels 11: 48 pixels x x x x Multi picture force background lines top Number of lines to be overwritten with background color from top 0000: 0 lines 1111: 15 lines x x General purpose GP0 (pin 83) 00: Tristate 01: Tristate 10: Low level 11: High level Note: QFP144 only x Channel for noise measurement (picture) 0: Master 1: Slave Description 116 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B UBORDERM VBORDERM MPFBLBM 20h W VSM2_40 MPFBPRM x x MPFBLTM PRELIMINARY DATA SHEET GP0 NMCHAN Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name SLOWVAR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Modification of NOISE 0: NOISE~NOISE_SUM_REG 1: NOISE=incremental steps x Modifies GAP for increasing homogenous regions AUTOGAP==1&&STAT_SIZE==0: GAP+=8; AUTOGAP==1&&STAT_SIZE==1: GAP+=4; AUTOGAP==1&&STAT_SIZE==2: GAP+=2; AUTOGAP==0 || STAT_SIZE==3: GAP+=0; x x x x Update rate UPDATERATEM*32+31 fields are necessary for the next update 0000: 31 1111: 511 Background generator in pre-frame generator 0: Disabled 1: Enabled x x x x x Multi picture force background pixels left Number of pixels to be overwritten with background color from left Granularity: 2 pixel 00000: 0 pixels 11111: 62 pixels x x x x x x x x Global motion detection stock ticker threshold value 00111100: Default Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET AUTOGAP UPDATERATEM 21h W VSM2_40 FRCBGNDM x MPFBPLM GMSTTHV Horizontal Prescaler Master Channel 22h W VSM1_40 FRCMMODM x Mosaic mode generator 0: Disabled 1: Enabled x Active pixel enable select 0: Count clock cycles (recommended for CVBS/RGB input) 1: Count active pixels (recommended for ITU656 input) x x x x x x x x x x x x Control signal for HSCALE in horizontal pre-scaler Subsampling factor by prescaler is (int) 0: 1 (int) 2048: 1.5 (720 pixels) (int) 2371: 1.578 (->684 pixels) (int) 4095: 2 (540 pixels) Horizontal antialiasing filter 00: Filter bypassed 01: Force characteristic weak 10: Force characteristic strong 11: Automatic characteristic (weak or strong) Note: For normal CVBS/RGB full-screen, filter should be set to weak or automatic characteristic. For ITU656 full-screen input, filter should be bypassed. Strong characteristic is for split-screen and PiP only. VSP 94x5B, VSP 94x7B APENSELM HSCPRESCM 23h W VSM1_40 HAAPRESCM x x 117 Table 3-13: Master channel, continued Subadd R/W Take Over Name HDCPRESCM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x Description Horizontal pre-scaler decimates by 0000: 1 0001: 2 0010: 3 0011: 4 0100: 6 0101: 8 0110: 12 0111: 16 1000: 24 1001: 32 x x x x x x x x x Active pixel per line (pre scaler) Describes, how many decimated active pixels are generated. Granularity: 2 pixels (int) 0: 0 pixels (int) 342: 684 pixels (int) 511: 1022 pixels Line memories availability 0: Available for vertical prescaler 1: Available for motion-detector x x General purpose GP2 (pin 85) 00: Tristate 01: Tristate 10: Low level 11: High level Note: QFP144 only x x General purpose GP1 (pin 84) 00: Tristate 01: Tristate 10: Low level 11: High level Note: QFP144 only x x x x x x x x x x Not active pixel per line (pre scaler) Granularity: 2 clock cycles (int) 0: 0 pixels (int) 100: 200 pixels (int) 1023: 2046 pixels 118 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B APPLIPM 24h W VSM1_40 MOTONM x GP2 GP1 NAPPLIPM PRELIMINARY DATA SHEET Vertical Prescaler Master Channel 25h W VSM1_40 VAAPRESCM x Vertical lowpass filter (pre-scaler) 0: Disabled 1: Enabled x x x x x Vertical peaking 00000: Maximum vertical peaking (enhancement) 10000: Vertical peaking has no effect (flat) 11111: Maximum attenuation (damping) VPKPRESCM Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name VCRPRESCM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Shift of chrominance signal 0: No shift 1: One line upward (e.g. for VCR) x x x x x x x x x Not active lines per field input (int) 0: Shift is 0 (int) 22: Shift is 22 lines (int) 511: Shift is 511 lines (max. shift is 1 field) Vertical prescaler by-pass 0: Vertical pre scaler enabled 1: Vertical pre scaler by-passed x x x x Vertical pre-scaler decimates by 0000: 1 0001: 2 0010: 3 0011: 4 0100: 6 0101: 8 0110: 12 0111: 16 1000: 24 1001: 32 x x x x x x x x x x Active lines per field (input processing) (int) 0: No active line (int) 288: 288 active lines (int) 1023: 1023 lines Horizontal start position of active measurement area 00: 0 01: 128 10: 256 11: 384 x x Duration of active measurement area 00: 400 01: 600 10: 800 11: 1200 x x x x x x x x x x x x Control signal for VSCALE in vertical pre-scaler (int) 0: Scaling factor is 1 (int) 4095: Scaling factor is 2 Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET NALPFIPM 26h W VSM2_40 VPREBYPM x W VDCPRESCM ALPFIPM 27h W VSM2_40 HORPOSNM x x VSP 94x5B, VSP 94x7B HORWIDTHNM VSCPRESCM Global Motion Detection Master Channel 28h W VSM2_40 GMSTTH[1] GMTHUM x x x x x x x x GMD stock ticker segment threshold (int) 0: Default GMD spatial hysteresis: upper threshold (int) 68: Default 119 Table 3-13: Master channel, continued Subadd R/W Take Over Name GMSTSS GMASM 29h W VSM2_40 GMSTTH[0] GMTHLM GMSTEN x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x x GMD stock ticker segment start (int)5: Default] x GMD Amount of still pictures (int) 29: Default (see 28h) GMD spatial hysteresis: lower threshold (int) 67: Default GMD stock ticker enable 0: disabled 1: enabled x x x x x x x x x x x x x x x x x x x x x GMD stock ticker segment length (int)1: Default] x GMD amount of motion pictures (int) 16: Default GMD spatial hysteresis: upper threshold (int) 11: Default x GMD spatial hysteresis: lower threshold (int) 10: Default Description 120 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B GMSTSL GMAMM 2Ah W VSM2_40 GSTHUM GSTHLM Film Mode Detection Master Channel 2Bh W VSM2_40 MDVFFON x Motion detection vertical filter for frame difference 0: Disabled 1: Enabled x FMD still detection on/off Forces camera mode, if still sequence is d 0: Disabled 1: Enabled x x x x x FMD threshold for dc level (int) 7: Default] FMDSON FMDCTH FMRES PRELIMINARY DATA SHEET FMD reset 0: Not forced 1: Forced to camera mode x FMD temporal hysteresis on/off 0: History length = 2 * (FMMEMHIS+1) 1: History length = 2 * (FMMEMHIS+1), camera-> film mode History length = 1* (FMMEMHIS+1), film -> camera mode x FMD trash counter on/off If trash counter > 120, the film mode detector switches automatically to camera mode. 0: Disabled 1: Enabled FMTHYON FMTHRON Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name FMSCALEL A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Limitation of lower boundary: 00: 16 01: 32 10: 64 11: 64 x x Limitation of upper boundary: 00: 256 01: 128 10: 64 11: 64 x x Region to be investigated by the film mode detector: 00: Upper half (line 0 to line 127) 01: Lower half (line 128 to last line) 10: Complete picture 11: Complete picture History length of film mode detection (int) 3: Default x x x x x x x x x x x FMD threshold for absolute value (int) 10: Default x FMD threshold for difference value (int) 15: Default Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET FMSCALEU FMREGION 2Ch W VSM2_40 FMMEMHIS FMATH FMDTH x x x x Motion Detection Master Channel 2Dh W VSM2_40 TFLDDON x Temporal field delay on 0: Two bit of field delayed motion values 1: One bit current motion value and one bit field delayed VSP 94x5B, VSP 94x7B THRGM SVALFI x x x x x x x Threshold of frame difference in MD for global motion detection: (int) 8: Default Sensitivity factor of field difference 00 : Factor 1(maximum) 01 : Factor 2 10 : Factor 4 11 : Factor 8 (minimum) x x Sensitivity of frame difference 00 : Factor 1(maximum) 01 : Factor 2 10 : Factor 4 11 : Factor 8 (minimum) x x Automatic movie mode detection In case of movie mode, the motion detection will be automatically switched to 00 : Disabled 01 : Disabled 10 : Only frame difference 11 : No motion SVALFR AMMON 121 Table 3-13: Master channel, continued Subadd R/W Take Over SWGM Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Description Switch input value for global motion detection 00: Frame difference, influenced by motion detection 01: Frame difference, not influenced by motion detection 10: Field difference, influenced by motion detection 11: Field difference, not influenced by motion detection x x Temporal filter delay time 00: Factor 0 01: Factor 1 10: Factor 2 11: Factor 3 Switch double temporal filter delay time 00: Single delay time 01: 4 times delayed 10: 8 times delayed 11: 16 times delayed x x x x x x x x x x x Threshold of field difference in MD for movie mode detection: (int) 8: Default (See MSB) Threshold for frame difference look up table: (int) 3: Default Temporal filter 0: Disabled 1: Enabled x x x x x x Threshold for field difference look up table: (int) 8: Default Sensitivity of line differences 00 : Factor 4 (maximum) 01 : Factor 8 10 : Factor 16 11 : Factor 32 (minimum) x x x x x Thresholds of line difference look up table: (int) 4: Default Frame or frame and field difference for motion detection 0 : Based on frame difference only 1 : Based on frame and field difference Note: In case of AMMON >1 and no movie mode, the motiondetection is still defined by FRAFION x x x x x x x x Threshold for frame difference look up table: (int) 4: Default x Threshold for field difference look up table: (int) 6: Default 122 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B TFDT 2Eh W VSM2_40 DTFDT[1] x THRMOV DTFDT[0] THFR0 TFON THFI0 2Fh W VSM2_40 SVALLI THLI0 FRAFION PRELIMINARY DATA SHEET THFR1 Micronas THFI1 Table 3-13: Master channel, continued Subadd 30h R/W W Take Over VSM2_40 THLI1 THFR2 THFI2 31h W VSM2_40 THLI2 THFR3 THFI3 x x x x x x x x x x x x x x x Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x x x x x x x x x Description Threshold for line difference look up table: (int) 8: Default Threshold for frame difference look up table: (int) 6: Default x Threshold for field difference look up table: (int) 18: Default Threshold for line difference look up table: (int) 12: Default Threshold for frame difference look up table: (int) 10: Default x Threshold for field difference look up table: (int) 28: Default Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Noise Measurement in Picture Content 32h W VSM1_40 GAPM x x x x x x Threshold for homogenous areas 000000: 0 111111: 63 x x Fixes sensitivity of measurement 00: NOISE_SUM_REG=NOISE_SUM*0.5 01: NOISE_SUM_REG=NOISE_SUM 10: NOISE_SUM_REG=NOISE_SUM*2 11: NOISE_SUM_REG=NOISE_SUM*4 x x x x x x x x Offset for eliminating standard noise 00000000: 0 11111111: 255 SENSITIVM OFFSET VSP 94x5B, VSP 94x7B Horizontal Post Scaler Master Channel 33h W VSBM2_36 HPANONM x Horizontal panorama mode 0: Panorama disabled 1: Panorama enabled x Disable border detection (postscaler) 0: Border detection active 1: Border detection not active x Chrominance delay 0: No delay 1: Half-pixel delay x x x x x x x x x x x x Horizontal scaling factor for post scaler (int) 1024: Upsampling factor is 4 (int) 2910: Upsampling factor is 1.407 (int) 4095: Upsampling factor is 1 DBDHPOSM CDELHPOSM HSCPOSCM 123 Table 3-13: Master channel, continued Subadd 34h R/W W Take Over VSBM2_36 Name HSEG1M[10:5] A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x Description Beginning of segment 1 for horizontal panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start x x x x x x x x x Horizontal post-scaler increment 0 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels (See 33h) x x x x x x x x x Horizontal post-scaler increment 1 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels Beginning of segment 2 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start x x x x x x x x x Horizontal post-scaler increment 2 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels (see 36h) x x x x x x x x x Horizontal post-scaler increment 3 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels Beginning of segment 3 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start x x x x x x x x x Horizontal post-scaler increment 4 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels (see 38h) x x x x x x x x x x x Beginning of segment 4 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start 124 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B HINC0M 35h W VSBM2_36 HSEG1M[4:0] HINC1M x x x x x 36h W VSBM2_36 HSEG2M[10:5] x x x x x x HINC2M 37h W VSBM2_36 HSEG2M[4:0] HINC3M x x x x x 38h W VSBM2_36 HSEG3M[10:5] x x x x x x HINC4M PRELIMINARY DATA SHEET 39h W VSBM2_36 HSEG3M[4:0] HSEG4M x x x x x Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Vertical Post Scaler Master Channel 3Ah W VSBM2_36 VPANONM x Vertical panorama mode 0: Panorama disabled 1: Panorama enabled x Vertical upsampling unit 0: No doubling 1: Number of output lines is doubled by interpolation x x x x x x x x x x x x x x Vertical scaling factor for post scaler (int) 256: Upsampling factor is 16 (int) 4096: Up/ downsampling factor is 1 (int) 8192: Downsampling factor is 2 (int) 16383: Downsampling factor is 4 Beginning of segment 1 for vertical panorama mode (int) 0: 0 lines behind picture start (int) 1023: 1023 lines behind picture start (VDOUBLE=0) (int) 1023: 1023*2 lines behind picture start (VDOUBLE=1) x x x x x x x x x Vertical post-scaler increment 0 100000000: Picture becomes bigger 000000000: No action 011111111: Picture becomes smaller (See 3Bh) x x x x x x x x x Vertical post-scaler increment 1 100000000: Picture becomes bigger 000000000: No action 011111111: Picture becomes smaller Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET VDOUBLEM VSCPOSCM 3Bh W VSBM2_36 VSEG1M[9:5] x x x x x VINC0M 3Ch W VSBM2_36 VSEG1M[4:0] VINC1M x x x x x VSP 94x5B, VSP 94x7B 3Dh W VSBM2_36 VSEG2M[9:5] x x x x x Beginning of segment 2 for vertical panorama mode (int) 0: 0 lines behind picture start (int) 1023: 1023 lines behind picture start (VDOUBLE=0) (int) 1023: 1023*2 lines behind picture start (VDOUBLE=1) x x x x x x x x x Vertical post-scaler increment 2 100000000: Picture becomes bigger 000000000: No action 011111111: Picture becomes smaller (See 3Bh) x x x x x x x x x Vertical post-scaler increment 3 100000000: Picture becomes bigger 000000000: No action 011111111: Picture becomes smaller Invert skew signal from input PLL 0: No inversion 1: Inversion VINC2M 3Eh W VSBM2_36 VSEG2M[4:0] VINC3M x x x x x 3Fh W VSBM2_36 INVSKEW x 125 Table 3-13: Master channel, continued Subadd R/W Take Over Name ARTSYNC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Description LL-PLL input 0: From CVBS input directly (PLL parallel mode) 1: From synthesizer x Input sync synthesizer source 0: Use sync from front-end PLL (PLL serial mode) 1: Use itu656 sync x Secam v-delay 0: Zero delay 1: Delay v-channel by 1 pixel x x PALDET identification level 00: 240 01: 192 10: 128 11: 64 x x x x x x x x x Vertical Post-scaler increment 4 100000000: Picture becomes bigger 000000000: No action 011111111: Picture becomes smaller Vertical post-scaler phase offset Granularity: 16 (int) 0: Vertical offset for dto is 0 (int) 255: Vertical offset for dto is 4080 x x x x x x x x x x Beginning of segment 3 for vertical panorama mode (int) 0: 0 lines behind picture start (int) 1023: 1023 lines behind picture start (VDOUBLE=0) (int) 1023: 1023*2 lines behind picture start (VDOUBLE=1) (See 40h) x x x x x x x x x x Beginning of segment 4 for vertical panorama mode (int) 0: 0 lines behind picture start (int) 1023: 1023 lines behind picture start (VDOUBLE=0) (int) 1023: 1023*2 lines behind picture start (VDOUBLE=1) 126 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B ITUSYNC SECDELM PALDETIDLM VINC4 40h W VSBM2_36 VOFPOSC[7:3] x x x x x VSEG3M 41h W VSBM2_36 VOFPOSC[2:0] VSEG4M x x x PRELIMINARY DATA SHEET Output Data Controller Master Channel 42h W VSBM2_36 DPBRT x x x x x x Brightness 000000: + 48 LSB 110000: no offset 111111: - 15 LSB x x x x x x Contrast 000000: 0 100000: 1 111111: 63/32 DPCON Micronas Table 3-13: Master channel, continued Subadd R/W Take Over DPCNS Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Contrast noise shaper 0: Disabled 1: Enabled Peak-white reduction 00000: No reduction 11111: Max. reduction x x x x x x x x Measured sync amplitude 00000000: Smallest sync 11111111: Largest sync Peak-white reduction 00000: No reduction 11111: Max. reduction Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 43h R VS1_20 PWADJCNTM x x x x x MINVM 44h R VS2_20 PWADJCNTS x x x x x MINVS x x x x x x x x Measured sync amplitude 00000000: Smallest sync 11111111: Largest sync Automatic freerun when sync-separartion not stable 00: Disabled (keep H/V locked, if selected) 01: Vertical freerun when not stable 10: Horizontal freerun when not stable 11: Horizontal and vertical freerun when not stable Depends on color decoder which is selected to be master with SELMASTER and SELSM 45h W VSBM2_36 AUTOFRRN x x LPFIPMD x Lines per field method 0: Back-end 1: Front-end x Vertical ODC line counting 0: Field delay 1: Frame delay x Back-end field inversion 0: No inversion 1: Inversion x x x x x x x x x x x Horizontal position inside active picture area (int) 32: Most left display position (int) 4095: Most right display position Values smaller than 32 are not usable Secam v-delay 0: Zero delay 1: Delay v-channel by 1 pixel VSP 94x5B, VSP 94x7B VINMTHD FIELDBINV HORPOSM 46h W VSBM2_36 SECDELS x 127 Table 3-13: Master channel, continued Subadd R/W Take Over Name PALDETIDLS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x PALDET identification level 00: 240 01: 192 10: 128 11: 64 x x x x x x x x x x Vertical position inside active picture area Granularity: 1 line (FMODE=0) or 2 lines (FMODE=1) (int) 0: Most top display position (int) (2047): Most bottom display position x Horizontal picture width Granularity: 2 pixels (int) 0: No display (int) 960: Default (int) 2047: 4094 pixels No fine horizontal synchronization 0: Horizontal synchronization 1: Horizontal synchronization without finer steps x x x x x x x x x x x Vertical picture width (int) 0: 0 lines (int) 288: Default (int) 2047: 2047 lines Description 128 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VERPOSM 47h W VSBM2_36 HORWIDTHM x x x x x x x x x x 48h W VSBM2_36 NOFHSYNC x VERWIDTHM Picture Improvement Master Channel 49h W VSBM2_36 PKCTIBPM x x Peaking factor for CTI (bandpass part) 00: 2 (CTI bp off) 01: 16 10: 24 11: 32 x x Peaking factor for CTI (highpass part) 00: 2 (CTI hp off) 01: 16 10: 24 11: 32 x Luminance transition improvement 0: Disabled 1: Enabled x x 1st adaptive peaking factor (bandpass part) 0000: 0.5 0100: 2.5 1111: 8 PKCTIHPM PRELIMINARY DATA SHEET LTIM APK1BPM[1:0] Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name APK2BPM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description 2nd adaptive peaking factor (bandpass part) 000: 1 001: 2(peaking bp off) 011: 4 111: 8 x x Peaking denoising threshold (bandpass part) 00: 0 (denoising off) 01: 2 10: 4 11: 8 x x 2nd peaking threshold (bandpass part) 00: 0 01: 4 10: 8 11: 16 x x Turningpoint threshold for CTI 00: 1 01: 2 10: 3 11: 4 1st adaptive peaking factor (highpass part) 0000: 0.5 0100: 2.5 1111: 8 x x x 2nd adaptive peaking factor (highpass part) 000: 1 001: 2 (peaking hp off) 011: 4 111: 8 x x Peaking denoising threshold (highpass part) 00: 0 (denoising off) 01: 2 10: 4 11: 8 x x 2nd peaking threshold (highpass part) 00: 0 01: 4 10: 8 11: 16 x Disable border detection (picture improvement) 0: Border detection active 1: Border detection not active x x (See 49h) Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET ATH1BPM ATH2BPM THEM 4Ah W VSBM2_36 APK1HPM[1:0] x x APK2HPM VSP 94x5B, VSP 94x7B ATH1HPM ATH2HPM DBDPICIM APK1BPM[3:2] 129 Table 3-13: Master channel, continued Subadd R/W Take Over Name APK1HPM[3:2] CORONM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x (See 49h) Coring or denoising for low amplitudes 0: Coring off, denoising on 1: Coring on, denoising off Description 130 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Pixel Mixer Master Channel 4Bh W VSBM2_36 YFRAMEM UFRAMEM VFRAMEM x x x x x x x x x x x Luminance value for the master frame (4MSB) 0001: Default value (yields value 0001 00000=32) Chrominance value for the master frame (4MSB) 0000: Default value (yields value 0000 00000=0) x Chrominance value for the master frame (4MSB) 0000: Default value (yields value 0000 00000=0) Dynamic Contrast Improvement Master Channel 4Ch W VSDCI_36 SPIXELM x x x x x Start pixel number for analysis window START= SPIXEL x 8 (int) 2: 16 pixels x x x x x x x End pixel number for analysis window END = EPIXEL x 8 + 512 (int) 54: 944 pixels x Enable split-screen demo mode 0: Disabled 1: Enabled x Scanning mode for DCI 0: Interlaced 1: Progressive x Color saturation compensation 0: Disabled 1: Enabled x Digital contrast improvement (DCI) 0: Disabled 1: Enabled The analysis continues also if DCI_ONM = 0, but it has no effect to the output. 4Dh W VSDCI_36 SLINEM x x x x Start line number for analysis window START = SLINE x 8 (int) 1: 8 lines x x x x x x End line number for analysis window END = ELINE x 8 + 128 (int) 55: 568 lines EPIXELM ENA_DEMOM SCAN_IDM CSC_ONM DCIONM PRELIMINARY DATA SHEET ELINEM Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name DCI_CORM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x Description DCI coring level for adaptive signal split (int) 0: No coring (int) 5: Default (int) 31: Max. coring x DCI analysis on/off (only for test purpose) 0: Disabled 1: Enabled x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x MAU 53h W VSBM1_36 MVCOFA0 x x Motion value factor 0 for actual field for calculating motion result without accumulator 00: *0 01: *1 10: *2 11: *3 x x x x x x x x x x x x x x Total number of active pixel per line (int) 960: 960 pixel x Filter time constant for average brightness (int) 16: 16 frames of settling tine of DCI analysis Sensitivity of average brightness analysis (ABA) (int) 40: Default x Light sample weighting factor (int) 2: Default Sensitivity of dark sample distribution analysis (DSDA) (int) 40: Default x Filter time constant for dark sample distribution (int) 16: Default Correction factor SENSBS x 32/DYTC (int) 75: Default x Dark area size for DSDA (int) 17: Default Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET FREEZE_ANLM 4Eh W VSDCI_36 PIXELPLINEM AB_FTCM 4Fh W VSDCI_36 SENSWSM LSWFM 50h W VSDCI_36 SENSBSM DSFTCM 51h W VSDCI_36 ERRORCMPM DYTCM VSP 94x5B, VSP 94x7B 52h W VSDCI_36 PK_FTCM PEAK_SIZEM Filter time constant for frame peak value (int) 16: Default x Peak area size. Range [0...9] (internally limited to max.9] (int) 4: Default 131 Table 3-13: Master channel, continued Subadd R/W Take Over Name MVCOFA1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Motion value factor 1 for actual field for calculating motion result without accumulator 000: *1 001: *2 010: *3 011: *4 100: *5 101: *6 110: *7 111: *8 x x Motion value factor 0 for previous field for calculating motion result without accumulator 00: *0 01: *1 10: *2 11: *3 x x x Motion value factor 1 for previous field for calculating motion result without accumulator 000: *1 001: *2 010: *3 011: *4 100: *5 101: *6 110: *7 111: *8 x x Motion value divider for actual field for calculating motion result without accumulator 00: /1 01: /2 10: /4 11: /8 x x Motion value divider for previous field for calculating motion result without accumulator 00: /1 01: /2 10: /4 11: /8 x x Motion value divider for calculating motion result without accumulator 00: /1 01: /2 10: /4 11: /8 132 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B MVCOFP0 MVCOFP1 MVDIVA MVDIVP PRELIMINARY DATA SHEET MVDIVR Micronas 54h W VSBM1_36 MVMODE x Method selection for creation the motion value result 0: Accumulator method 1: New method w/o accumulator Table 3-13: Master channel, continued Subadd R/W Take Over Name MVREFPOS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Description Indicating the reference position for MvMode = 0 0: Delayed value 1: Actual value x Soft mix method selection 0: 2 field access 1: 3 field access (Only valid in field jam mode) x Enabling the fixed motion value 0: Use incoming motion values 1: Use value adjusted by MvFixVal x x x x Fixed motion value used if MvFixEna is enabled Global motion film mode fallback enable 0: Global motion fallback is disabled for film mode phases 1: Global motion fallback is enabled for film mode phases x Global still film mode fallback enable 0: Global still fallback is disabled for film mode phases 1: Global still fallback is enabled for film mode phases x Global still enable 0: Off 1: On x Motion value visibility enable 0: Off 1: On x Field jam selection inversion Inverts the field jam selection output bit 0: No inversion 1: Inversion x Motion value chrominance UV hold switch 0: Use new motion value on each incoming motion value 1: Use motion value for u channel for v channel also (hold) Dynamic operation table entry: Motion sequence when video mode active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET SMMODE MVFIXENA MVFIXVAL GMFMFBENA GSFMFBENA GSTILLENA MVVISENA FJSELLNV VSP 94x5B, VSP 94x7B MVCHOLD 55h W VSBM1_36 DYNOPMSV x x x 133 Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPITV A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Interpolation type when video mode active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when video mode active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when video mode active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when 2-2-pull-down (PAL) film mode phase 0 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: Interpolation type when 2-2-pull-down (PAL) film mode phase 0 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-2-pull-down (PAL) film mode phase 0 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-2-pull-down (PAL) film mode phase 0 active 0: Get old stored field data 1: Get new incoming field data 134 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DYNOPSMV DYNOPFJV DYNOPMSP0 DYNOPITP0 DYNOPSMP0 PRELIMINARY DATA SHEET DYNOPFJP0 Micronas Table 3-13: Master channel, continued Subadd 56h R/W W Take Over VSBM1_36 Name DYNOPLSGM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Line scan pattern sequence when global motion active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA x x x Dynamic operation table entry: Line scan pattern sequence when global still active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA x Linescan pattern freerun 0: lsp freerun disabled 1: lsp freerun enabled x x x Dynamic operation table entry: Line scan pattern sequence when video mode active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA x x x Dynamic operation table entry: Line scan pattern sequence when 2-2-pull-down (PAL) film mode phase 0 active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET DYNOPLSGS OPPHASEFR DYNOPLSV VSP 94x5B, VSP 94x7B DYNOPLSP0 135 Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPLSP1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Description 136 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B x Dynamic operation table entry: Line scan pattern sequence when 2-2-pull-down (PAL) film mode phase 1 active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA Dynamic operation table entry: Line scan pattern sequence when 2-3-pull-down (NTSC) film mode phase 0 active 000: LspSeqAAAA 001: LspSeqBBBB 010: LspSeqAABB 011: LspSeqABBA 100: LspSeqBBAA 101: LspSeqBAAB 110: LspSeqABAB 111: LspSeqBABA 57h W VSBM1_36 DYNOPLSN x x x FMFORCETRIG x Force the actual adjusted FM phase (FmForce) if strictly force of FM PAL or FM NTSC is selected (FmForce = 1/2/3/4/5/6/7) As long as the trigger is set the phase is forced to the selected value On I2C_FmForce = 0/8/9/10/11-15 this parameter has no effect 0: Phase forcing is disabled 1: Phase forcing is enabled x x Field jam mode selector 00: Field jam disabled 01: Field jam enabled but always soft mix mode is activated 10: Field jam enabled and forced 11: Field jam enabled with adaptive behavior to film mode generator X Control signal for the line select generator output (int) 0: LineSel is NOT altered (int) 1: LineSel is inverted FJMODE NEGLINESEL PRELIMINARY DATA SHEET Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name FMFORCE A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x Description Indicates film mode force/hold method 0000: Strictly force VIDEO 0001: Strictly force FM PAL (initial phase 0) 0010: Strictly force FM PAL (initial phase 1) 0011: Strictly force FM NTSC (initial phase 0) 0100: Strictly force FM NTSC (initial phase 1) 0101: Strictly force FM NTSC (initial phase 2) 0110: Strictly force FM NTSC (initial phase 3) 0111: Strictly force FM NTSC (initial phase 4) 1000: Auto detect & hold VIDEO 1001: Auto detect and hold FM PAL 1010: Auto detect & hold FM NTSC 1011: Auto detect and hold VIDEO or FM PAL 1100: Auto detect and hold VIDEO or FM NTSC 1101: Auto detect and hold FM PAL or FM NTSC 1110: Force/hold disabled, use FM detector result 1111: Force/hold disabled, use FM detector result x Control signal for the line select generator initialisation (int) 0: Init value for LineSel is 0 (int) 1: Init value for LineSel is 1 x x x Chrominance static operation motion sequence If enabled use always this motion sequence for chrominance signals 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x Chrominance static operation motion sequence enable switch Enable signal for separate static chrominance motion sequence 0: Use motion sequence from dynamic operation table 1: Use StatOpMsC motion sequence for chroma channel only x x x Dynamic operation table entry: Motion sequence when global motion active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET INITLINESEL STATOPMSC VSP 94x5B, VSP 94x7B STATOPMSCENA 58h W VSBM1_36 DYNOPMSGM 137 Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPITGM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Interpolation type when global motion active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when global motion active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when global motion active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when global still active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: Interpolation type when global still active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when global stillactive 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when global still active 0: Get old stored field data 1: Get new incoming field data 138 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DYNOPSMGM DYNOPFJGM DYNOPMSGS DYNOPITGS DYNOPSMGS PRELIMINARY DATA SHEET DYNOPFJGS Micronas Table 3-13: Master channel, continued Subadd 59h R/W W Take Over VSBM1_36 Name DYNOPMSN0 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Motion sequence when 2-3-pull-down (NTSC) film mode phase 0 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: interpolation type when 2-3-pull-down (NTSC) film mode phase 0 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-3-pull-down (NTSC) film mode phase 0 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-3-pull-down (NTSC) film mode phase 0 active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when 2-3-pull-down (NTSC) film mode phase 1 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: Interpolation type when 2-3-pull-down (NTSC) film mode phase 1 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET DYNOPITN0 DYNOPSMN0 DYNOPFJN0 DYNOPMSN1 VSP 94x5B, VSP 94x7B DYNOPITN1 139 Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPSMN1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x Description Dynamic operation table entry: Soft mix enable switch position when 2-3-pull-down (NTSC) film mode phase 1 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-3-pull-down (NTSC) film mode phase 1 active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when 2-3-pull-down (NTSC) film mode phase 2 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: interpolation type when 2-3-pull-down (NTSC) film mode phase 2 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-3-pull-down (NTSC) film mode phase 2 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry Field jam switch position when 2-3-pull-down (NTSC) film mode phase 2 active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when 2-3-pull-down (NTSC) film mode phase 3 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA 140 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DYNOPFJN1 5Ah W VSBM1_36 DYNOPMSN2 DYNOPITN2 DYNOPSMN2 DYNOPFJN2 PRELIMINARY DATA SHEET DYNOPMSN3 Micronas Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPITN3 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Interpolation type when 2-3-pull-down (NTSC) film mode phase 3 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-3-pull-down (NTSC) film mode phase 3 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-3-pull-down (NTSC) film mode phase 3 active 0: Get old stored field data 1: Get new incoming field data x x x Dynamic operation table entry: Motion sequence when 2-3-pull-down (NTSC) film mode phase 4 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: Interpolation type when 2-3-pull-down (NTSC) film mode phase 4 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-3-pull-down (NTSC) film mode phase 4 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-3-pull-down (NTSC) film mode phase 4 active 0: Get old stored field data 1: Get new incoming field data Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET DYNOPSMN3 DYNOPFJN3 5Bh W VSBM1_36 DYNOPMSN4 DYNOPITN4 VSP 94x5B, VSP 94x7B DYNOPSMN4 DYNOPFJN4 141 Table 3-13: Master channel, continued Subadd R/W Take Over Name DYNOPMSP1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x Description Dynamic operation table entry: Motion sequence when 2-2-pull-down (PAL) film mode phase 1 active 000: MotSeqAAAA 001: MotSeqBBBB 010: MotSeqAABB 011: MotSeqABBA 100: MotSeqBBAA 101: MotSeqBAAB 110: MotSeqABAB 111: MotSeqBABA x x x Dynamic operation table entry: interpolation type when 2-2-pull-down (PAL) film mode phase 1 active 000: IpolTypeAB 001: IpolTypeLineDb 010: IpolTypeLin2 011: (reserved) 100: IpolTypeLin4 x Dynamic operation table entry: Soft mix enable switch position when 2-2-pull-down (PAL) film mode phase 1 active 0: Soft mix disabled 1: Soft mix enabled x Dynamic operation table entry: Field jam switch position when 2-2-pull-down (PAL) film mode phase 1 active 0: Get old stored field data 1: Get new incoming field data x ProgressivePicture Improvement 0: off 1: on x x x x x x x x x x x x x x x x HDTO freerunning frequency Granularity=103 Hz (int) 33981 (minimum: nominal pixel clock= 3.5 MHz) (int) 349525 (nominal pixel clock= 36 MHz) (int) 388362 (maximum: nominal pixel clock= 40 MHz) (see 57h) x Reduce hold-range of LLPLL in unlocked HPLL state 0: Disabled 1: Enabled x Freerunning clocks 0: From fixed clock divider 1: From freerunning DTO (adjustable clocks) x x x (See 5Dh) 142 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DYNOPITP1 DYNOPSMP1 DYNOPFJP1 5Ch GCMON 5Dh W NTO FRINC[18:3] PRELIMINARY DATA SHEET 5Eh W NTO FJMODE FRZLIMLR x x FRFIX Micronas FRINC[2:0] Table 3-13: Master channel, continued Subadd 5Fh R/W W Take Over VS1_20 Name INCOMBC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x Chroma Input for comb filter 00: ADC 2 01: Blue ADC 10: Red ADC 11: (Reserved) x x x x x x (See 11h) (See 11h) (See 10h) (See 10h) Automatic standard detection priority 50 Hz 00: PAL B 01: SECAM 10: (Reserved) 11: Automatic x x Automatic standard detection priority 60 Hz 00: NTSC M 01: NTSC44/PAL60 10: (Reserved) 11: Automatic x Reference for sync-AGC 0: Normal reference 1: Referenc reduced by 2% x AGC peak-white counter reset 0: No reset 1: Reset x De-skewing of H50 pulse 0: Disabled 1: Enabled x x AGC hysterisys 00: Broad 01: Medium 1 10: Medium 2 11: Small Vertical length measurement with vertical pulse detection 0: Disabled 1: Enabled x Vertical pulse gating 0: Disabled 1: Enabled x x x x x Slicer line number CC or WSS Description Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET BELLIIRM[2] BELLFIRM[2] DEEMPIIRM[2] DEEMPFIRM[3] AMSTD50M AMSTD60M SYNCGAINM AGCPWRESM VSP 94x5B, VSP 94x7B H50SKEW AGCTHDM 60h W VS1_20 MVPM x MVPGM SLNCW 143 Table 3-13: Master channel, continued Subadd R/W Take Over Name SLNRUW DDR_CC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 x x x x x x Slicer line number US-WSS Double data rate CC (test only) 0: Normal data-rate 1: Double data-rate x Clamp signal adapation 0: Disabled 1: Enabled Note: MUST be enabled when internal 4H comb-filter is used for master. MUST be disabled, if no or external comb-filter is used for master. x Combfilter compensation delay (ADC2) 0: Enabled 1: Disabled x Combfilter compensation delay (ADC1) 0: Enabled 1: Disabled x x x x x x x x Hsync shift Shift=HSPPL * 4 00000000: Default x x x x x x x Vsync shift Shift=VSLPF * 4 0000000: Default Reference value bandgap 01000000: Low reference 00000000: Medium reference 00111111: High reference 1XXXXXXX: Reference disabled, resistor used contains fused value only when REFTRIMEN=0. x x x x Reference value CVBS ADC 0000: Narrow 1111: Wide Note: Contains fused value only when REFTRIMEN=0. Description 144 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B BGSHIFTM REMDEL2 REMDEL1 61h W VS656_27 HSPPL VSLPF 62h R NTO REFTRIMRD x x x x x x x x REFTRIMCVRD PRELIMINARY DATA SHEET REFTRIMRGBRD x x x x Reference value RGB ADC 0000: Narrow 1111: Wide Note: Contains fused value only when REFTRIMEN=0. Micronas 3.9.2. Slave Channel Table 3-14: Slave channel Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description Color Decoder Slave 63h W VS2_20 MVPS x Vertical length measurement with vertical pulse detection 0: Disabled 1: Enabled x Vertical pulse gating 0: Disabled 1: Enabled x x x x x x (See 75h) (See 75h) (See 74h) (See 74h) Automatic standard detection priority 50 Hz 00: PAL B 01: SECAM 10: (Reserved) 11: Automatic x x Automatic standard detection priority 60 Hz 00: NTSC M 01: NTSC44/PAL60 10: (Reserved) 11: Automatic x Reference for sync-AGC 0: Normal reference 1: Referenc reduced by 2% x AGC peak-white counter reset 0: No reset 1: Reset x Clamp signal adapation 0: Disabled 1: Enabled Note: MUST be enabled when internal 4H comb-filter is used for slave. MUST be disabled, if no or external comb-filter is used for slave. x x AGC hysterisys 00: Broad 01: Medium 1 10: Medium 2 11: Small Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET MVPGS BELLIIRS[2] BELLFIRS[2] DEEMPIIRS[2] DEEMPFIRS[3] AMSTD50S AMSTD60S SYNCGAINS VSP 94x5B, VSP 94x7B AGCPWRESS BGSHIFTS AGCTHDS 145 Table 3-14: Slave channel, continued Subadd 64h R/W Take Over W VS2_20 Name SYNCFTHDS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x SYNCF threshold 00: 4 lines 01: 3 lines 10: 2 lines 11: 1 line x x x x x x x Vertical Sync Gating: Closing 60 Hz Closing=262+4*VTHRH60M 0000000: Closing in line 262 1111111: Closing in line 770 x x x x x x x Vertical Sync Gating: Opening 60 Hz Opening=4*VTHRL60M 0000000: Opening in first line 1111111: Opening in line 508 Color switched on at level above CKILLS (SECAM) At level=CKILLS+CONS 000: Min value 010: Default 111: Max value x Forces color on 0: Color depends on color decoder status 1: Color always on x Opens the closed loop 0: Normal operation 1: Chroma PLL opened x Enabling of additional lowpass filtering of luminance channel 0: No filtering 1: Filtering x Fix ACC to nominal value 0: ACC is working 1: ACC is set to fixed value according to PALREFS/NTSCREFS x Freeze ACC 0: ACC is working 1: ACC is frozen at current value x Mode selection 0: Interlace input 1: Progressive input x Field inversion 0: No inversion 1: Inversion x Clamping strategy 0: Back-porch clamping 1: Sync-tip-clamping 146 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VTHRH60S VTHRL60S 65h W VS2_20 CONSS x x x COLONS CPLLOFS LPPOSTS ACCFIXS ACCFRZS PRELIMINARY DATA SHEET FLINES FLDINVS CLPSTGYS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name DISCHCHS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Disable channel change signal 0: Color decoder not reset after channel-change 1: Color decoder reset after channel change x x x x Clamping duration CD2, signals 1 Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3 s Color switched on at level above CKILL (PAL/NTSC) Level=CKILL+CON 000: Min value 010: Default 111: Max value x x Chrominance coring 00: Off 01: 1LSB 10: 2LSB 11: 3LSB x x Selection of notch filter behaviour in SECAM mode 00: 4.406 MHz 01: 4.250 MHz 10: 4.33 MHz 11: 4.406 / 4.205 dependent on line switch x x H polarity at HINP 00: Use Hsync 01: Use inverted Hsync 10: Autodetect polarity 11: (Reserved) x Automatic multisync capability 0: Disabled 1: Enabled x x Comb filter usage CD2 00: Use first CVBS input 01: Use second CVBS input 10: Use comb-filter 11: ADCG / ADCF (dependent on ADCSEL) x x x x Clamping duration CD2, signals 1 Granularity: 0000: 0 s 0111: 1.4 s 1111: 3 s Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET CLMPD1S 66h W VS2_20 CONS x x x UVCORS SECNTCHS HPOLS VSP 94x5B, VSP 94x7B FHDETS COMBUSES CLMPD2S 147 Table 3-14: Slave channel, continued Subadd 67h R/W Take Over W VS2_20 Name PWTHDS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Selection of "Peak-White" Threshold 00: 448 01: 470 10: 500 11: 511 x x Choice of UV or CrCb output 00: UV color space 01: CrCb color space 10: Modified CrCb color space (SECAM only) x x Luminance offset 00: No offset (NTSC) 01: - 7.5 IRE 10: + 7.5 IRE (PAL, SECAM) 11: -3.7 IRE Note: A 7.5 IRE offset is added during blanking in display processing. When chosing 10, the luminance offset is equal to the offset of the CVBS input as in both picture and blanking the same 7.5 IRE offset is used. x Vertical pulse detection 0: From sync signal (CVBS, Y, or G)) 1: From separate V-input pin Note: When set to 0, no V polarity detection possible x Y/C select 0: CVBS input 1: Y/C input x No signal behavior 0: Noisy screen when out of sync 1: Colored background insertion instead x Synchronization input 0: Synchronization from CVBS front-end (CVBS or Y/C) 1: Synchronization via RGB front-end (green or fbl ADC) When set to 0, no H polarity detection possible CLMPST1S x x x x x x Measurement start CD2, Signals 1 000000:0 s 011100:5.6 s 111111: 12.8 s Vertical flywheel mode 00: Check for correct standard 01: 3 lines deviation allowed 10: 4 lines deviation allowed, no check for interlace 11: 5 lines deviation allowed, no check for interlace x x x x x x Chroma bandwidth Selects chroma bandwidth 011100: Nominal bandwidth 148 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B CRCBS LMOFSTS VINPS YCSELS NOSIGBS HINPS PRELIMINARY DATA SHEET 68h W VS2_20 VFLYWHLMDS x x CHRFS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name PLLTCS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Time constant HPLL (VCR...TV) 00: Very fast 01: Fast 10: Slow 11: Very slow x x x x x x Clamping start CD2, Signals 2 000000: 0 s 011100: 5.6 s 111111: 12.8 s Delay line 0: Use delay line 1: Do not use delay line (only suited for NTSC) x x x x x x x Color standard assignment 0000000: No color standard chosen 0000001: PAL N 0000010: PAL B 0000100: SECAM 0001000: PAL 60 0010000: PAL M 0100000: NTSC M 1000000: NTSC 44 For allowed combinations please refer to chapter "chroma decoder" 1100110: PALB/SECAM/NTSCM/NTSC44/PAL60 x x x x x x x x Chroma level for color off (PAL/NTSC) 00000000: High burst amplitude 01000000: Default 11111111: Low burst amplitude Chroma level for color off (SECAM) 00000000: Low burst amplitude 01000000: Default 11111111: High burst amplitude Behavior is opposite to CKILL (PAL/NTSC case) x x x x x x x x Free running frequency of horizontal PLL 00000000: 384 clocks (52.7 kHz) 11100100: 1296 clocks (15.625 kHz) 11111111: 1404 clocks (14.423 kHz) V Polarity at VINP 00: Use Vsync 01: Use inverted Vsync 10: Autodetect polarity 11: (Reserved) x H slicing level threshold 0: 50 % 1: 37 % Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET CLMPST2S 69h W VS2_20 COMBS x CSTANDS CKILLS 6Ah W VS2_20 CKILLSS x x x x x x x x VSP 94x5B, VSP 94x7B FHFRRNS 6Bh W VS2_20 VPOLS x x THRSELS 149 Table 3-14: Slave channel, continued Subadd R/W Take Over Name YCDELS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x Luminance delay 10000: 800 ns 0000: No delay 01111: -700 ns x Disable all chroma resets 0: Resets allowed 1: Resets disabled May only be used if ONE color standard is selected x Noise reduction for satellite signal 0: Disabled 1: Enabled x x x Noise reduction for horizontal PLL 000: 1/8 001: 1/4 010: 1/2 011: 1 100: 2 101: 4 110: 8 111: 16 x x x Window shift for fine error calculation 100: -4 clock cycles 000: No offset 011: +3 clock cycles Hue control (tint) 10000000: -89 00000000: 0 01111111: +88 x x x x x x x x Field detection window shift 00000000: No shift 11111111: Shifted by 2048 ACC reference adjustment (NTSC) 00000000: Low reference value 10010001: Nominal value 11111111: High reference value x PAL/NTSC identification level 1 0: Less sensitive (192) 1: More sensitive (64) x x x x x x x Vertical Sync Gating: Opening 50 Hz Opening=4*VTHRL50M 0000000: Opening in first line 1111111: Opening in line 508 150 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DISALLRESS SATNRS NSREDS LPCDELS 6Ch W VS2_20 HUES x x x x x x x x VSHIFTS 6Dh W VS2_20 NTSCREFS x x x x x x x x PRELIMINARY DATA SHEET PALIDL1S VTHRL50S Micronas Table 3-14: Slave channel, continued Subadd 6Eh R/W Take Over W VS2_20 Name PALREFS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x ACC reference adjustment (PAL) 00000000: Low reference value 11110000: Nominal value 11111111: High reference value x PAL/NTSC identification level 0 0: Less sensitive 1: More sensitive x x x x x x x Vertical sync gating: Closing 50 Hz Closing=312+4*VTHRH50M 0000000: Closing in line 312 1111111: Closing in line 820 When VINPS (67h) is set, 50 Hz values are taken for opening and closing values. Slicing level threshold H 00: No offset 01: Small negative 10: Small positive 11: Large positive (adaptive) x x x x x x Subcarrier adjustment 000000: -262 ppm 001111: 0 ppm 111111: 840 ppm x x AGC method 00: Sync amplitude and peak white 01: Sync amplitude only 10: peak white only 11: Fixed to value AGCADJ1S x x x x x x Gain adjustment ADC1 000000: 0.6 V input sign 100000: 1.0 V input signal 111111: 1.8 V input signal AGC reset 0: No reset 1: Reset x Freeze AGC (ADC_CVBS) 0: Normal operation 1: Freeze AGC at current value x x x x x x Gain adjustment ADC2 000000: 0.6 V input signal 100000: 1.0 V input signal 111111: 1.8 V input signal x Vertical flywheel 0: Disabled 1: Enabled Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET PALIDL0S VTHRH50S 6Fh W VS2_20 SLLTHDS x x SCADJS AGCMDS AGCADJ1S VSP 94x5B, VSP 94x7B 70h W VS2_20 AGCRESS x AGCFRZES AGCADJ2S VFLYWHLS 151 Table 3-14: Slave channel, continued Subadd R/W Take Over Name CPLLRESS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Force chroma PLL reset 0: No reset 1: Reset chroma PLL Note: After use, CPLLRESS must be set to 0 again x x x x x x Clamping start CD2, Signals 1 000000: 0 s 011100: 5.6 s 111111: 12.8 s Vertical end of clamping pulse 00000000: Line 256 00111100: Line 376 11111111: Line 766 x x SECAM identification level 00: 128 01: 64 10: 96 11: 80 x x x x x x Measurement start CD2, Signals 2 000000: 0 s 011100: 5.6 s 111111: 12.8 s 2nd IF compensation filter 0: Disabled 1: Enabled x x x Secam acceptance level 000: 100 001: 84 010: 64 011: 32 100: 70 101: 76 110: 90 has only effect if SECACCS (74h) is enabled 152 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B CLMPST1SS 71h W VS2_20 CLMPHIGHS x x x x x x x x SCMIDLS CLMPST2SS 72h W VS2_20 IFCOMPSTRS x SECACCLS PRELIMINARY DATA SHEET CLMPLOWS x x x x Vertical start of clamping pulse 0000: Line 0 0011: Line 6 1111: Line30 x x x x x ACC limitation 00000: Limit at high color-carrier 01000: Limit at -24 dB 11111: Limit at low color-carrier ACCLIMS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name IFCOMPS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x IF compensation filter 000: Pal prefiltering 001: Pal prefiltering + IF 010: Prefiltering 011: IF 6 dB 100: Flat Vertical slicing level threshold polarity 0: Positive 1: Negative x EIA 770 support 0: Standard TV signals expected 1: Progressive signals expected Note: Timing according to EIA 770.1 or 770.2 when 1 x Vertical sync-detection slope 0: Normal 1: Slow x x Duration of chroma-PLL search 00: 25 fields 01: 20 fields 10: 17 fields 11: 15 fields x Additional lock-detection 0: No used 1: Used x Additional lock-detection selection 0: PALID 1: PALDET x Additional lock-detection color-killer 0: Do not use lock signal 1: Use lock-signal x x x x Clamping duration for CD2, signals 2 (for RGBF) Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3.2 s x x x x Clamping duration for CD2, signals 1 Granularity: 200 ns 0000: 0 s 0111: 1.4 s 1111: 3.2 s Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 73h W VS2_20 SLLTHDVPS x EIA770S VDETIFSS LOCKSPS ADLCKS ADLCKSELS VSP 94x5B, VSP 94x7B ADLCKCCS CLMPD2SS CLMPD1SS 153 Table 3-14: Slave channel, continued Subadd 74h R/W Take Over W VS2_20 Name DEEMPFIRS[2:0] A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Deemphase filter FIR component 0000:16 0101: 21 1111: 31 DEEMPFIRS[3] is in 63h x x Deemphase filter IIR component 000: 5 001: 6 010: 7 011: 8 100: 9 101: 10 110: (reserved) 111: (reserved) DEEMPIIRS[2] is in 63h x x x Vertical detection integration time constant 000: 400 clock cycles 001: 375 clock cycles 010: 350 clock cycles 011: 300 clock cycles 100: 250 clock cycles 101: 225 clock cycles 110: 200 clock cycles 111: Automatic x Secam acceptance 0: Disabled 1: Enabled x Secam divider 0: Divide by 4 1: Divide by 2 x x Secam increment 1 00: 2 01: 3 10: 4 11: 5 x x Secam increment 2 00: 1 01: 2 10: 3 11: 4 x x Secam rejection level 00: 320 01: 384 10: 352 11: 1024 154 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B DEEMPIIRS[1:0] VDETITCS SECACCS SECDIVS SECINC1S PRELIMINARY DATA SHEET SECINC2S SCMRELS Micronas Table 3-14: Slave channel, continued Subadd 75h R/W Take Over W VS2_20 Name DEEMPSTDS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Deemphase filtering for standard detection 0: Weak 1: Strong x x Bell filter FIR component 000: -116 001: -113 010: -110 011: -108 100: -106 101: -104 110: -102 111: -100 BELLFIRS[2] is in 63h x x Bell filter IIR component 000: 8 001: 9 010: 10 011: 11 100: 12 101: 13 110: 14 111: 16 BELLIIRI[2] is in 63h x x x Slicing level threshold V 000: No offset 001: 4 010: 8 011: 12 101: Adaptive (limited to +-4) 110: Adaptive (limited to +-8) 111: Adaptive (limited to +-12) x x Force line standard at CVBS/RGB front-end 00: Automatic 01: Force 50 Hz 10: Force 60 Hz 11: (Reserved) x Enable limiter 0: Disabled 1: Enabled x x I -adjustment for horizontal PLL 00: *1 01: *16 10: *4 11: *8 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET BELLFIRS[1:0] BELLIIRS[1:0] SLLTHDVS VSP 94x5B, VSP 94x7B FLNSTRDS ENLIMS ISHFTS 155 Table 3-14: Slave channel, continued Subadd R/W Take Over Name NOTCHOFFS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Luminance notch-filter 0: Notch-filter enabled 1: Filter bypassed for PAL/NTSC / filter enabled for SECAM Note: To switch-off filter for SECAM, use TNOTCHOFF x x Lowpass for vertical sync-separation 00: None 01: Weak 10: Medium 11: Strong PAL/NTSC delay vs. SECAM (chrominance) 00: PAL/NTSC most left 11: PAL/NTSC most right x Luminance notch-filter 0: Notch-filter according to NOTCHOFFS 1: Notch-filter disabled x x x Burstgate delay (SECAM only) Granularity: 200 ns 000: Most left (-400 ns) 010: No delay 111: Most right (+1 s) x Pal detection: Increment 1 0: +3 1: +2 x Pal detection: Increment 2 0: -1 1: -2 Do not use PALINC2S=1 in combination with PALINC1S=1 PALIDL2S x PAL / NTSC identification level 2 0: less sensitive 1: more sensitive x x Chroma lock-range 00: 425 Hz 01: 463 Hz 10: 505 Hz 11: 550 Hz x x x Luminance notch selection 000: Sharp notch 001: Medium 1 010: Medium 2 011: Broad notch 100: Broad steep notch (PAL, SECAM only) 156 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VLPS 76h W VS2_20 PALDELS x x TNOTCHOFFS BGPOSS PALINC1S PALINC2S CLRANGES PRELIMINARY DATA SHEET NTCHSELS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name TRAPBLUS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Notch frequency for 4.250 MHz 0: 4.25 MHz 1: 4.2 MHz Has only effect in SECAM mode x Notch frequency for 4.406 MHz 0: 4.406 MHz 1: 4.356 MHz Note: Has only effect in SECAM mode Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET TRAPREDS Memory Controller Slave Channel 77h W VSS2_40 INTPROGS x Interlaced or progressive input signal for master channel 0: Interlaced input source 1: Progressive input source (e.g. VGA) x Freeze master picture 0: Live 1: Frozen (no writing of master data) x Vertical resolution master channel for frame based MUP-mode 0: Field resolution 1: Frame resolution x x Write mode master channel 00: All incoming fields are stored 01: Only A fields are stored 10: Only B fields are stored 11: Not defined x Read master memory data to slave 0: Slave data is read from slave memory 1: Slave data is read from master memory x x Pixels per line slave channel 00: Defined by DISPMODE 01: 448 pixels/line 10: 768 pixels/line 11: 896 pixels/line x x x x x x Horizontal Position of master picture in the memory 000000: Left border position Effective values: WRPOSXS/2 * 32 pixel, WRPOSXS* 16 pixel (MUP-modes), WRPOSXS/8 * 128 pixel (DISPMODE=0000, MOTVALON=1) Vertical position of master picture in the memory 00000000: Upper border position Resolution: 1 line FREEZES VERRESS WRITES READM2S VSP 94x5B, VSP 94x7B PIXPLINS WRPOSXS 78h W VSS2_40 WRPOSYS x x x x x x x x 157 Table 3-14: Slave channel, continued Subadd 79h R/W Take Over W VSBS_36 Name RDPOSYS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x Vertical read position slave Line number indicating the start line of reading for the master channel Granularity: 1 line 00000000: First line x x x x x Horizontal read position slave Pixel number indicating the start position of reading for the master channel 00000: First left pixel position=RDPOSXS*32 x x Read mode master channel 00: Reading A and B fields 01: Reading only A fields 10: Reading only B fields 11: (Reserved) For DISPMODE=0001 (Snap Shot): 00: Reading live channel 00: Reading still picture 158 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B RDPOSXS READS Noise Measurement Slave Channel 7Ah W VSS1_40 NMLINES x x x x x x x x x Line for noise measurement 0d: Line 2 1d: Line 3 311d: Line 1 (PAL) 261d: Line 1 (NTSC) Note: Lines 3-260 are not standard dependent x x Noise measurement sensitivity 00: *1 01: *2 10: *4 11: *8 x x Noise measurement analyze window position 00: 6.3 s 01: 12.6 s 10: 18.9 s 11: 23.7 s NMSENSES x NMPOSS PRELIMINARY DATA SHEET Temporal Noise Reduction Slave Channel 7Bh W VSS2_40 FEMAGS x x x x x Fine error characteristic 00000: Smallest gain 10000: Default (equal to B11version) 11111: Largest gain x x x Secam Dr adjustment 00: 191 01: 194 10: 197 11: 200 SDRS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name SDBS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Secam Db adjustment 00: -55 01: -58 10: -61 11: -64 x Motion detector works on absolute values: 0: Absolute values not calculated 1: Absolute values calculated x Temporal noise reduction 0: Disabled 1: Enabled x Chrominance motion values from: 0: Luminance motion detector 1: Separate chrominance motion detector x Temporal noise reduction of luminance and chrominance 0: Frame based 1: Field based TNR curve characteristic of luma segment 0 0001: Default x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x TNR curve characteristic of luma segment 1 1111: Default TNR curve characteristic of luma segment 2 1111: Default TNR curve characteristic of luma segment 3 0100: Default Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET TNRABSS NRONS TNRSELS TNRNR4YS 7Ch W VSS2_40 TNRYS0S TNRYS1S TNRYS2S TNRYS3S x x x x VSP 94x5B, VSP 94x7B 7Dh W VSS2_40 TNRYS4S TNRYS5S TNRYS6S TNRYS7S TNR curve characteristic of luma segment 4 0100: Default TNR curve characteristic of luma segment 5 0100: Default TNR curve characteristic of luma segment 6 0000: Default TNR curve characteristic of luma segment 7 0000: Default TNR curve characteristic of chroma segment 0 0001: Default 7Eh W VSS2_40 TNRCS0S TNRCS1S x x x x TNR curve characteristic of chroma segment 1 1111: Default TNRCS2S x x x x TNR curve characteristic of chroma segment 2 1111: Default 159 Table 3-14: Slave channel, continued Subadd R/W Take Over Name TNRCS3S 7Fh W VSS2_40 TNRCS4S TNRCS5S TNRCS6S TNRCS7S 80h W VSS2_40 TNRYSSS TNRCSSS x x x x x x x x x x x x x x x x x x x x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x TNR curve characteristic of chroma segment 3 0100: Default TNR curve characteristic of chroma segment 4 0100: Default TNR curve characteristic of chroma segment 5 0100: Default TNR curve characteristic of chroma segment 6 0000: Default TNR curve characteristic of chroma segment 7 0000: Default TNR start value of luma LUT 1111: Default TNR start value of chroma LUT 1111: Default TNR luminance classification: 0000: Strong noise reduction 1111: Slight noise reduction x x x x TNR chrominance classification: 0000: Strong noise reduction 1111: Slight noise reduction 160 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B TNRCLYS TNRCLCS Preframe Generator Slave Channel 81h W VSS2_40 YBORDERS x x x x Y border value of display Granularity: 16 0000: 0 0001: 16 1111: 240 x x x x U border value of display Granularity: 16 0000: 0 0001: 16 0111: 112 1000: -128 1111: -16 x x x x V border value of display Granularity: 16 0000: 0 0001: 16 0111: 112 1000: -128 1111: -16 UBORDERS PRELIMINARY DATA SHEET VBORDERS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name MPFBLBS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x Multi picture force background lines bottom Number of lines of background color to be appended 0000: 0 lines 1111: 15 lines Multi picture force background pixels right Number of pixels of background color to be appended 00: 0 pixels 01: 16 pixels 10: 32 pixels 11: 48 pixels x x x x Multi picture force background lines top Number of lines to be overwritten with background color from top 0000: 0 lines 1111: 15 lines x x x x x x V saturation 000000: 0 100000: 1 111111: 63/32 Background generator in pre-frame generator 0: Disabled 1: Enabled x x x x x Multi picture force background pixels left Number of pixels to be overwritten with background color from left Granularity: 2 pixel 00000: 0 pixels 11111: 62 pixels x x x x x x U saturation 000000: 0 100000: 1 111111: 63/32 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 82h W VSS2_40 MPFBPRS x x MPFBLTS DPVSAT 83h W VSS2_40 FRCBGNDS x MPFBPLS DPUSAT VSP 94x5B, VSP 94x7B Horizontal Prescaler Slave Channel 84h W VSS1_40 FRCMMODS x Mosaic mode generator 0: Disabled 1: Enabled x Active pixel enable select 0: Count clock cycles (recommended for CVBS/RGB input) 1: Count active pixels (recommended for ITU656 input) x x x x x x x x x x x x Control signal for HSCALE in horizontal pre-scaler Subsampling factor by prescaler is (int) 0: 1 (int) 2048: 1.5 (720 pixels) (int) 2371: 1.578 (684 pixels) (int) 4095: 2 (540 pixels) APENSELS HSCPRESCS 161 Table 3-14: Slave channel, continued Subadd 85h R/W Take Over W VSS1_40 Name HAAPRESCS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Horizontal antialiasing filter 00: Filter bypassed 01: Force characteristic weak 10: Force characteristic strong 11: Automatic characteristic (weak or strong) Note: For normal CVBS/RGB full-screen, filter should be set to weak or automatic characteristic. For ITU656 full-screen input, filter should be bypassed. Strong characteristic is for split-screen and PiP only. x x x x Horizontal pre-scaler decimates by 0000: 1 0001: 2 0010: 3 0011: 4 0100: 6 0101: 8 0110: 12 0111: 16 1000: 24 1001: 32 x x x x x x x x x Active pixel per line (pre scaler) Describes, how many decimated active pixels are generated. Granularity: 2 pixels (int) 0: 0 pixels (int) 342: 684 pixels (int) 511: 1022 pixels Line memories 0: Available for vertical prescaler 1: Disabled x x x x x x x x x x Not active pixel per line (pre scaler) Granularity: 2 clock cycles (int) 0: 0 pixels (int) 100: 200 pixels (int) 1023: 2046 pixels 162 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B HDCPRESCS APPLIPS 86h W VSS1_40 MOTONS x NAPPLIPS Vertical Prescaler Slave Channel 87h W VSS1_40 VAAPRESCS x Vertical lowpass filter (pre-scaler) 0: Disabled 1: Enabled x x x x x Vertical peaking 00000: Maximum vertical peaking (enhancement) 10000: Vertical peaking has no effect (flat) 11111: Maximum attenuation (damping) x Shift of chrominance signal 0: No shift 1: One line upward (e.g. for VCR) PRELIMINARY DATA SHEET VPKPRESCS VCRPRESCS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name NALPFIPS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x Not active lines per field input (int) 0: Shift is 0 (int) 22: Shift is 22 lines (int) 511: Shift is 511 lines (max. shift is 1 field) Vertical Pre scaler Bypass 0: Vertical pre scaler enabled 1: Vertical pre scaler bypassed x x x x Vertical pre-scaler decimates by 0000: 1 0001: 2 0010: 3 0011: 4 0100: 6 0101: 8 0110: 12 0111: 16 1000: 24 1001: 32 x x x x x x x x x x Active lines per field (input processing) (int) 0: No active line (int) 288: 288 active lines (int) 1023: 1023 lines Control signal for VSCALE in vertical pre-scaler (int) 0: Scaling factor is 1 (int) 4095: Scaling factor is 2 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 88h W VSS2_40 VPREBYPS x VDCPRESCS ALPFIPS 89h W VSS2_40 VSCPRESCS x x x x x x x x x x x x Horizontal Postscaler Slave Channel 8Ah W VSBS_36 HPANONS x Horizontal panorama mode 0: Panorama disabled 1: Panorama enabled x Disable border detection (postscaler) 0: Border detection active 1: Border detection not active x Chrominance delay 0: No delay 1: Half-pixel delay x x x x x x x x x x x x Horizontal scaling factor for post scaler (int) 1024: Upsampling factor is 4 (int) 2910: Upsampling factor is 1.40 (int) 4095: Upsampling factor is 1 Beginning of segment 1 for horizontal panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start VSP 94x5B, VSP 94x7B DBDHPOSS CDELHPOSS HSCPOSCS 8Bh W VSBS_36 HSEG1S[10:5] x x x x x x 163 Table 3-14: Slave channel, continued Subadd R/W Take Over Name HINC0S A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x Horizontal post-scaler increment 0 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels (See 8Dh) x x x x x x x x x Horizontal post-scaler increment 1 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels Beginning of segment 2 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start x x x x x x x x x Horizontal post-scaler increment 2 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels (See 8Fh) x x x x x x x x x Horizontal post-scaler increment 3 100000000: -32 pixels 000000000: 0 pixels 011111111: 31.875 pixels Beginning of segment 3 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start x x x x x x x x x Horizontal post-scaler increment 4 100000000: -32 pixels 000000000: 0 pixelsi 011111111: 31.875 pixels (See 91h) x x x x x x x x x x x Beginning of segment 4 for panorama mode Granularity: 2 pixels (int) 0: 0 pixel behind picture start (int) 2047: 4094 pixel behind picture start 164 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B 8Ch W VSBS_36 HSEG1S[4:0] HINC1S x x x x x 8Dh W VSBS_36 HSEG2S[10:5] x x x x x x HINC2S 8Eh W VSBS_36 HSEG2S[4:0] HINC3S x x x x x 8Fh W VSBS_36 HSEG3S[10:5] x x x x x x HINC4S 90h W VSBS_36 HSEG3S[4:0] HSEG4S x x x x x PRELIMINARY DATA SHEET Output Data Controller Slave Channel 91h W VSBS_36 HOROFFS [10:6] x x x x x Horizontal offset to compensate slave processing delay (int) 64: Default x x x x x x x x x x x Horizontal position inside active picture area (int) 0: Most left display position (int) 4095: Most right display position Micronas HORPOSS Table 3-14: Slave channel, continued Subadd 92h R/W Take Over W VSBS_36 Name HOROFFS[5:0] VERPOSS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x x x x x x x x (See 91h) Vertical position inside active picture area Granularity: 1 line (FMODE=0) or 2 lines (FMODE=1) (int) 0: Most top display position (int) (2047): Most bottom display position Horizontal picture width Granularity: 2 pixels (int) 0: No display (int) 960: Default (int) 2047:4094 pixels Vertical offset to compensate slave processing delay (int) 17: Default x x x x x x x x x x x Vertical picture width (int) 0: 0 lines (int) 288: Default (int) 2047: 2047 lines Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 93h W VSBS_36 HORWIDTHS x x x x x x x x x x x 94h W VSBS_36 VEROFFS VERWIDTHS x x x x x Picture Improvement Slave Channel 95h W VSBS_36 PKCTIBPS x x Peaking factor for CTI (bandpass part) 00: 2 (CTI bp off) 01: 16 10: 24 11: 32 x x Peaking factor for CTI (highpass part) 00: 2 (CTI hp off) 01: 16 10: 24 11: 32 x Luminance transition improvement 0: disabled 1: enabled x x 1st adaptive peaking factor (bandpass part) 0000: 0.5 0100: 2.5 1111: 8 x x x 2nd adaptive peaking factor (bandpass part) 000: 1 001: 2 (peaking bp off) 011: 4 111: 8 PKCTIHPS VSP 94x5B, VSP 94x7B LTIS APK1BPS[1:0] APK2BPS 165 Table 3-14: Slave channel, continued Subadd R/W Take Over Name ATH1BPS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Peaking denoising threshold (bandpass part) 00: 0 (denoising off) 01: 2 10: 4 11: 8 x x 2nd peaking threshold (bandpass part) 00: 0 01: 4 10: 8 11: 16 x x Turning point threshold for CTI 00: 1 01: 2 10: 3 11: 4 1st adaptive peaking factor (highpass part) 0000: 0.5 0100: 2.5 1111: 8 x x x 2nd adaptive peaking factor (highpass part) 000: 1 001: 2 (peaking hp off) 011: 4 111: 8 x x Peaking denoising threshold (highpass part) 00: 0 (denoising off) 01: 2 10: 4 11: 8 x x 2nd peaking threshold (highpass part) 00: 0 01: 4 10: 8 11: 16 x Disable border detection (picture improvement) 0: Border detection active 1: Border detection not active x x x x x (See 49h) (See 49h) Coring or denoising for low amplitudes 0: Coring off, denoising on 1: Coring on, denoising off 166 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B ATH2BPS THES 96h W VSBS_36 APK1HPS[1:0] x x APK2HPS ATH1HPS ATH2HPS PRELIMINARY DATA SHEET DBDPICIS APK1BPS[3:2] APK1HPS[3:2] CORONS Micronas Table 3-14: Slave channel, continued Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description Pixel mixer slave channel 97h W VSBS_36 YFRAMES UFRAMES VFRAMES x x x x x x x x x x x x Luminance value for the slave frame (4MSB) 0001: Default value (yields value 0001 00000=32) Chrominance value for the slave frame (4MSB) 0000: Default value (yields value 0000 00000=0) Chrominance value for the slave frame (4MSB) 0000: Default value (yields value 0000 00000=0) Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET 3.9.3. Common Table 3-15: Common Subadd R/W Take Over Name A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description Comb filter 98h W VS1_20 CVBSEL1 x x x x Input select for ADC1 0000: CVBS1 0001: CVBS2 0010: CVBS3 0011: CVBS4 or Y1 0100: CVBS5 or C1 0101: CVBS6 or Y2 0110: CVBS7 or C2 0111: Y1 + C1 1000: Y2 + C2 1001: CVBS8 (QFP144 versions only) 1010: CVBS9 (QFP144 versions only) 1111: Disabled x x x x Input select for ADC2 0000: CVBS1 0001: CVBS2 0010: CVBS3 0011: CVBS4 or Y1 0100: CVBS5 or C1 0101: CVBS6 or Y2 0110: CVBS7 or C2 0111: Y1 + C1 1000: Y2 + C2 1001: CVBS8 (QFP144 versions only) 1010: CVBS9 (QFP144 versions only) 1111: Disabled VSP 94x5B, VSP 94x7B CVBSEL2 167 Table 3-15: Common, continued Subadd R/W Take Over Name CLMPSIG1 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Clamping signals ADC1 00: 1st color decoder: signals 1 01: 1st color decoder: signals 2 10: 2nd color decoder: signals 1 11: 2nd color decoder: signals 2 x x Clamping signals ADC2 00: 1st color decoder: signals 1 01: 1st color decoder: signals 2 10: 2nd color decoder: signals 1 11: 2nd color decoder: signals 2 x VCR detection threshold 0: High threshold 1: Low threshold x YC by Red 0: Normal operation 1: C input from red ADC x YC by Blue 0: Normal operation 1: C input from blue ADC x YC to Comb filter 0: Normal comb operation 1: yc signal fed through comb delays Use INCOMB instead of YCBYR or YCBYB for this mode Output select 1 for pin cvbso1 0000: CVBS1 0001: CVBS2 0010: CVBS3 0011: CVBS4 or Y1 0100: CVBS5 or C1 0101: CVBS6 or Y2 0110: CVBS7 or C2 0111: Y1 + C1 1000: Y2 + C2 1001: CVBS8 (QFP144 versions only) 1010 : CVBS9 (QFP144 versions only) 1111: Disabled 168 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B CLMPSIG2 VCRDETHD YCBYR YCBYB YCTOCOMB 99h W VS1_20 CVBOSEL1 x x x x PRELIMINARY DATA SHEET Micronas Table 3-15: Common, continued Subadd R/W Take Over Name CVBOSEL2 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x Output select for pin cvbso2 0000: CVBS1 0001: CVBS2 0010: CVBS3 0011: CVBS4 or Y1 0100: CVBS5 or C1 0101: CVBS6 or Y2 0110: CVBS7 or C2 0111: Y1 + C1 1000: Y2 + C2 1001: CVBS8 (QFP144 versions only) 1010 : CVBS9 (QFP144 versions only) 1111: Disabled x x x x Output select for pin cvbso3 0000: CVBS1 0001: CVBS2 0010: CVBS3 0011: CVBS4 or Y1 0100: CVBS5 or C1 0101: CVBS6 or Y2 0110: CVBS7 or C2 0111: Y1 + C1 1000: Y2 + C2 1001: CVBS8 (QFP144 versions only) 1010 : CVBS9 (QFP144 versions only) 1111: Disabled x x Vertical difference gain 00: Max. gain 01: Medium 2 10: Medium 1 11: Min. gain x x Horizontal difference gain 00: Min. gain 01: Medium 1 10: Medium 2 11: Max. gain Diagonal dot reduction 00: Min. reduction 01: Medium 1 10: Medium 2 11: Max. reduction x x x x Test only 000: Normal operation Test only 0: Normal operation Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET CVBOSEL3 VDG VSP 94x5B, VSP 94x7B HDG 9Ah W VS1_20 DDR x x F2F1F0 DT 169 Table 3-15: Common, continued Subadd R/W Take Over Name DC COR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Test only 0: Normal operation Vertical peaking coring 0: Disabled 1: Enabled x x Notch filter select 00: Flat frequency characteristic 01: Min. peaked 10: Med. peaked 11: Max. peaked x Vertical peaking DC rejection filter 0: Disabled 1: Enabled x Timing of Rising edge of H50 sync 0: late 1: early x x x x Vertical peaking gain (comb-filter peaking) 0000: No vertical peaking 1111: Max. vertical peaking Nr. of pixel for 50 Hz signals Length=1284+LINLENH50 LINLENH50=12 (=1296 pixel per line) x x x x Nr. of pixel for 60 Hz signals Length=1284+LINLENH60 LINLENH60=3 (= 1287 pixel per line) x Reference value enable 0: Use on-chip fused values 1: Use IC values x Signal select for PIN Vout50 0: Single scan vertical output 1: Blank signal output x Reset control bit cancel 0: No operation 1: Reset POR bit (EBh) After use, PORCNCL must be set to 0 again x Reset PC1 signal (test only) 0: Normal operation 1: Reset PC1 x Reset PC2 signal (test only) 0: Normal operation 1: Reset PC2 170 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B NOSEL DCR SYNCOMB VPK 9Bh W VS1_20 LINLENH50 x x x x LINLENH60 REFTRIMEN V50BLANK PRELIMINARY DATA SHEET PORCNCL RESETPC1 RESETPC2 Micronas Table 3-15: Common, continued Subadd R/W Take Over Name SELCOMB A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x COMB filter used for first or second color-decoder 0: CD 1 1: CD 2 x Disable comb-filter 0: Comb-filter enabled 1: Comb-filter disabled (notch CVBS or Y/C input) x Resampling mode (test only) 0: Fractionally subcarrier locked 1: Fractionally line-locked mode Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET DISCOMB RESMODE SLICER/ANALOG 9Ch W VS1_20 XDSCLS x x x x x XDS-Primary-filter (class) 00000: Transparent (all sliced data, both fields) 1xxxx: "Current" selected (only second field) x1xxx: "Future" selected (only second field) xx1xx: "Channel" selected (only second field) xxx1x: "Miscellenious" selected (only second field) xxxx1: "Public Services" selected (only second field) x Signal select for PIN 656VIO 0: 656vin or 656vout (dependent on operation mode) 1: Blank signal output x x x XDS-secondary-filter (classtype) / [WSS field] 000: ALL (no filtering) [field 1 only] 001: 05h (program rating) [field 2 only] 010: 01h, 04h (time information only)[both fields] 011: 40h (out of band only) 100: 01h,02h,03h,04h,0Dh,40h (VCR information) 101: 01h, 04h,05h (time information only and PR)[both fields] 110: 05h,40h (out of band only and PR) 111: 01h,02h,03h,04h,05h,0Dh,40h (VCR information and PR) x x x IRQpin selection 000: Horizontal sync (2 s) 001: Interrupt, when new data arrived (pos. polarity)(2 s) 010: Interrupt, when new data arrived (neg. polarity)(2 s) 011: Equivalent to DATAV for both registers (pos. pol.) 100: Equivalent to DATAV for both registers (neg. pol.) 101: Vertical sync (2 s) 110: Selected line for slicing 111: Cvbs field at output x Closed caption or WSS 0: Closed caption 1: WSS x x Input for comb filter 00: ADC 1 01: ADC 2 10: ADCG / ADCF (dependent on ADCSEL) 656BLANK XDSTPE VSP 94x5B, VSP 94x7B IRQCON SERVICE INCOMB 171 Table 3-15: Common, continued Subadd R/W Take Over Name SLSRC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Select Slicer source 0: Master front-end 1: Slave front-end Reference value bandgap 01000000: Low reference 00000000: Medium reference 00111111: High reference 1XXXXXXX: Reference disabled, resistor used x x x x Reference value ADC CVBS (antialiasing filter) 0000: Narrow 1111: Wide x x x x Reference value ADC RGBF (antialiasing filter) 0000: Narrow 1111: Wide 172 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B 9Dh W NTO REFTRIM x x x x x x x x REFTRIMCV REFTRIMRGB ITU Input/Output Interface 9Eh W VS656_27 OMODE x x Output format: 00: Full ITU656 01: ITU656 only data, H- and V-blank as outputs, according to ITU656 10: ITU656 only data, H- and V-blank as inputs, according to ITU656 11: (Reserved) x Clock for ITUO 0: 656clk is clock input 1: 656clk is output equal to pin clkout x x x x x x x x x Pixels per line ITU Granularity: 2 pixel (int) 432: Default CbYCrY-phase shift 00: No phase shift 01: 1 clk 10: 2 clk 11: 3 clk CLK656OUT PPLIPI 9Fh W VS656_27 NAPIPPHI x x PRELIMINARY DATA SHEET F_OFFS x x Offset of active field at interlaced mode (line offset): 00: NALPFIPI+1 (A), NALPFIPI (B) 01: NALPFIPI (A), NALPFIPI+1 (B) 01: 1 H delay in field A 11: 1 H delay in field B x x x x x Ancillary data line number if ADINS=0: Tansmitter address is: 111(+5 bits of ADLINE), if ADINS=1: ADLINE defines the line, which should contain the ancillary data. x Field polarity 0: Field A=0, Field B=1 1: Field A=1, Field B=0 ADLINE FPOL Micronas Table 3-15: Common, continued Subadd R/W Take Over Name IMODE A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Input format 00: Full ITU mode (automatic) 01: Full ITU mode (manual) 10: ITU656 only data, H/V-sync according PAL/NTSC 11: ITU656 only data, H/V-sync according ITU656 x Ancillary data insertion 0: Transmitter preamble is detected in the data stream. If identical as ADLINE data are stored in I2C-Registers. 1: Ancillary data detection in video line ADLINE only, transmitter address ignored. If preamble detected, data are stored in I2C-Registers. x Generate V-sync related to F- or V-flag 0: Use F-flag 1: Use V-flag x x Lines per field for ITU (int)625: 625 lines per field Active pixels per line for ITU Active pixels = APPLIPI * 2 (int) 360=720 lines] x x x x x x x x x x x x x x x x x x x x x x x Not active lines per field for ITU (int) 20= 20 lines Not active pixels from HSYNC to input data for ITU Delay = NAPPLIPI * 2 + NAPIPPHI Active lines per field for ITU Active lines = ALPFIPI * 2 (int) 144: 288 active lines Input signal 0: Interlaced 1: Non interlaced x Chrom. data format 0: Unsigned 1: 2s complement x H656 polarity 0: H656 active low 1: H656 active high x V656 polarity 0: V656 active low 1: V656 active high x x ITU656-interface: 00: input mode 01: memory read output 1x: output display data Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET ADINS VSREF A0h A1h W W VS656_27 VS656_27 LPFIPI APPLIPI x x x x x x x x x x x x x x x x x NALPFIPI A2h W VS656_27 NAPPLIPI ALPFIPI VSP 94x5B, VSP 94x7B A3h W VS656_27 VSIGNAL x CFORMAT HPOL VPOL EN_656 173 Table 3-15: Common, continued Subadd R/W Take Over Name ITUPRTSEL A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x ITU port selection 0: First input (656io) 1: Second input (i656i) RGB Interface A4h W VSRGB_40 BRTADJ x x x x x x x x Brightness adjustment 10000000: -128 (darkest picture) 00000000: 0 01111111: 127 (brightest picture) x x x x x x Contrast adjustment 0000000: 0 000001: 1/32 100000: 1 111111: 63/32 x Chroma subsampling filter 0: Disabled 1: Enabled x (Digital) antialiasing selection 0: -3dB @ 10.6MHz 1: -3dB @ 11.8MHz Front-end clock is given to pin 74 (mqfp80) 0: Pin 74 is used as h-input for ITU656 1: CLKF20 (20.25 MHz) is given to pin 74 x x x Fast blank delay vs. RGB/YUV input Granularity: 25 ns 000: -50 ns delay 010: No delay 110: +100 ns delay 111: (Reserved) x x Clamping correction for G ADC 00: 0 (G/Y, pedestal offset visible) 01: 16 (G/Y, no pedestal offset visible) 10: 64 (G/Y with sync, pedestal offset visible) 11: 80 (G/Y with sync, no pedestal offset visible) x x x x x x x Gain of fast blank signal 1000000: -64 0000000: 0 0111111: +63 Note: For proper operation in dynamic soft-mix mode, absolute value of MIXGAIN must be bigger than 2 (e.g. 3) x Standby mode RGB ADC 0: RGBF ADCs active 1: RGBF ADCs in standby mode 174 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B CONADJ CHRSFR AASEL A5h W VSRGB_40 CLKF2PAD x FBLDEL GOFST PRELIMINARY DATA SHEET MIXGAIN STANDBYRGB Micronas Table 3-15: Common, continued Subadd R/W Take Over Name STANDBYCV A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Standby mode CVBS ADC 0: CVBS ADCs active 1: CVBS ADCCs in standby mode x Decimation by 2 Decimation of RGB/YUV signal before soft-mix 0: No decimation 1: Decimation by 2 Y delay adjustment Granularity: 50 ns 0000000: No delay 1111111: 6.3 s x x x x x x x UV delay adjustment Granularity: 50 ns 0000000: No delay 1111111: 6.3 s x RGB input selection 0 : Use RGB/YUV input1 1 : Use RGB/YUV input2 x Configuration of FBLACTIVE signal 0: React for one clock active FBL input 1: React for 5 clock active FBL input U saturation adjustment 000000: 0 000001: 1/32 100000: 1 111111: 63/32 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET DEC2 A6h W VSRGB_40 YFDEL x x x x x x x UVDEL RGBSEL FBLCONF A7h W VSRGB_40 USATADJ x x x x x x VSP 94x5B, VSP 94x7B VSATADJ x x x x x x V saturation adjustment 000000: 0 000001: 1/32 100000: 1 111111: 63/32 x Select ADC for sync signal conversion 0: Use ADC_G 1: Use ADC_FBL x Bypass RGB/YUV antialiasing filter 0: Use filter 1: Bypass x Clamping value G ADC 0 : 16 1 : 80 x Clamping value fast blank input 0 : Enable clamping 1 : Disable clamping (DC coupling) ADCSEL AABYP CLMPVG DCLMPF 175 Table 3-15: Common, continued Subadd A8h R/W Take Over W VSRGB_40 Name AGCADJR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x Gain adjustment Red 000000: 0.5 V input signal 111111: 1.5 V input signal x x x x x x Gain adjustment Blue 000000: 0.5 V input signal 111111: 1.5 V input signal x x Mixing configuration 00: Enable Soft-Mix 01: Only RGB path visible 10: Only CVBS path visible 11: (Reserved) x x Clamping value Red and Blue ADC 00 : 16 (B/R signal without sync) 01 : 80 (B/R signal without sync) 10 : 128 (U/V signal) 11: (Reserved) Gain adjustment Green 000000: 0.5 V input signal 111111: 1.5 V input signal x x x x x x Gain adjustment fast Blank 000000: 0.5 V input signal 111111: 1.5 V input signal x x x Clamping correction for R/B ADC 000: 0 (R/B, pedestal offset visible) 001: 16 (R/B, no pedestal offset visible) 010: 64 (R/B with sync, pedestal offset visible) 011: 80 (R/B with sync, no pedestal offset visible) 100: 127 (UV negative pedestal offset) 101: 128 (UV) 110: 129 (UV positive pedestal offset) 111: (Reserved) x SKEW correction for RGB/YUV channel 0: SKEW correction enabled 1: SKEW correction disabled Fast blank offset correction 000000 : 0 offset 111111: 63 offset x x Select master channel input 00: CD1 01: CD2 10: Soft-mix output 11: 656 input 176 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B AGCADJB MIXOP CLMPVRB A9h W VSRGB_40 AGCADJG x x x x x x AGCADJF RBOFST SKEWSEL PRELIMINARY DATA SHEET AAh W VSRGB_40 FBLOFFST x x x x x x SELMASTER Micronas Table 3-15: Common, continued Subadd R/W Take Over Name SELSLAVE A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Select slave channel input 00: CD1 01: CD2 10: Soft-mix output 11: 656 input x Select soft-mix input (and clamp, deskew) 0: CD1 1: CD2 x YUV or RGB input selection 0: YUV expected 1: RGB expected x Soft-mix operation mode 0: Dynamic 1: Static x Y to RGB (for YUV mode) 0: Use Y from green ADC 1: Use Y from CVBS ADC x Blue ADC selection 0: Blue ADC gets B1 or B2 (dependent on RGBSEL) 1: Blue ADC gets R2 (independent on RGBSEL) x Blue ADC clamping selection 0: CD 1 (signals 2) 1: CD 2 (signals 2)' Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET SELSM YUVSEL SMOP Y2RGB BLUESEL BLUETWO LL-PLL Processing ABh W NTO/HS IICINCR[18:3] x x x x x x x x x x x x x x x x Set HDTO frequency Granularity=103 Hz 33981d (minimum: nominal pixel clock= 3.5 MHz) 349525d (nominal pixel clock= 36 MHz) 388362d (maximum: nominal pixel clock= 40 MHz) Switch clkf20 and clkf40 to pads cvbs1 or bin2 00: No clock 01: Cvbs1 is output of clkf40 10: Bin2 is output of clkf20 11: Cvbs1 is output of clkf40 and bin2 is output of clkf20 x Test-bit for HPLL 0: Normal mode 1: Test mode x x x x Increment freeze duration 0: No freeze 15: Increment is frozen for 15 lines x Dynamic time constant control 0: Linear mode 1: Non linear mode VSP 94x5B, VSP 94x7B ACh W NTO/HS CLKT1 x x HDTOTEST FILE LNL 177 Table 3-15: Common, continued Subadd R/W Take Over Name DISRES A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Disable reset of LL-PLL watchdog 0: Reset disabled 1: Reset enabled x Limit value for DTO increment 0: No limit '1' : Increment value for DTO is limited to 393216 (Max. frequency of back-end clocks: clkb72: 81 MHz / clkb36: 40.5 MHz ) x x x x x (see ABh) Window-width of coincidence detector 00: 32 pixel (= 0.9 s for TV application) 01: 64 pixel (= 1.8 s for TV application) 10: 128 pixel (= 3.6 s for TV application) 11: 256 pixel (= 7.2 s for TV application) x x Hysteresis of coincidence detector 00: 0 lines 01: 8 lines 10: 16 lines 11: 32 lines x x x x x x x Test bits for HPLL 00: default Width of noise suppression window of LL-HPLL 0000: 28 s 0001: 24 s 0010: 20 s 0011: 16 s 0100: 12 s 0101: 8 s 0110: 4 s 0111: Dynamic windowing. 1000: 30 s 1001: 27 s 1010: 26 s 1011: 22 s 1100: 18 s 1101: 14 s 1110: 10 s 1111: 6 s HSWIN[3] is in B3h x Stability signal of LL_HPLL 0: STABLL is generated by the HPLL 1: STABLL is forced to 1 x Phase detector steepness 0: Steepness for normal TV operation mode 1: Steepness for operations where PPLIP is less than 288d 178 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B LIMHI IICINCR[2:0] ADh W NTO KOIWID KOIH HTESTW HSWIN[2:0] PRELIMINARY DATA SHEET SETSTABLL Micronas KD2 Table 3-15: Common, continued Subadd R/W Take Over Name HINCR_EXT A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x HDTO testmode 0: Normal mode 1: Increment is taken from pins x Selects line locked mode 0: Line locked-clocks derived from HPLL 1: Line-locked-clocks derived from front-end line-length x Selects freerun mode 0: Freerun-clocks derived from crystal 1: Freerun-clocks derived from HDTO Note: Adjustable frequency is only possible when set to 1. When set to 00, Backend clock is always 36 MHz (single-scan versions: 18 MHz) Reset of LL-HPLL 0: No reset 1: Reset Reset automatically when written x Minimum width of H-sync 0: 60*Tclkllf36 1: 15*Tclkllf36 x x x x Increment freeze before V-sync 0: No freeze 15: Freeze starts 15 lines before V-sync x x x x x x x x x x Pixel per line LL_PLL Granularity=4 pixel (int) 175: 700 (minimum) (int) 576: 2304 (int) 963: 3852 (maximum) Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET LMOD FMOD AEh W NTO HRES x HWID FION PPLIP VSP 94x5B, VSP 94x7B AFh W NTO FREQSELL x x Amplifier current setting of oscillator pad 00: 100 A 01: 590 A 10: 235 A 11: 1730 A x Power down of crystal oscillator amplifier 0: Normal mode 1: Power down mode x Power down of crystal oscillator shaper 0: Normal operation 1: Power down active x Testmode control of crystal oscillator 0: Normal operation (shaper active) 1: External clock input (shaper replaced) OSCPD SHAPERDIS TSTSHABRI 179 Table 3-15: Common, continued Subadd R/W Take Over Name LIMLR[2:0] A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Limit LL-PLL lock-in range 0000: Full lock-in range of +/- 5.85 % 0001: Lock in range limited to +/- 3.8 % 0010: Lock in range limited to +/- 2.55 % 0011: Lock in range limited to +/- 1.27 % 0100: Lock in range limited to +/- 0.63 % 0101: Lock in range limited to +/- 0.32 % 0110: Lock in range limited to +/- 0.19 % 0111: Lock in range limited to +/- 0.13 % 1000: Lock in range limited to +/- 5 % 1001: Lock in range limited to +/- 4.5 % 1010: Lock in range limited to +/- 3.1 % 1011: Lock in range limited to +/- 2.1 % 1100: Lock in range limited to +/- 1.5 % 1101: lock in range limited to +/- 1 % 1110: (Reserved) 1111: (Reserved) LIMLR[3] is in B3h x Force coincidence bit 0: Coincidence bit dynamically changed 1: Coincidence bit forced to 1 x Force coincidence hysteresis bit 0: Coincidence hysteresis bit dynamically changed 1: Coincidence hysteresis bit forced to 1 180 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B FKOI FKOIHYS PRELIMINARY DATA SHEET Micronas Table 3-15: Common, continued Subadd R/W Take Over Name KIL[3:0] A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x Integrational factor for loop filter if HPLL is locked 00000: 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111: 16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7 KIL[4] is in B1h x x Limiter Control for P-part for increased dynamic range LIMIT_P= 16*LIMIP 00000000: 0 11111110: 4064 11111111: No limitation Proportional factor for loop filter if HPLL is not locked Same values as in locked condition (KPL) Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET B0h W NTO LIMIP x x x x x x VSP 94x5B, VSP 94x7B B1h W NTO KPNL[3:0] x x x x 181 Table 3-15: Common, continued Subadd R/W Take Over Name KPL[3:0] A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x Proportional factor for loop filter if HPLL is locked) 00000: 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111: 16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7 KPL[4] is in B1h x x x x x x x x x x Proportional factor for loop filter if HPLL is not locked Same vales as in locked condition (KPI) (See B1h) (See B1h) (See B1h) (See AFh) STABLL detection window 00: 64 01: 72 10: 48 11: 32 x x Fine/coarse error selection threshold 00: 16 01: 12 10: 8 11: 0 (never use fine-error) 182 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B KINL[3:0] KPNL[4] KPL[4] KINL[4] KIL[4] B2h W NTO SLLWIN PRELIMINARY DATA SHEET FETHD Micronas Table 3-15: Common, continued Subadd R/W Take Over Name LIMII A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x Limiter control for I-part for increased dynamic range LIMIT_I= 16*LIMII 00000000: 0 11111110: 4064 11111111: No limitation (See ADh) x x (See AFh) Limiter enable 0: B11 behavior for LIMIP and LIMII 1: Normal LIMII and LIMIP characteristic Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET B3h W NTO HSWIN[3] LIMLR[3] LIMEN x Letterbox Detection B4h W VSM1_40 LBSUB x x Subsampling mode 0x: Others (factor 1) 10: 20.25 MHz source (factor 1.5) 11: 40.5 MHz source (factor 3) x Reset of gradient method 0: No reset 1: Reset x Stability flag 0: Continuous format update 1: Format update only once x Sensitivity to 4:3 switch 0: Off 1: On x No gradient found 0: Disabled 1: Enabled x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Threshold for darkness-brightness, histogram, activity (int)30: Default Histogram stability delay (int)10: Default Threshold for gradient detected (int) 50: Default Vertical measure window lower end (int) 150: Default, [in lines (*2) related to VSYNC] Histogram white (int) 50: Default Horizontal measure window end (int) 180: Default, [in active pixels (*4) related to HSYNC] LBGRADRST LBSTABILITY LB43SENS LBNGFEN VSP 94x5B, VSP 94x7B LBTHDNBNHA LBHSDEL B5h W VSM1_40 LBGRADDET LBVWENDLO B6h W VSM1_40 LBHIWHITE LBHWEND 183 Table 3-15: Common, continued Subadd B7h R/W Take Over W VSM1_40 Name LBHISTBLA LBHWST B8h W VSM1_40 LBMASLA x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x x x x x x x Histogram black (int) 25: Default Horizontal measure window start (int) 36: Default, [in active pixels (*4) related to HSYNC] Master-slave switch for detection 0: Slave 1: Master x x x x x x x x Vertical measure window lower start (int) 96: Default], [in lines (*2) related to VSYNC] Field subsampling mode 0: A+B fields 1: Only A field x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Vertical measure window upper end (int) 73: Default], [in lines (*2) related to VSYNC] Gradient stability delay value (int) 10: Default] Gradient fall back delay value (int) 11: Default] Vertical measure window upper start (int) 20: Default], [in lines (*2) related to VSYNC] Activity stability delay (int) 10: Default] Visualisation of letter box results 0: Disabled 1: Enabled x x x x x x x x x x Activity (int) 5: Default] Threshold for darkness-brightness, gradient only (int) 15: Default] 184 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B LBVWSTLO LBFS LBVWENDUP B9h W VSM1_40 LBGSDEL LBGFBDEL LBVWSTUP BAh W VSM1_40 LBASDEL LBVISUON LBACTIVITY LBTHDNBNG PRELIMINARY DATA SHEET Output Data Controller BBh W VSBM2_36 PPLOFF x x x Synchronization offset (For switching from hor. freerun mode to locked mode) Granularity: 4 pixel 000: 0 010: 8 111: 28 Micronas Table 3-15: Common, continued Subadd R/W Take Over Name LPFOPOFF A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x Lines per field offset: (For switching from vertical freerun mode to locked mode) Granularity: 2 lines 0000: 0 0110: 12 1111: 31 (Set equal to LPFOPOFF in BFh) x x x x x x x x x Not active pixel per line output: Granularity: 4pixel 000000000: No not active pixel 000000001: 4 not active pixel 111111111: 2044not active pixel VSYNC freerun: 0: Locked mode 1: Freerun mode x HSYNC freerun: 0: Locked mode 1: Freerun mode x No horizontal synchronization will be performed: 0: Horizontal synchronization 1: No horizontal synchronization x x Raster mode: (50p / 100 i) 00 = / 01 = / 10 = / 11 = / x x x x x x x x x x x (see BEh) H Sync output Delay: Granularity: 4 pixel 0000000000: No delay 0000000001: 4 pixel delay 1111111111: 4092 pixel delay Global fallback 0: Disabled 1: Enabled x Frame mode 0: 2fV, 1: 1fV x Switch for Vsync transfer algorithm: 0: Vsync transfer algorithm is enabled 1: Vsync transfer algorithm is disabled Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET NAPPLOP BCh W VSBM2_36 VOUTFR x HOUTFR NOSYNC RMODE OPDEL HOUTDEL VSP 94x5B, VSP 94x7B BDh W VSBM2_36 GFBON x FMODE PDGSR 185 Table 3-15: Common, continued Subadd R/W Take Over Name MASTERON A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Master channel 0: Disabled (no master picture visible) 1: Enabled x Slave channel 0: Disabled (no slave picture visible) 1: Enabled x x x x x x x x x x x (See BEh) Pixel per line output: Granularity: 4 0000000000: 0 pixel 0100100000: 1152 pixel 1111111111: 4092 pixel V delay for output operation: 000000000: No delay 010101010: 170 lines 111111111: 511 lines x x x x x x x x Lines per field output: Only used for freerun mode Granularity: 2 lines 000000000: No lines 010011100: 312 lines 111111111: 1022 lines 186 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B SLAVEON LPFOP[8] PPLOP BEh W VSBM2_36 OPDEL x x x x x x x x LPFOP[7:0] Memory Controller BFh W VSBM1_36 DISPMODE x x x x Display mode 0000: FSM-mode 0001: SPS-mode 0010: SSC1-mode 0011: MUP1-mode 0100: MUP2-mode 0101: PCE-mode 0110: PCF-mode 0111: PCP-mode 1000: SSC2-mode x Motion values on (Only active for DISPMODE=0000) 0: Motion values are not stored 1: Motion values are stored x Refresh on 0: No memory refresh 1: Memory refresh active PRELIMINARY DATA SHEET MOTVALON REFRON Micronas Table 3-15: Common, continued Subadd R/W Take Over Name REFRPER A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Refresh period 00: 3.2 ms 01: 6.5 ms 10: 13 ms 11: 26 ms x x x x Lines per field offset: (For switching from vertical freerun mode to locked mode) Granularity: 2 lines 0000: 0 0110: 12 1111: 30 (Set equal to LPFOPOFF in BBh) x Automatic raster-shift enable 0: Allow raster shift if stable signals detected 1: Allow raster shift always x Reset joint line controller Reset of joint line controller for SSC mode 0: Enable 1: Reset x Master slave exchange Synchronize the display raster to the slave channel for master slave exchange 0: Display raster phase is synchronized to master channel 1: Display raster phase is synchronized to slave channel Static operation mode slave Defines the algorithm of upconversion for slave channel 000: (reserved) 001: ABAB () or A+B, A+B (+, +) 010: AABB () or A+A, B+B (+, +) 011: AAAA () or A+A, A+A (+, +) 100: AAAA () or A+A*, A+A* (+, +) 101: BBBB () or B+B, B+B (+, +) 110: BBBB () or B+B*, B+B* (+, +) 111: AA*B*B () or A+A*, B*+B (+, +) x External read Reading data via ITU R656 to an external controller 0: External read disabled 1: External read enabled x Port P3 disable 0: Enabled 1: Disabled x Port P4 disable 0: Enabled 1: Disabled Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET LPFOPOFF ARSDIS JLCRES MASLEX C0h W VSBS_36 STOPMOS x x x VSP 94x5B, VSP 94x7B EXTRD P3DIS P4DIS 187 Table 3-15: Common, continued Subadd R/W Take Over Name HPE1OFF A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Horizontal pixel erosion 1 0: On 1: Off x Vertical line erosion 0: On 1: Off x Horizontal pixel smearing 1 0: On 1: Off x Horizontal pixel erosion 2 0: On 1: Off x Horizontal pixel extension 0: On 1: Off x Vertical line extension 0: On 1: Off x Horizontal pixel smearing 2 0: On 1: Off x Vertical line smearing 0: On 1: Off 188 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B VLEROFF HPS1OFF HPE2OFF HPEXOFF VLEXOFF HPS2OFF VLS1OFF Formatter C1h W VSBM2_36 CHROMSIGN656 x Chrominance format for 656 output 0: (R-Y), (B-Y) output 1: -(R-Y), -(B-Y) output x Fieldoffset for ITU656 NTSC signals 0: Disabled 1: Enabled x Enable (single or double-scan) digital DP656 output 0: Disable output 1: Enable output x Shift UV subsampling at digital output 0: Take first UV couple 1: Take second UV couple x Stability signal of LL_HPLL 0: STABLL is generated accoding to SETSTABLL 1: STABLL is forced to 1 (hout synchronization enabled) FIOFFOFF PRELIMINARY DATA SHEET DPOUT656 SHIFTUV FSWFTL Micronas Table 3-15: Common, continued Subadd R/W Take Over Name AFPROC A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Active field processing for 656V generation 0: Inverted active field used as v-sync output 1: V-sync modifies end of active video x V656 delay 0: Identical delay for modification 1: Field 0 is one line shorter Note: Has only effect when AFPROC =1 x 656CLK output inversion 0: Normal cloct 1: Inverted clock X Horizontal output tristate 0: Normal operation 1: Tristate X Chroma output data format 0: Signed 2's complement 1: Binary X VOUT pin used as input 0: Output 1: Input X Digital output (drout, dbout, dgout) 0: Disabled 1: Enabled x Output mode 0: 4:4:4 1: 4:2:2 x Chroma subsampling filter 0: Disabled 1: Enabled x Noise shaper 0: Dabled 1: Enabled x Data width at output 0: 8-bit 1: 9-bit Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET V656DEL CLK656OUTINV HOUTTR UVCODE V100IN DIGOUTEN M422 VSP 94x5B, VSP 94x7B CHRSFM NSHAP DWO YUV_RGB C2h W VSBM2_36 C1[10:2] C2[10:2] C3h W VSBM2_36 C3[10:2] x x x x x x x x x x x x x x x x x x x x x x x x Matrix coefficient C1 (2c) 0: Default Matrix coefficient C2 (2c) 179: Default Matrix coefficient C3 (2c) -44: Default 189 Table 3-15: Common, continued Subadd R/W Take Over Name C4[10:2] C4h W VSBM2_36 C5[10:2] x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x Matrix coefficient C4 (2c) -91: Default Matrix coefficient C5 (2c) 227: Default C6[10:2] C5h W VSBM2_36 TO1RGB x x x x x x x x x x x Matrix coefficient C6 (2c) 0: Default RGB or YUV output selection 000: YUV output 001: RGB outpu (others): Reserved x Digital 601 output 0: Starting with U sample at beginning of line 1: Starting with V sample at beginning of line x x x x x x x x x x x Pixel Mixer C6h W VSBM2_36 WINDVSP x x Vertical window speed 00: Slow 01: medium 10: Fast 11: Very fast x Vertical windowing: Start 0: Window is closed 1: Window is open x Vertical windowing: Direction 0: Open the vertical window 1: Close the vertical window x Vertical windowing: Enable 0: Off 1: On x x x x x x x x x x x Horizontal position inside active picture area (int) 0: 0 pixel (int) 2047: 2047 pixel x (See C4h) (See C4h) (See C3h) (See C3h) (See C2h) (See C2h) 190 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B UENINV C6[1:0] C5[1:0] C4[1:0] C3[1:0] C2[1:0] C1[1:0] WINDVST PRELIMINARY DATA SHEET WINDVDR WINDVON HORPOSP Micronas Table 3-15: Common, continued Subadd C7h R/W Take Over W VSBM2_36 Name WINDHSP A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Horizontal windowing: Speed 00: Slow 01: Medium 10: Fast 11: Very fast x Horizontal windowing: Start 0: Window is closed 1: Window is open x Horizontal windowing: Direction 0: Open the horizontal window 1: Close the horizontal window x Horizontal windowing: Enable 0: Off 1: On x x x x x x x x x x x Horizontal position inside active picture area (int) 0: 0 pixel (int) 2047: 2047 pixel Luminance value for curtain (4MSB) 0001: Default value (yields value 0 0010 0000=32) x x Luminance amplification 00: 1 01: 5/4 10: 6/4 11: 8/4 x x x x x x x x x x Vertical start position of background (or test-pattern) (int) 0: 0 lines (int) 1023: lines Chrominance value for curtain (4MSB) 0000: Default value (yields value 0 0000 0000=0) x x Chrominance Amplification 00: -2 01: -1 10: +1 11: +2 x x x x x x x x x x Vertical width of background or pattern (or test-pattern) (int) 0: 0 lines (int) 1023: 1023 lines Chrominance value for curtain (4MSB) 0000: Default value (yields value 0 0000 0000=0) x x x x x x x x x x x Horizontal position of slave frame (int) 0: most left (int) 2047: most right Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET WINDHST WINDHDR WINDHON HORWIDTHP C8h W VSBM2_36 YCUR LUMAMP x x x x VERPOSP VSP 94x5B, VSP 94x7B C9h W VSBM2_36 UCUR CHROMAMP x x x x VERWIDTHP CAh W VSBS_36 VCUR HORPOSF x x x x 191 Table 3-15: Common, continued Subadd CBh R/W Take Over W VSBS_36 Name HORFRAMEF A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x Horizontal slave frame size (int) 0: 0 pixel (int) 31: 31 pixel x x x x x x x x x x x Horizontal width of slave frame hole (int) 0: 0 pixel (int) 2047: 2047 pixel Vertical slave frame size (int) 0: 0 lines (int) 31: 31 lines x x x x x x x x x x Vertical position of slave frame (int) 0: top (int) 1023: bottom Luminance Value for background (4MSB ) 0001: Default value (yields value 0 0010 0000=32) x x x x x x x x x x Vertical width of slave frame hole (int) 0: 0 lines (int) 1023: lines Chrominance value for background (4MSB) 0000: Default value (yields value 0 0000 0000=0) x x x x x x x x x x x Horizontal position of master frame (int) 0: most left (int) 2047: most right Chrominance value for background (4MSB) 0000: default value (yields value 0 0000 0000=0) x x x x x x x x x x x Horizontal width of master frame hole (int) 0: 0 pixel (int) 2047: 2047 pixel Horizontal master frame size (int) 0: 0 lines (int) 31: 31 lines 192 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B HORWIDTHF CCh W VSBS_36 VERFRAMEF x x x x x VERPOSF CDh W VSBS_36 YBAGR VERWIDTHF x x x x CEh W VSBM2_362 UBAGR HORPOSG x x x x CFh W VSBM2_36 VBAGR HORWIDTHG x x x x D0h W VSBM2_36 HORFRAMEG x x x x x PRELIMINARY DATA SHEET VERPOSG x x x x x x x x x x Vertical position of master frame (int) 0: top (int) 1023: bottom Vertical master frame size (int) 0: 0 lines (int) 31: 31 lines D1h W VSBM2_36 VERFRAMEG x x x x x VERWIDTHG x x x x x x x x x x Vertical width of master frame hole (int) 0: 0 lines (int) 1023: lines Micronas Table 3-15: Common, continued Subadd D2h R/W Take Over W VSBM2_36 Name PRIOP A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Priority background (or test-pattern) 000: 0 010: 4 111: 14 x Temporary overlapping flag 0: Static overblending 1: Temporal overblending x Overblending flag 0: No overblending 1: Soft overblending x x x Test-pattern mode 000: Trivial background mode 001: Trivial background mode 010: trivial background mode 011: Y-ramp (strong) 100: Y-ramp (soft) 101: YUV-ramp 110: Color bar 111: Crosshatch x x Time for smooth temporal overblending 00: 64 01: 128 10: 256 11: 512 x Frame dimension master 0: 2-dim. 1: 3-dim. Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET OBTEMP OBSOFT PATTMODE TBLEND FRAMEDIMM VSP 94x5B, VSP 94x7B FRAMEDIMS x Frame dimension slave 0: 2-dim. 1: 3-dim. Priority curtain 000: 0 001: 2 111: 14 D3h W VSBM2_36 PRIOC x x x PRIOS x x x Priority slave 000: 0 110: 12 111: 14 x x x Priority slave frame 000: 0 101: 10 111: 14 PRIOF 193 Table 3-15: Common, continued Subadd R/W Take Over Name PRIOM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Priority master 000: 0 100: 8 111: 14 x x x Priority master frame 000: 0 011: 6 111: 14 194 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B PRIOG Output sync controller D4h W VSBM2_36 BLANDEL x x x x x x x x Delay in pixels from hsync to active edge of blank signal: Blank_start=4*BLANDEL 00000000: No delay 00000001: 4 pixel delay 11111111: 1020 pixel delay x Vertical blank signal polarity 0: Positive 1: Negative x Output clock select 0: Clkout_o depends on CLKOUTSEL 1: Ckout_o is identical to clkb72 x CLKOUT inversion 0: No inverted CLKOUT 1: Inverted CLKOUT x HOUT polarity: 0: High active 1: Low active x VOUT polarity: 0: High active 1: Low active x Blank polarity: 0: Blank is high active 1: Blank is low active x Output clock select 0: Clkout_o is identical to clkb27 1: Clkout_o is identical to clkb36 Note: HSYNC, VSYNC, BLANK are transferred to selected clock x Output clock (pin clkout) 0: Disabled 1: Enabled Output clock select 0: CLKOUT depends on CLKOUTSEL 1: CLKOUT is identical to clkb72 VBLANPOL CLKOUT72 CLKOUTINV HOUTPOL VOUTPOL BLANPOL PRELIMINARY DATA SHEET CLKOUTSEL CLKOUTON Micronas D5h W VSBM2_36 CLKOUTSEL72 x Table 3-15: Common, continued Subadd R/W Take Over Name VBLANDEL[9:5] BLANLEN A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x x x x x x (see D6h) Length in pixels from start of active blank signal: Blank_length=4*BLANLEN 00000000: No pixel 11110000: 960 pixel 11111111: 1020 pixel length Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET Delay block D6h W VSBM2_36 VBLANDEL[4:0] x x x x x Vertical delay in lines from vsync to active edge of blank signal: Blank_start=4*VBLANDEL 00000000: No delay 11111111: 1020 lines delay x x x x x x x x x x Vertical length in lines from start of active blank signal: Blank_length=4*VBLANLEN 00000000: No line 11111111: 1020 lines Voltage level for Y DAC output 00000000: 0.4 V 10000000: 1.0 V 11111111: 1.9 V Note: Including peaking overshoots. 0.9V for white max. x x x x x x x x Voltage level for U DAC output 00000000: 0.4 V 10000000: 1.0 V 11111111: 1.9 V Luminance coarse delay output Granularity: 1 CLKB36 (27.8 ns for TV signal) 000: -4 CLKB36 100: No delay 111: +3 CLKB36 x Luminance fine delay output 0: No delay 1: +1 CLKB72 (13.9 ns for TV signal) x x x x x x x x Voltage level for U DAC output 00000000: 0.4 V 10000000: 1.0 V 11111111: 1.9 V VBLANLEN D7h W VSBM2_36 PKLY x x x x x x x x PKLU D8h W VSBM2_36 COARSEDEL x x x VSP 94x5B, VSP 94x7B FINEDEL PKLV C800 D9h DAh W W NTO NTO C800 VDELAY_BE x x x x x x x x x x x x x x x x x x C800 (reserved) 00: vertical synchronized takeover, no sychronisation of FE and BE 01: Update of BE register with the next BE v after update of the FE registers 10: Update of BE register like VDELAY_BE=1 plus one additional BE field delay 11: Update of BE register like VDELAY_BE=1 plus two additional BE fields delay 195 Table 3-15: Common, continued Subadd R/W Take Over Name VSEL_BE GPH50 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x 0: master channel synchonizes BE 1: slave channel synchonizes BE H50/IRQ-pin switching 00: Normal function 01: Normal function 10: H50/IRQ static 0 11: H50/IRQ static 1 x x VIN/INTR-pin switching 00: V-pin used as v-input for front-end 01: V-pin is output of C800 interrupt 10: V static 0 11: V static 1 x C800 processor 0: Processor enabled 1: Processor disabled x 196 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B CPUIRQ2V CPUDISABLE AUTOINC_OFF IC Autoincrement 0: Autoincrement after 2 byte access 1: No autoincrement Nr. of lines per field (input signal) 00000000: 256 lines or less 11111111: 766 lines or more LINES=2*LPFLD+256 Read Registers Master Channel DBh R VS1_20 LPFLDM x x x x x x x x NRPIXELM x x x x x x x x Pixel number of input signal Granularity: 4 00000000: 384 or less 11111111: 1404 or more PIXEL=4*NRPIXEL+384 Detected polarity of HSync 0: Negative 1: Positive DCh R VS1_20 DETHPOLM x PRELIMINARY DATA SHEET DETVPOLM x Detected polarity of V sync 0: Negative 1: Positive x x x Detected color standard 000: Non standard or standard not detected 001: NTSC M 010: PAL M 011: NTSC44 100: PAL60 101: PAL N 110: SECAM 111: PAL B/G STDETM Micronas Table 3-15: Common, continued Subadd R/W Take Over Name SCOUTENM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x SCDEV valid indication 0: SCDEV not valid 1: SCDEV valid x PAL identification 0: Not PAL 1: PAL x Colorkill status 0: Color off 1: Color on x Line standard detection 0: 60 Hz 1: 50 Hz x Interlace detection 0: Progressive input 1: Interlace input x x x x x x Deviation of clock system or color carrier 100000: Minimum deviation 000000: No deviation 011111: Maximum deviation Vertical flywheel mode locked 0: Unlocked 1: Locked x x x x x x x Length of vertical pulse 0000000: Short v 1111111: Long v x x x x x x AGC value for ADC1 000000: Smallest input range 111111: Biggest input range x PAL identification (algorithm 2) 0: Not PAL 1: PAL x Status of synchronization 0: Sync separation not locked 1: Sync separation locked and stable Noise level of the input signal (blanking algorithm): 0000000: No noise 1111110: Strong noise 1111111: Strong noise or measurement failed x x x x x x x x Noise level of the input signal (picture algorithm): 00000000: No noise 11111111: Strong noise Cyclic field counter Input processing master Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET PALIDM CKSTATM LNSTDRDM INTM SCDEVM DDh R VFLYMDM x VLENGTHM VSP 94x5B, VSP 94x7B AGCADJCV1 PALDETM STABM DEh R VSM1_40 NOISEMEM x x x x x x x NOISE 197 DFh R VSM2_40 FCIM x x x x Table 3-15: Common, continued Subadd R/W Take Over Name STATSIZE A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x Statistic of homogenous areas 00: Not enough homogenous areas 11: Many homogenous areas found x x x x Film mode detection value: 0000: Camera mode (secure detection) 0001: Film mode PAL phase 0 (secure detection) 0010: Film mode PAL phase 1 (secure detection) 0011: Film mode NTSC phase 0 (secure detection) 0100: Film mode NTSC phase 1 (secure detection) 0101: Film mode NTSC phase 2 (secure detection) 0110: Film mode NTSC phase 3 (secure detection) 0111: Film mode NTSC phase 4 secure detection) 1000: Camera mode (unsecure detection) 1001: Film mode PAL phase 0 (unsecure detection) 1010: Film mode PAL phase 1 (unsecure detection) 1011: Film mode NTSC phase 0 (unsecure detection) 1100: Film mode NTSC phase 1 (unsecure detection) 1101: Film mode NTSC phase 2 (unsecure detection) 1110: Film mode NTSC phase 3 (unsecure detection) 1111: Film mode NTSC phase 4 (unsecure detection) Film mode detection register value Global motion detection register value x Global still detection value: 0: Picture status: not still 1: Picture status: still x Global motion detection value: 0: Picture status: no motion 1: Picture status: in motion Last detected Standard 50 Hz 0: PAL or none 1: SECAM x Last detected Standard 60 Hz 0: NTSC M or none 1: NTSC44 or PAL60 x Status bit for letter box detection: 0: No new value available 1: New value from Letter Box Detection available x Indicates new value of the global motion detector available 0: NOISESTATUS has not been updated 1: New value of NOISESTATUS available reset automatically when read 198 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B FILMMODEM E0h E1h R R VSM2_40 VSM2_40 FMOTREGM GMOTREGM GSTILLM x x x x x x x x x x x x x x x x x x x x x x x x x x x x GMOTIONM E2h R NTO/RSTYP AM50_OM x AM60_OM PRELIMINARY DATA SHEET LBSTATUS NOISESTATUS Micronas Table 3-15: Common, continued Subadd R/W Take Over Name GMDSTATUSM A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Indicates new value of the gobal motion detector available 0: GMDSTATUS has not been updated 1: New value of GMDSTATUS available reset automatically when read x Indicates new value of the film mode detector available 0: FMSTATUS has not been updated 1: New value of FMSTATUS available reset automatically when read x Indicates new value of the noise measurement 0: NOISEME has not been updated 1: New value of NOISEME available reset automatically when read Calculated pivot point Pivot point=12.5 IRE+(TFDPPM+192)*0.192 IRE TFDDPM is limited to -192....-44 Pivot point is in the range of 12.5 IRE ...41 IRE x x x x x x x x x x Calculated gain segment 1 Gain_Segment_1=1+GAINSEG1FRCM/1024 GAINSEG1FRCM is limited to 0...510 Gain_Segment_1 is in the range of 1 ... 1.5 E4h R VSDCI_36 TFDPPM[3:0] GAINSEG2FRCM x x x x x x x x x x x x x x (See E3h) Calculated gain segment 2 Gain_Segment_2=1+GAINSEG2FRCM/1024 GAINSEG2FRCM is limited to 0...716 Gain_Segment_2 is in the range of 1 ... 1.7 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET FMSTATUSM NMSTATUSM E3h R VSDCI_36 TFDPPM[8:4] x x x x x GAINSEG1FRCM VSP 94x5B, VSP 94x7B Read registers slave channel E5h R VS1_20 LPFLDS x x x x x x x x Nr. of lines per field (input signal) 00000000: 256 lines or less 11111111: 766 lines or more LINES=2*LPFLD+256 x x x x x x x x Pixel number of input signal Granularity: 4 00000000: 384 or less 11111111: 1404 or more PIXEL=4*NRPIXEL+384 Detected polarity of H Sync 0: Negative 1: Positive x Detected polarity of V Sync 0: Negative 1: Positive NRPIXELS E6h R VS1_20 DETHPOLS x DETVPOLS 199 Table 3-15: Common, continued Subadd R/W Take Over Name STDETS A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Detected color standard 000: Non standard or standard not detected 001: NTSC M 010: PAL M 011: NTSC44 100: PAL60 101: PAL N 110: SECAM 111: PAL B/G x SCDEV valid indication 0: SCDEV not valid 1: SCDEV valid x PAL identification 0: Not PAL 1:PAL x Colorkill status 0: Color off 1: Color on x Line standard detection 0: 60 Hz 1: 50 Hz x Interlace detection 0: Progressive input 1: Interlace input x x x x x x Deviation of clock system or color carrier 100000: Minimum deviation 000000: No deviation 011111: Maximum deviation Vertical flywheel mode locked 0: Unlocked 1: Locked x x x x x x x Length of vertical pulse 0000000: Short v 1111111: Long v x x x x x x AGC value for ADC2 000000: Smallest input range 111111: Biggest input range x PAL identification (algorithm 2) 0: Not PAL 1: PAL x Status of synchronization 0: Sync separation not locked 1: Sync separation locked and stable 200 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B SCOUTENS PALIDS CKSTATS LNSTDRDS INTS SCDEVS E7h R VS1_20 VFLYMDS x VLENGTHS PRELIMINARY DATA SHEET AGCADJCV2 PALDETS Micronas STABS Table 3-15: Common, continued Subadd E8h R/W Take Over R VSS1_40 Name NOISEMES A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x Noise level of the input signal (blanking algorithm): 0000000: No noise 1111110: Strong noise 1111111: Strong noise or measurement failed Last detected standard 50 Hz 0: PAL or none 1: SECAM x Last detected standard 60 Hz 0: NTSC M or none 1: NTSC44 or PAL60 x Indicates new value of the noise measurement 0: NOISEME has not been updated 1: New value of NOISEME available reset automatically when read Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET E9h R NTO/RSTYP AM50_OS x AM60_OS NMSTATUSS Read Registers Common Channel EAh R VSSLI_20 DATA_CCWSS2 DATA_CCWSS1 EBh R VSSLI_20 DATA_USWSS3 DATA_USWSS2 ECh R VSSLI_20 DATA_USWSS1 POR x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Second CC or WSS DATA Byte (A7=MSB, A0=LSB) First CC or WSS DATA Byte(B7=MSB, B0=LSB) Third US-WSS DATA Byte (A7=MSB, A0=LSB) Second US-WSS DATA Byte(B7=MSB, B0=LSB) First US-WSS DATA Byte (A7=MSB, A0=LSB) Reset indication A reset at pin 24 (reset) sets POR. POR is reset with PORCNCL (9Bh) 0: No reset appeared 1: Reset appeared x TV mode detection 0: Comb filter input is nonstandard signal (VCR) 1: Comb filter input is standard signal (TV) x Field number of sliced data (US-WSS) 0: First field 1: Second field x New data indication (US WSS) 0: Data read via IC or no new data available 1: New data received and available in DATAA and DATAB x Field number of sliced data (CC or WSS) 0: First field 1: Second field x New data indication (CC or WSS 0: Data read via IC or no new data available 1: New data received and available in DATAA and DATAB VSP 94x5B, VSP 94x7B TVMODE SLFLDUSWSS DATAVUSWSS SLFLDCCWSS DATAVCCWSS 201 Table 3-15: Common, continued Subadd EDh R/W Take Over R NTO/RSTYP Name FBSTAT A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Indicates overflow at FBL input 0: No overflow 1: Overflow x Indicates falling edge at FBL input 0: No falling edge 1: Flling edge detected Reset automatically when read x Indicates rising edge at FBL input 0: No rising edge 1: Rising edge detected Reset automatically when read x Indicates overflow at FBL input 0: No overflow 1: Overflow x Indicates overflow at GREEN input 0: No overflow 1: Overflow x Indicates overflow at BLUE input 0: No overflow 1: Overflow x Indicates overflow at RED input 0: No overflow 1: Overflow x Activity at FBL input 0: No activity 1: Activity Reset automatically when read Letter box detection: Maximum gradient upper part Internal value, only for test purposes Letter box detection: Maximum gradient lower part Internal value, only for test purposes (see F1h) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Letter box detection: Maximum histogram upper part Internal value, only for test purposes Letter box detection: Maximum activity lower part Internal value, only for test purposes Letter box detection: Maximum histogram lower part Internal value, only for test purposes Letter box detection: Gradient start line of active area Internal value, only for test purposes 202 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B FBFALL FBRISE PFBL PG PB PR FBLACTIVE EEh EFh F0h R R R VSM1_40 VSM1_40 VSM1_40 MAXGUC MAXGLC MAXALC MAXHUC x x x x x x x x x x x x x x x x x x x x x x x x PRELIMINARY DATA SHEET F1h R VSM1_40 MAXALC MAXHLC Micronas F2h R VSM1_40 GRADSLAA Table 3-15: Common, continued Subadd R/W Take Over Name MAXAUC F3h R VSM1_40 LBFORMAT x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x Letter box detection: Maximum activity upper part Internal value, only for test purposes Letter box detection: Format 0: 4:3 format 1: Other format (letter box) x Letter box detection: Subtitle flag 0: No subtitle 1: Subtitle available x Letter box detection: Toptitle flag 0: No toptitle 1: Toptitle available x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Letter box detection: Gradient is stable Internal value, only for test purposes Letter box detection: Upper area contains high activity Internal value, only for test purposes Letter box detection: Lower area contains high activity Internal value, only for test purposes Letter box detection: No gradient found Internal value, only for test purposes Letter box detection: Switch to 4:3 format Internal value, only for test purposes Letter box detection: Upper area contains high brightness level Internal value, only for test purposes Letter box detection: Lower area contains high brightness level Internal value, only for test purposes Letter box detection: Upper area contains medium brightness level Internal value, only for test purposes Letter box detection: Lower area contains medium brightness level Internal value, only for test purposes Letter box detection: Start line of active area LBSLAA is measured in relation to VSYNC Letter box detection: End line of active area LBELAA is measured in relation to VSYNC Letter box detection: Gradient end line of active area Internal value, only for test purposes Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET LBSUBTITLE LBTOPTITLE GRADISSTABLE TOPTITLE SUBTITLE NOGRADFOUND SWITCHTO43 UPWHITE LPWHITE UPBLACK LPBLACK F4h R VSM1_40 LBSLAA LBELAA F5h R VSM1_40 GRADELAA VSP 94x5B, VSP 94x7B 203 Table 3-15: Common, continued Subadd F6h R/W Take Over R NTO Name VERSION A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x Version of VSP 94xx family: 010: VSP 94x2A 001: VSP 94x5B 011:VSP 94x7B 101: VSP 94x9C x Line standard at device output 0: 100 Hz 1: 50 Hz x x x x Revision of VSP 94xxB family: 0000: A11 0001: B11 0100: C1 x x x x x x = Readable value of RMODE Chip ID 0000: VSP9405B / VSP 9425B (double scan mode) 0001: VSP9407B / VSP 9427B (double scan mode) 0010: VSP9435B / VSP 9425B (single scan mode) 0011: VSP9437B / VSP 9427B (single scan mode) 0100: VSP9415B 0101: VSP9417B 0110: VSP9445B 0111: VSP9447B x Shows LL-HPLL lock status 0: LL_HPLL is not locked 1: LL_HPLL is locked Ancillary data (656 input) 0: not detected 1: detected x Field output CD1 0: First field 1: Second field x Field output CD2 0: First field 1: Second field x V status bit of 40.5 MHz domain (RGB) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 36 MHz domain (back-end master 2) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 36 MHz domain (Back-end master 2) 0: New write or read cycle can start 1: No new write or read cycle can start 204 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B SLS REV RMMIRROR CHIPID STABLL F7h R NTO ADR_RDY x FIELDCD1 FIELDCD2 PRELIMINARY DATA SHEET VSRGB_40STAT VSBM2_36STAT Micronas VSBM1_36STAT Table 3-15: Common, continued Subadd R/W Take Over Name VSDCI_36STAT A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x V status bit of 36 MHz domain (DCI) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 36 MHz domain (back-end slave) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 20.25 MHz domain (data slicer) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 40.5 MHz domain (input slave 2) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 40.5 MHz domain (input slave 1) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 40.5 MHz domain (input master 2) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 40.5 MHz domain (input master 1) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 27 MHz domain (ITU) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 20.25 MHz domain (CD 2) 0: New write or read cycle can start 1: No new write or read cycle can start x V status bit of 20.25 MHz domain (CD 1) 0: New write or read cycle can start 1: No new write or read cycle can start Cyclic field counter output processing master x Raster phase shifting active Indication of performing display raster phase shifting for joint line free SSC1 mode 0: Phase shift not active 1: Phase shift in progress ITU656 input data byte 1 x x x x x x x x x x x x x x x x x x x x x x x x ITU656 input data byte 0 ITU656 input data byte 3 ITU656 input data byte 2 Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET VSBS_36STAT VSSLI_20STAT VSS2_40STAT VSS1_40STAT VSM2_40STAT VSM1_40STAT VS656_27STAT VS2_20STAT VSP 94x5B, VSP 94x7B VS1_20STAT F8h R VSBM2_36 FCBM SHIFTACT x x x x F9h R VS656_27 ADATA0 ADATA1 x x x x x x x x FAh R VS656_27 ADATA2 ADATA3 205 Table 3-15: Common, continued Subadd FBh R/W Take Over R VS656_27 Name ADATA4 ADATA5 FCh R VS656_27 ADATA6 ADATA7 x x x x x x x x x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x x x x x x x x x x x x x x x x ITU656 input data byte 5 ITU656 input data byte 4 ITU656 input data byte 7 ITU656 input data byte 6 206 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B Command Registers FDh FEh W W C800 IMRGB_40 x C800 (reserved) Immediate take-over 40.5 MHz domain (RGB) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 36 MHz dom. (back-end master 2) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 36 MHz dom. (back-end master 1) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 36 MHz domain (back-end master) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 36 MHz domain (back-end slave) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 20.25 MHz domain (data slicer) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 40.5 MHz domain (input slave 2) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 40.5 MHz domain (input slave 1) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 40.5 MHz domain (input master 2) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 40.5 MHz domain (input master 1) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 27 MHz domain (ITU) 0: No immediate take-over 1: Immediate take-over IMBM2_36 IMBM1_36 IMDCI_36 IMBS_36 IMSLI_20 IMS2_40 IMS1_40 PRELIMINARY DATA SHEET IMM2_40 IMM1_40 Micronas IM656_27 Table 3-15: Common, continued Subadd R/W Take Over Name IM2_20 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x Immediate take-over 20.25 MHz domain (CD 2) 0: No immediate take-over 1: Immediate take-over x Immediate take-over 20.25 MHz domain (CD 1) 0: No immediate take-over 1: Immediate take-over V take-over 40.5 MHz domain (RGB) 0: No V take-over 1: V take-over x V take-over 36 MHz dom. (back-end master 2) 0: No V take-over 1: V take-over x V take-over 36 MHz dom. (back-end master 1) 0: No V take-over 1: V take-over x V take-over 36 MHz domain (back-end master) 0: No V take-over 1: V take-over x V take-over 36 MHz domain (back-end slave) 0: No V take-over 1: V take-over x V take-over 20.25 MHz domain (data slicer) 0: No V take-over 1: V take-over x V take-over 40.5 MHz domain (iInput slave 2) 0: No V take-over 1: V take-over x V take-over 40.5 MHz domain (input slave 1) 0: No V take-over 1: V take-over x V take-over 40.5 MHz domain (input master 2) 0: No V take-over 1: V take-over x V take-over 40.5 MHz domain (input master 1) 0: No V take-over 1: V take-over x V take-over 27 MHz domain (ITU) 0: No V take-over 1: V take-over x V take-over 20.25 MHz domain (CD 2) 0: No V take-over 1: V take-over Micronas Nov. 28, 2002; 6251-576-3PD PRELIMINARY DATA SHEET IM1_20 FFh W VSRGB_40 x VSBM2_36 VSBM1_36 VSDCI_36 VSBS_36 VSSLI_20 VSS2_40 VSP 94x5B, VSP 94x7B VSS1_40 VSM2_40 VSM1_40 VS656_27 VS2_20 207 Table 3-15: Common, continued Subadd R/W Take Over Name VS1_20 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Description x V take-over 20.25 MHz domain (CD 1) 0: No V take-over 1: V take-over 208 Nov. 28, 2002; 6251-576-3PD VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 4. Specifications 4.1. Outline Dimensions 0.18 0.05 60 41 19 x 0.65 = 12.35 0.1 0.65 61 40 0.3 0.05 0.65 + 0.1 80 21 1 17.2 0.15 20 2.0 - 0.05 2.15 0.2 0.1 14 0.1 SPGS706000-7(P80)/1E Fig. 4-1: 80-Pin Plastic Metric Quad Flat Pack (MQFP80) Weight approximately 0.96 g Dimensions in mm 0.17 0.05 108 73 35 x 0.65 = 22.75 0.1 0.65 109 72 0.65 0.32 0.07 19 x 0.65 = 12.35 0.1 17.2 0.15 14 0.1 144 37 1 31.2 0.1 36 3.7 0.2 3.4 0.08 0.1 28 0.1 SPGS706000-7(P144)/1E Fig. 4-2: 144-Pin Plastic Metric Quad Flat Pack (MQFP144) Weight approximately 5.5 g Dimensions in mm Micronas 35 x 0.65 = 22.75 0.1 31.2 0.1 28 0.1 Nov. 28, 2002; 6251-576-3PD 209 VSP 94x5B, VSP 94x7B 4.2. Pin Connections and Short Descriptions for VSP 94xxB PRELIMINARY DATA SHEET For VSP 941x/4x, the pin connections differ for pins: 1, 2, 3, 75, 76, 77, 78, 79 ,80 (see Section 4.2.2. on page 215). 4.2.1. Common Pin Connection and Short Descriptions Pin No. MQFP 80-pin 1 2 MQFP 144-pin 1 VDDDACY AYOUT S O Leave open or connect to vss and disable DAC Pin Name Type Connection (If not used) Short Description DAC (Y) Y output 3 4 5 6 7 8 3 4 5 10 13 14 VSSDACY VSSD2 VDDD2 SDA TMS 656VIN/BLANK1) S S S I/O I I/O Connect to vss and disable blank Leave open Leave open DAC (Y) Supply voltage for digital (0 V digital) Supply voltage for digital (1.8 V digital) I2C-Bus data Testmode select (Connected to vdd33) Separate V input for 656 / BLANK output 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 15 16 19 20 28 29 30 31 32 33 34 35 37 38 39 656CLK 656IO7 VSSP2 VDDP2 SCL V2) 656IO6 656IO5 HOUT H503) ADR / TDI V504) 656IO4 656IO3 VOUT I/O I/O S S I I I/O I/O O O I O I/O I/O O Digital input / output clock Digital input / output (MSB) Supply voltage for digital (0 V pad) Supply voltage for digital (3.3 V pad) I2C-Bus clk Connect to vss Leave open Leave open Leave open Leave open Vertical pulse for RGB input Digital input / output Digital input / output Horizontal output (Single or double scan, dependent on version) Hout 50 Hz (with skew) I2C address / test data in Leave open Leave open Leave open Leave open Vout 50 Hz Digital input / output Digital input / output Vertical output (Single or double scan, dependent on version) 210 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Pin No. MQFP 80-pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 MQFP 144-pin 40 41 42 51 58 59 60 61 62 63 64 65 66 67 68 70 72 73 74 75 76 77 78 80 82 89 92 93 96 97 Pin Name Type Connection (If not used) Short Description RESET VDDP3 VSSP3 CLKOUT VDDD3 VSSD3 656IO2 656IO1 656IO0 VSSD4 VDDD4 VDDAFBL VSSAFBL FBL1 FBL2 RIN1 GIN1 BIN1 VDDARGB VSSARGB VDD33RGB VSS33RGB RIN2 GIN2 BIN2 VSSD55) VDDAC1 VSSAC1 CVBS1 CVBS2 I S S O S S I/O I/O I/O S S S S I I I I I S S S S I I I S S S I I Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Leave open Leave open Leave open Leave open Reset input (Reset active low) Supply voltage for digital (0 V pad) Supply voltage for digital (3.3 V pad) Output clock (27 MHz nom.) Supply voltage for DRAM (1.8 V digital) Supply voltage for digital (0 V digital) Digital input / output Digital input / output Digital input / output (LSB) Supply voltage for digital (0 V digital) Supply voltage for digital 1.8 V digital Supply voltage for FBL (1.8 V) Supply voltage for FBL (0 V) Fast Blank input 1 (H1) (Analog input) Fast Blank input 2 (H2) (Analog input) R or V in1 (Analog input) G or Y in1 (Analog input) B of U in1 (Analog input) Supply voltage for RGB (1.8 V) Supply voltage for RGB (0 V) Supply voltage RGB (3.3 V) Supply voltage RGB (0 V) R or V in2 (Analog input) G or Y in2 (Analog input) B of U in2 (Analog inpu) Supply voltage for digital (0 V) Supply voltage CVBS1 (1.8 V) and digital core supply Supply voltage CVBS1 (0 V) CVBS input (Analog input) CVBS input (Analog input) Micronas Nov. 28, 2002; 6251-576-3PD 211 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Pin No. MQFP 80-pin 54 55 56 57 58 MQFP 144-pin 98 100 102 104 106 94 95 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 107 108 111 110 109 112 113 117 118 119 122 123 129 130 131 138 Pin Name Type Connection (If not used) Short Description CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 CVBS8 CVBS9 VDD33C VSS33C CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20 I I I I I I I S S O O O S S S S S O I I S S I/O Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss Connect to vss CVBS input (Analog input) CVBS input or Y1 (Analog input) CVBS input or C1 (Analog input) CVBS input or Y2 (Analog input) CVBS input or C2 (Analog input) CVBS input (Analog input) CVBS input (Analog input) Supply voltage CVBS (3.3 V) Supply voltage CVBS (0 V) Leave open Leave open Leave open CVBS output 3 (Analog output) CVBS output 2 (Analog output) CVBS output 1 (Analog output Supply voltage CVBS2 (1.8 V) Supply voltage CVBS2 (0 V) Supply voltage for digital (1.8 V digital) Supply voltage for digital (0 V digital) Supply voltage for PLL (1.8 V) Crystal connection 2 Crystal connection 1 Testclock Supply voltage for digital (3.3 V pad) Supply voltage for digital (0 V pad) Connect to vss and disable clock Separate H input for 656 / 20.25 clock output DAC (V) 75 76 139 140 VDDDACV AVOUT S O Leave open or connect to vss and disable DAC V output 77 78 141 142 VSSDACV VDDDACU S S DAC (V) DAC (U) 212 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Pin No. MQFP 80-pin 79 MQFP 144-pin 143 Pin Name Type Connection (If not used) Short Description AUOUT O Leave open or connect to vss and disable DAC U output 80 144 11 12 36 50 55 56 86 87 88 120 121 134 135 17 57 85 84 83 133 136 137 69 71 79 81 99 101 VSSDACU VDDP4 VSSP4 VSSPDB1 VSSP3 VDDP5 VSSP5 VDDPOR VDDP6 VSSP6 VSSP7 VDDP7 VSSP8 VDDP8 (reserved) (reserved) GP2 GP1 GP0 (reserved) (reserved) (reserved) (NC) (NC) (NC) (NC) (NC) (NC) S DAC (U) Supply voltage for digital (3.3 V) Supply voltage for digital (0 V) Bulk supply voltage (0 V) Supply voltage for digital (0 V) Supply voltage for digital (3.3 V) Supply voltage for digital (0 V) Supply voltage for digital (1.8 V) Supply voltage for digital (3.3 V) Supply voltage for digital (0 V) Supply voltage for digital (0 V) Supply voltage for digital (3.3 V) Supply voltage for digital (0 V) Supply voltage for digital (3.3 V) Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open (Reserved) (Reserved) General purpose pin 2 General purpose pin 1 General purpose pin 0 (Reserved) (Reserved) (Reserved) (Not connected) (Not connected) (Not connected) (Not connected) (Not connected) (Not connected) Micronas Nov. 28, 2002; 6251-576-3PD 213 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Pin No. MQFP 80-pin MQFP 144-pin 103 105 54 53 52 48 47 46 45 44 43 25 24 23 22 21 9 8 7 6 132 128 127 126 125 124 116 115 114 91 Pin Name Type Connection (If not used) Short Description (NC) (NC) DROUT0 DROUT1 DROUT2 DROUT3 DROUT4 DROUT5 DROUT6 DROUT7 DROUT8 DGOUT0 DGOUT1 DGOUT2 DGOUT3 DGOUT4 DGOUT5 DGOUT6 DGOUT7 DGOUT8 DBOUT0 DBOUT1 DBOUT2 DBOUT3 DBOUT4 DBOUT5 DBOUT6 DBOUT7 DBOUT8 SISCEN O O O O O O O O O O O O O O O O O O O O O O O O O O O I Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open (Not connected) (Not connected) Digital out red Digital out red Digital out red Digital out red Digital out red Digital out red Digital out red Digital out red Digital out red Digital out green/656out0 Digital out green/656out1 Digital out green/656out2 Digital out green/656out3 Digital out green/656out4 Digital out green/656out5 Digital out green/656out6 Digital out green/656out7 Digital out green Digital out blue Digital out blue Digital out blue Digital out blue Digital out blue Digital out blue Digital out blue Digital out blue Digital out blue Single-scan enable 214 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Pin No. MQFP 80-pin MQFP 144-pin 18 1) Pin Name Type Connection (If not used) Short Description TDO O Leave open Test data out This pin is not used and not bonded in VSP 94x2A. All VDDPx, VSSx and VDDDx must be connected within their group with low resistance. Analog supplies are internally connected to digital supplies via antiparallel diodes. 4.2.2. Differing Pin Connections and Short Descriptions for VSP 941xB and VSP 944xB Pin No. MQFP 80-pin 1 2 3 75 Pin Name Type Connection (If not used) Short Description I656I5 I656I6 I656I7 I656ICLK I I I I Connect to Vdd (3.3V) Connect to Vss 656 input 656 input 656 input (MSB) Connect to Vdd (3.3V) (or leave open) Connect to Vss 656 input clock (27 MHz nom.) 76 77 78 79 80 I656I0 I656I1 I656I2 I656I3 I656I4 I I I I I 656 input (LBS) 656 input Connect to Vdd (3.3V) Connect to Vss 656 input 656 input 656 input Micronas Nov. 28, 2002; 6251-576-3PD 215 VSP 94x5B, VSP 94x7B 4.3. Pin Configurations VSSAC1 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VDD33C VSS33C VDDAC1 VSSD5 BIN2 GIN2 RIN2 VSS33RGB VDD33RGB PRELIMINARY DATA SHEET VSSARGB VDDARGB BIN1 CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20 VDDDACV AVOUT VSSDACV VDDDACU AUOUT VSSDACU 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 33 32 GIN1 RIN1 FBL2 FBL1 VSSAFBL VDDAFBL VDDD4 VSSD4 656IO0 656IO1 656IO2 VSSD3 VDDD3 CLKOUT VSSP3 VDDP3 RESET VOUT 656IO3 656IO4 VSP 9405 B VSP 9407 B VSP 9435 B VSP 9437 B 31 30 29 28 27 26 25 24 23 22 21 10 11 12 13 14 15 16 17 18 19 20 VDDACY AYOUT VSSDACY VSSD2 VDDD2 SDA TMS 656VIN/BLANK 656CLK 656IO7 V50/BLANK ADR/TDI H50/IRQ HOUT 656IO5 656IO6 V/INTR SCL VDDP2 VSSP2 Fig. 4-3: MQFP80 package: 9405/07/35/37 versions 216 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B VSSAC1 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 VDD33C VSS33C VDDAC1 VSSD5 BIN2 GIN2 RIN2 VSS33RGB VDD33RGB VSSARGB VDDARGB BIN1 CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 VDDD1 VSSD1 VDDAPLL XOUT XIN TCLK VDDP1 VSSP1 656HIN/CLKF20 I656ICLK I656I0 I656I1 I656I2 I656I3 I656I4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 33 32 GIN1 RIN1 FBL2 FBL1 VSSAFBL VDDAFBL VDDD4 VSSD4 656IO0 656IO1 656IO2 VSSD3 VDDD3 CLKOUT VSSP3 VDDP3 RESET VOUT 656IO3 656IO4 VSP 9415 B VSP 9417 B VSP 9445 B VSP 9447 B 31 30 29 28 27 26 25 24 23 22 21 10 11 12 13 14 15 16 17 18 19 20 I656I5 I656I6 I656I7 VSSD2 VDDD2 SDA TMS 656VIN/BLANK 656CLK 656IO7 V SCL VDDP2 VSSP2 H50 HOUT 656IO5 656IO6 V50 ADR/TDI Fig. 4-4: MQFP80 package: 9415/17/45/47 versions Micronas Nov. 28, 2002; 6251-576-3PD 217 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET SISCEN VDDAC1 VSSAC1 CVBS8 CVBS9 CVBS1 CVBS2 CVBS3 (NC) CVBS4 (NC) CVBS5 (NC) CVBS6 (NC) CVBS7 VDD33C VSS33C VDDD5 VSSD5 VSSP6 VDDP6 VDDPOR (RESERVED) (RESERVED) (RESERVED) BIN2 (NC) GIN2 (NC) RIN2 VSS33RGB VDD33RGB VSSARGB VDDARGB BIN1 108107106105104103102101100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 CVBSO3 CVBSO2 CVBSO1 VDDAC2 VSSAC2 DBOUT8 DBOUT7 DBOUT6 VDDD1 VSSD1 VDDAPLL VSSP7 VDDP7 XOUT XIN DBOUT5 DBOUT4 DBOUT3 DBOUT2 DBOUT1 TCLK VDDP1 VSSP1 DBOUT0 (RESERVED) VSSP8 VDDP8 (RESERVED) (RESERVED) 656HIO/CLKF20 VDDDACV AVOUT VSSDACV VDDDACU AUOUT VSSDACU 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 GIN1 (NC) RIN1 (NC) FBL2 FBL1 VSSAFBL VDDAFBL VDDD4 VSSD4 656IO0 656IO1 656IO2 VSSD3 VDDD3 (RESERVED) VSSP5 VDDP5 DROUT0 DROUT1 DROUT2 CLKOUT VSSP3 VDDP3 DROUT3 DROUT4 DROUT5 DROUT6 DROUT7 DROUT8 VSSP3 VDDP3 RESET VOUT 656IO3 656IO4 VSP 9425 B VSP 9427 B 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDDDACY AYOUT VSSDACY VSSD2 VDDD2 DGOUT8 DGOUT7 DGOUT6 DGOUT5 SDA VDDP4 VSSP4 TMS 656VIO/BLANK 656CLK 656IO7 (RESERVED) TDO VSSP2 VDDP2 VSSP2 DGOUT0 DGOUT1 DGOUT2 DGOUT3 DGOUT4 VDDP2 SCL 656IO5 656IO6 VIN/INTR HOUT VSSPDB1 V50/BLANK TDI/ADR H50/IRQ Fig. 4-5: MQFP144 package: 9425 and 9427 versions 218 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B IC selectable VSP 940xA VSP 943xA VSP 940xB VSP 943xB VSP 940xA VSP 943xA VSP 940xB VSP 943xB Analog Output Analog Output Single-scan 656 input (port 1) Single-scan 656 output (943x) or Double-scan 656 output (940x) Fig. 4-6: Signal flow 940x, 943x Digital output (YUV or RGB or 656) VSP 941xA VSP 944xA VSP 941xB VSP 944xB Analog output VSP 9425B VSP 9427B Single-scan 656 input (port 2) Single-scan 656 output (944x) or Double-scan 656 output (941x) Single-scan 656 input (port 1) Fig. 4-7: Signal flow 941x, 944x, 942x Micronas Nov. 28, 2002; 6251-576-3PD 219 VSP 94x5B, VSP 94x7B 4.4. Pin Circuits PRELIMINARY DATA SHEET VSSP PIN VDDP OUT PIN VSSB Fig. 4-8: Supply Pins (Ground): VSSDACY, VSSDACU, VSSDACV, VSS33C, VSS33RGB, VSSP1 ... VSSP8, VSSPDB1 Fig. 4-12: Digital Output Pins: H50, V50, CLKOUT, HOUT, VOUT, DGOUT0 ... DGOUT8, DROUT0 ... DROUT8, DBOUT0 ... DBOUT8 VDDP PIN VDDP PIN IN VSSB Fig. 4-9: Supply Pins (Power 3.3 V): VDDDACY, VDDDACU, VDDACV, VDD33C, VDD33RGB, VDDP1 ... VDDP8, VDDPOR Fig. 4-13: Digital Input Pins: V, TMS, ADR/TDI, RESET, TCLK REF (int.) OSCCLK VDDP IN XIN XOUT OUT PIN Fig. 4-10: Input/Output Pins (Crystal connection): XIN, XOUT Fig. 4-14: I2C bus Pins: SDA, SCL VDD PIN VDDP VSS PIN OUT VSSB 500 IN Fig. 4-11: Supply Pins (Power 1.8 V and Ground): VDDAC1, VSSAC1, VDDAC2, VSSAC2, VDDARGB,VSSARGB, VDDAFBL, VSSAFBL, VDDAPLL, VDDD1, VSSS1, VDDD2, VSSS2, VDDD3, VSSS3, VDDD4, VSSS4, VDDD5, VSSS5 PIN Fig. 4-15: Digital Input/Output Pins: 656IOX,656CLK, 656HIN/CLKF20, 656VIN/BLANK 220 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B VDDDACx VDD display DAC PIN 150 PIN 300k 500 1V Fig. 4-16: Analog Output Pins: AYOUT, AUOUT, AVOUT Fig. 4-18: Analog Input Pins: CVBS1...CVBS9 (if cvbsx is not connected to any ADC) VDD VDD PIN 500 500 OUT IN PIN Fig. 4-19: Analog Output Pins: CVBSO1...CVBSO3 Fig. 4-17: Analog Input Pins: RIN1, RIN2, GIN1, GIN2, BIN1, BIN2, FBL1, FBL2, CVBS1...CVBS9 (if cvbsx is connected to any ADC) Micronas Nov. 28, 2002; 6251-576-3PD 221 VSP 94x5B, VSP 94x7B 4.5. Electrical Characteristics 4.5.1. Absolute Maximum Ratings All voltages listed are referenced to ground (0 V, VSS) except where noted. Symbol TA TS TC VI VO VDD1 VDD2 Ptot80 Ptot144 1) 2) 3) 4) 5) PRELIMINARY DATA SHEET Parameter Ambient Operating Temperature Storage Temperature Case Operating Temperature Input Voltage 1) Output Voltage 2) Supply Voltages1 Supply Voltages2 Total Power Dissipation QFP803) Total Power Dissipation QFP1443) Pin Name - - - - - - - - - Min. 0 -45 - -0.3 -0.3 -0.3 -0.3 Max. +70 +125 +115 VDD2+0.3 VDD2+0.3 24) 5) 3.64) 5) 1.2 1.2 Unit C C C V V V V W W Not valid for VDD1 supply pins Not valid for VDD1 supply pins Package limit VDD2 (3.3V nom.) must always be higher than VDD1 (1.8V nom.) - 0.3 (even during power-up) The deviation among all VDD1 or VDD2 supplies may never exceed 0.3 V. Stresses beyong those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 222 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 4.5.2. Recommended Operating Conditions In the operating conditions, the functions given in the circuit description are fulfilled. Symbol TA Parameter Ambient Operating temperature1) Pin Name - Min. 0 Typ. +25 Max. +70 Unit C 3.3 V Power Supply VDDxx Supply voltages2) VDDP1, VDDP2, VDDP3, VDDACY, VDDACU, VDDACV, VDD33C, VDD33RGB 3.14 3.3 3.47 V 1.8 V Power Supply VDDxx Supply voltages2) VDDAC1, VDDAC2, VDDARGB, VDDAFBL, VDDAPLL; VDDD1; VDDD2;VDDD3; VDDD4 1.71 1.8 1.89 V CVBS/RGB Frontend Vi,CVBS Vi,RGB Vi,FBL Analog CVBS input voltage Analog RGB input voltage Analog FBL input voltage Analog chroma input voltage (burst) Input coupling capacitors CVBS Input coupling capacitors RGB/FBL Source resistance Reset Input Rise time tRES tRES Active time reset (after power-on) Active time reset (during normal operation, if required) RESET 0 1.3 100 - - tbd - - s s ns CVBS1, CVBS2, CVBS3, CVBS4, CVBS5, CVBS6, CVBS7, CVBS8, CVBS9, RIN1, RIN2, GIN1, GIN2, BIN1, BIN2, FBL1, FBL2 0.6 0.5 0.5 - - - - 1.2 1.2 1.2 0.3 100 47 0.1 1.8 1.5 1.5 - - - - V V V V nF nF k Digital To Analog Converters RL CL Load resistance Load capacitance AYOUT, AUOUT, AVOUT 10 - - - - 15 k pF Micronas Nov. 28, 2002; 6251-576-3PD 223 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Crystal Specification fxtal fmax/fxtal f/fxtal CL RS C1 C0 CL,EXT Frequency (fundamental)3) Maximum permissible frequency deviation4) Recommended permissible frequency deviation4) Load capacitance Series resistance Motional capacitance Parallel capacitance External load capacitance to ground XIN, XOUT 20.248 -100 -40 - - 20 - - 20.25 - 0 13 tbd - 7 13 20.252 100 40 - 25 30 - - MHz ppm ppm pF fF pF pF All Digital Inputs Vin,L Vin,H Input voltage low Input voltage high TMS, ADR/TDI, V, TCLK, RESET, 656VIN/BLANK, 656HIN, 656IO[0...7], 656CLK I656I[0...7], I656ICLK - 2.0 - - 0.8 - V V 1) Favourable PCB design required. Two layer boards recommended. 2) 5% 3) Values outside this range may cause color decoding failures. 4) after (subcarrier) adjustment // including temperature and aging deviations 224 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 4.5.3. Characteristics Min./Max. values at TA= 0 to 70 C, fCLOCK = 20.25 MHz, VSUP3,3 V = 3.14 to 3.47 V, VSUP1.8 V = 1.71 to 1.89 V Typical values at TA= 25 C, fCLOCK = 20.25 MHz, VSUP3.3 V = 3.3 V, VSUP1.8 V = 1.1.8 V 4.5.3.1. General Characteristics Symbol Parameter Pin Name Min. Typ. 65 0.85 0.45 Max. 470 90 1.2 tbd Unit mA mA W W STANDBYxx='1' Test Conditions IDDtot 1.8 V Average total supply current IDDtot 3.3 V Average total supply current Ptot PtotPD Total power dissipation Total power dissipation in power-save-mode Digital Inputs CI Input capacitance Input leakage current TMS, ADR/ TDI, V, TCLK, RESET, 656VIN/ BLANK, 656HIN/, 656IO[0...7], 656CLK, 656I[0...7], I656ICLK 656IO[0...7], I656I[0...7] 656CLK, I656ICLK -1 7 1 pF A Incl. leakage current of SDA output stage Except for current of below specified pullup or pulldown pins. tSI tHI fclkin tWL tWH tLH tHL set-up-time hold-time input clock frequency Low time High time Rise time Fall time 2.5 2.5 27 10 10 1.6 1.6 30 ns ns MHz ns ns ns ns wrt. 656clk (rising) wrt. 656clk (rising) Digital Outputs VOH VOL Output voltage high Output voltage low 2.4 CLKOUT, HOUT, VOUT, 656CLK, H50, DBOUT[0..8], DROUT[0..8], DGOUT[0..8], VIN/INT, V50 Vdd2 0.4 V V @-12mA @8mA Micronas Nov. 28, 2002; 6251-576-3PD 225 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET Symbol tLH Parameter Rise time Pin Name CLKOUT, 656CLK Min. - Typ. - Max. 1.6 2.5 Unit ns ns Test Conditions @20pF @20pF DBOUT[0..8], DROUT[0..8], DGOUT[0..8], HOUT, VOUT, H50, V50, VIN/INT tHL Fall time CLKOUT, 656CLK DBOUT[0..8], DROUT[0..8], DGOUT[0..8] HOUT, VOUT, H50, V50, VIN/INT fclkout Output frequency CLKOUT 656CLK Duty cycle tHO Hold-time CLKOUT 656CLK 656IO[0...7], 656VIO, 656HIO - - 6 1.6 2.5 ns ns ns @20pF @20pF @20pF 10.12 5 27 40 3 50 4 81 60 60 ns MHz MHz % ns @20pF Referred to 656CLK, CLK656INV=1 Referred to 656CLK, CLK656INV=0 Referred to CLKOUT, CLKOUTINV=1 Referred to CLKOUT, CLKOUTINV=0 Referred to 656CLK, CLK656INV=1 Referred to 656CLK, CLK656INV=0 Referred to CLKOUT, CLKOUTINV=1 Referred to CLKOUT, CLKOUTINV=0 Pulldown always active Pulldown always active 3+ Tclk/2 DBOUT[0..8], 3 DROUT[0..8], DGOUT[0..8], HOUT, VOUT 3+ Tclk/2 tDO Delay-Time 656IO[0...7], 656VIO, 656HIO 0 3+ Tclk/2 3 0 3+ Tclk/2 3 -59.5 -11.7 -122 -25.8 -235 -55.5 ns ns ns ns ns ns ns A A DBOUT[0..8], DROUT[0..8], DGOUT[0..8] HOUT, VOUT IPD Pulldown-current (@Vdd) I656ICLK, 656CLK 656VIO/ BLANK, VIN/ INT, ADR/ TDI, TCLK, 656HIO 226 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Symbol IPU Parameter Pullup-current (@Vss) Pin Name TMS, SISCEN Min. 12.4 Typ. 21.4 Max. 36.4 Unit A Test Conditions Pullup always active Analog CVBS Front-end (2 x 9 bit ADC) Input leakage current CI Input capacitance Input clamping error CT BW Acvbso Crosstalk between CVBS inputs Bandwidth CVBS output amplification CVBS1, CVBS2, CVBS3, CVBS4, CVBS5, CVBS6, CVBS7, CVBS8, CVBS9 CVBSO1, CVBSO2, CVBSO3 -100 -1 -50 7 0.9 7 100 1 1.1 nA pF LSB dB MHz Settled state fsig<5 MHz -3 dB Clamping inactive Analog RGBF Front-end (4 x 8 bit ADC) Input leakage current CI CVBS input capacitance Input clamping error CT BW Crosstalk between RGB inputs Bandwidth RIN1, RIN2, BIN1, BIN2, GIN1, GIN2, FBL1, FBL2 -100 -1 -50 10 7 100 1 nA pF LSB dB MHz -3 dB Settled state Clamping inactive Digital To Analog Converters ( 3 x 9 bit DAC) UOL UOH Full range output voltage Full range output voltage Output matching -3 0.4 1.9 3 V V % Nominal conditions PKLY/U/V=min Nominal conditions PKLY/U/V=max Color Decoder/Synchronization and Luminance Processing fHf Horizontal PLL pull-inrange ACC range AGC range fSC Chroma PLL pull-in-range - - - - -30 -7.5 4.9 500 +6 +2 % dB dB Hz Nominal crystal frequency Based on 15625 kHz The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Micronas Nov. 28, 2002; 6251-576-3PD 227 VSP 94x5B, VSP 94x7B 4.5.3.2. IC Bus Characteristics Symbol Parameter Pin Name Min. Typ. Max. PRELIMINARY DATA SHEET Unit Test Conditions Fast I2C Bus (All Values are Referred to Min(VIH) and Max(VIL)) Cb tR, tF tBUF fSCL tLOW tHIGH tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO Capacitive load/bus line SDA/SCL rise/fall times Inactive time before start of transmission I2C clock frequency SCL low time SCL high time Set-up time start condition Hold time start condition Set-up time DATA Hold time DATA Set-up time stop condition SDA SCL SDA/SCL 20+$ 1300 0 1300 600 600 600 100 0 600 900 400 400 300 pF ns ns kHz ns ns ns ns ns ns ns $=0.1 Cb/pF I2C Bus pins VIHr VIL Threshold rise Threshold fall SDA, SCL 2.08 1.8 V V t f t HIGH t LOW tR SCL t SU;STA SDA IN tHD;STA t SP tAA SDA OUT t AA t HD;STA t SU;DAT t SU;STO t BUF Fig. 4-20: IC bus timing data T 656clk clkout tLH 656in tSI Datain VIH VIL tWH tHI Datain tHL tWL 656out dgout drout dbout tHO Dataout Dataout tDO Fig. 4-21: Timing diagram clock 228 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B 5. Application Circuit L1 10 H +1V8 C39 10 F L2 10 H +1V8 C38 10 F C37 100nF C36 100nF C35 100nF C34 100nF C33 100nF 20.25MHz C32 100nF C31 100nF +3.3V L3 10H 34 33 28 29 5 4 66 67 42 43 68 64 65 50 51 35 36 71 19 7 74 8 C29 47nF C28 47nF C27 47nF C25 47nF C24 47nF C23 47nF C22 -- / 47 nF C21 100nF C20 100nF C19 100nF C18 100nF C17 100nF C16 100nF C15 100nF vddd4 vssd4 vddd3 vssd3 vddd2 vssd2 vddd1 vssd1 vddargb vssargb vddapll vddac2 vssac2 vddac1 vssac1 vddafbl vssafbl tclk adr/tdi tms IC1 vddp3 vssp3 vddp2 vssp2 vddp1 vssp1 vdd33c vss33c vdd33rgb vss33rgb vdddacy vssdacy vdddacu vssdacu 25 26 12 11 72 73 59 60 44 45 1 3 78 80 75 C41 100nF C40 100nF C42 100nF C44 100nF C43 100nF C48 10 F C45 100nF L4 10 H C47 100nF C46 100nF C49 10 F +3.3 V +3.3 V J1 656HIN 656ICLK 656IN7 656IN6 656IN5 656IN4 656IN3 656IN2 656IN1 656IN0 656OCLK 656OUT7 656OUT6 656OUT5 656OUT4 656OUT3 656OUT2 656OUT1 656OUT0 CLKOUT HOUT VOUT BLANK J3 656VIN J2 I2C Address B2h B0h C30 100nF VSP vdddacv 77 vssdacv 9405B vss 49 9407B 9435B 9437B 656clk 656io7 stepping R21...R27: 8x 75 RIN2 GIN2 BIN2 FBL2 RIN1 GIN1 INTR BIN1 656hin/clkf20 656vin/blank rin2 gin2 bin2 fbl2 rin1 gin1 bin1 fbl1 vin/intr cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 scl sda reset xin 70 9 10 15 16 21 22 30 31 32 27 17 23 2 79 76 61 62 63 18 20 46 47 48 38 39 40 41 37 14 58 57 56 55 54 53 52 13 6 24 656io6 656io5 656io4 656io3 656io2 656io1 656io0 clkout hout vout ayout auout avout cvbso3 cvbso2 cbbso1 h50/irq v50/blank xout 69 Cx MQFP80 J4 VIN CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 HIN1/FBL1 CVBSO3 CVBSO2 CVBSO1 H50/INT V50/BLANK R1...R7: 7x 75 Q1 20M25 C5 22pF* SCL (3.3V) *values are PCB and crystal dependent SDA (3.3V) C6 22pF* +5V R20 51 R21 51 C52 33 F Y100 C53 33 F C54 33 F U100 V100 R19 51 RESET T3 T4 T5 -- / 3*BC807 buffer not necessary when short connection to backend-processor Application Example VSPB V1.41 (Cx) 2002-11-07 Fig. 5-1: Application Example for 940xB and 943xB Micronas Nov. 28, 2002; 6251-576-3PD 229 VSP 94x5B, VSP 94x7B PRELIMINARY DATA SHEET L1 10 H +1V8 C39 10 F L2 10 H +1V8 C38 10 F C37 100nF C36 100nF C35 100nF C34 100nF C33 100nF 20.25MHz C32 100nF C31 100nF +3.3V 34 33 28 29 5 4 66 67 42 43 68 64 65 50 51 35 36 71 19 7 74 8 C29 47nF C28 47nF C27 47nF C25 47nF C24 47nF C23 47nF C22 -- / 47 nF C21 100nF C20 100nF C19 100nF C18 100nF C17 100nF C16 100nF C15 100nF vddd4 vssd4 vddd3 vssd3 vddd2 vssd2 vddd1 vssd1 vddargb vssargb vddapll vddac2 vssac2 vddac1 vssac1 vddafbl vssafbl tclk adr/tdi tms IC1 vddp3 vssp3 vddp2 vssp2 vddp1 vssp1 vdd33c vss33c vdd33rgb vss33rgb vss i656iclk i656i7 i656i6 i656i5 i656i4 i656i3 i656i2 i656i1 i656i0 656clk stepping 25 26 12 11 72 73 59 60 44 45 49 75 3 2 1 80 79 78 77 76 9 10 15 16 21 22 30 31 32 27 17 23 61 62 63 18 20 C44 100nF C43 100nF C45 100nF C47 100nF C46 100nF L3 10 H +3.3 V C49 10 F L4 10 H +3.3 V C48 10 F J1 656HIN 656ICLK 656IN7 656IN6 656IN5 656IN4 656IN3 656IN2 656IN1 656IN0 656OCLK 656OUT7 656OUT6 656OUT5 656OUT4 656OUT3 656OUT2 656OUT1 656OUT0 CLKOUT HOUT VOUT CVBSO3 CVBSO2 CVBSO1 H50/INT V50/BLANK BLANK J3 656VIN J2 I2C Address B2h B0h C30 100nF VSP 9415B 9417B 9445B 9447B R21...R27: 8x 75 RIN2 GIN2 BIN2 FBL2 RIN1 GIN1 INTR BIN1 656hin/clkf20 656vin/blank rin2 gin2 bin2 fbl2 rin1 gin1 bin1 fbl1 vin/intr cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 scl sda reset xin 70 46 47 48 38 39 40 41 37 14 58 57 56 55 54 53 52 13 6 24 656io7 656io6 656io5 656io4 656io3 656io2 656io1 656io0 clkout hout vout cvbso3 cvbso2 cbbso1 h50/irq v50/blank xout 69 Cx MQFP80 J4 VIN CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 HIN1/FBL1 R1...R7: 7x 75 Q1 20M25 C5 22pF* SCL (3.3V) *values are PCB and crystal dependent SDA (3.3V) C6 22pF* RESET Application Example VSPB V1.51 (Cx) 2002-11-07 Fig. 5-2: Application Example for 941xB and 944xB 230 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B L1 10 H +1V8 C34 10 F L2 10 H +1V8 C33 10 F C32 100nF C31 100nF C30 100nF C29 100nF C28 100nF C27 100nF 90 89 64 63 58 59 5 vddd5 vssd5 vddd4 vssd4 vddd3 vssd3 vddd2 vsspdb1 vddp8 vssp8 vddp7 vssp7 vddp6 36 135 134 121 120 87 C52 100nF C51 100nF C50 100nF C49 100nF C48 100nF C47 100nF C46 100nF C45 100nF C43 100nF C42 100nF C41 100nF C40 100nF C39 100nF C54 100nF C53 100nF L3 10 H +3.3 V C55 10 F C26 100nF C25 100nF 20.25MHz J1 656HIN C24 100nF BLANK J3 656VIN GP2 GP1 GP0 656clk 656in7 656in6 656in5 656in4 656in3 656in2 656in1 656in0 +3.3V J2 B2h I2C Address B0h 656clk 656in7 656in6 656in5 656in4 656in3 656in2 656in1 656in0 RIN2 GIN2 BIN2 FBL2 RIN1 GIN1 INTR BIN1 C23 47nF C22 47nF C21 47nF C20 47nF C18 47nF C18 47nF R20 10k J4 VIN CVBS9 CVBS8 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 HIN1/FBL1 C16 100nF C15 100nF C14 100nF C13 100nF C12 100nF C11 100nF C10 100nF C9 100nF C8 100nF 88 vssp6 55 4 vssd2 vddp5 117 56 vddd1 vssp5 118 11 vssd1 vddp4 12 74 vddargb vssp4 75 49 vssargb vddp3 119 50 vddapll vssp3 112 41 vddac2 vddp3 113 42 vssac2 vssp3 92 27 vddac1 vddp2 IC1 93 26 vssp2 vssac1 20 65 vddafbl VSP9425B vddp2 66 19 vssafbl VSP9427B vssp2 130 86 vddpor vddp1 MQFP144 137 131 vssp1 reseved 136 107 reseved stepping vdd33c 108 Cx 133 vss33c reseved 85 76 vdd33rgb reseved 77 84 vss33rgb reseved 83 1 vdddacy reseved 3 57 reseved vssdacy 142 17 vdddacu reseved 105 144 vssdacu nc 139 103 vdddacv nc 141 101 vssdacv nc 99 43 nc drout8 44 81 drout7 nc 79 45 nc drout6 46 71 nc drout5 69 47 nc drout4 129 48 drout3 tclk 34 52 drout2 adr/tdi 13 53 drout1 tms 138 54 656hio/clkf20 drout0 114 14 dbout8 656vio/blank 115 15 dbout7 656clk 116 16 dbout6 656io7 124 30 656io6 dbout5 125 31 656io5 dbout4 126 37 656io4 dbout3 127 38 656io3 dbout2 128 60 656io2 dbout1 132 61 656io1 dbout0 62 6 dgout8 656io0 7 78 dgout7 rin2 80 8 dgout6 gin2 82 9 dgout5 bin2 68 21 dgout4 fbl2 22 70 dgout3 rin1 23 72 dgout2 gin1 24 73 dgout1 bin1 67 25 dgout0 fbl1 29 51 clkout vin/intr 95 32 cvbs9 hout 94 39 vout cvbs8 106 2 ayout cvbs7 143 104 auout cvbs6 140 102 cvbs5 avout 109 100 cvbso3 cvbs4 110 98 cvbso2 cvbs3 111 97 cbbso1 cvbs2 96 33 h50/irq cvbs1 35 28 scl v50/blank 18 10 sda tdo 91 40 reset siscen xin xout 123 122 Q1 20M25 C5 22pF* C6 22pF* L4 10 H +3.3 V C44 10 F DROUT8 DROUT7 DROUT6 DROUT5 DROUT4 DROUT3 DROUT2 DROUT1 DROUT0 DBOUT8 DBOUT7 DBOUT6 DBOUT5 DBOUT4 DBOUT3 DBOUT2 DBOUT1 DBOUT0 656OUT7 656OUT6 656OUT5 656OUT4 656OUT3 656OUT2 656OUT1 656OUT0 DGOUT8 DGOUT7 DGOUT6 DGOUT5 DGOUT4 DGOUT3 DGOUT2 DGOUT1 DGOUT0 CLKOUT HOUT VOUT CVBSO3 CVBSO2 CVBSO1 H50/IRQ V50/BLANK +5V R20 51 R21 51 C52 33 F C53 33 F C54 33 F Y100 U100 V100 SCL (3.3V) R19 51 SDA (3.3V) *values are PCB and crystal dependent RESET +3.3V J5 single-scan double-scan T3 T4 T5 -- / 3*BC807 buffer not necessary when short connection to backend-processor Application Example VSP94x7B V1.51 2002-11-07 Micronas Fig. 5-3: Application Example for 9425B and 9427B Micronas Nov. 28, 2002; 6251-576-3PD 231 VSP 94x5B, VSP 94x7B 5.1. Application Overview RGB H, V PRELIMINARY DATA SHEET RGB DVD YUV Camcorder YC CVBS VSP 9405B VSP 9407B VSP 9435B VSP 9437B VSP 9425B VSP 9427B OPTIMUS BLANK VCR Tuner IF Tuner IF CVBS CLK analog YUV H, V RGB SDA 9380 EDDC CVBS HD, VD, EW CVBS, YC ITU656 CVBS still-picture storage HW SDA 6000 M2 SDA 5550 TvTpro RGB, FBL, COR Fig. 5-4: Application overview with analog outputs of VSP 940xB RGB H, V RGB DVD YUV Camcorder YC CVBS VSP 9415B VSP 9445B VSP 9417B VSP 9447B VSP9425B VSP9427B OPTIMUS VCR Tuner IF Tuner IF CVBS CVBS CVBS, YC ITU656 CLK digital YUV RGB DDP 3315C H, V HD, VD, EW CVBS still-picture storage HW SDA 6000 M2 SDA 5550 TvTpro RGB, FBL, COR Fig. 5-5: Application overview with digital outputs of VSP 941xB, (VSP 942xB) 232 Nov. 28, 2002; 6251-576-3PD Micronas PRELIMINARY DATA SHEET VSP 94x5B, VSP 94x7B Micronas Nov. 28, 2002; 6251-576-3PD 233 VSP 94x5B, VSP 94x7B 6. Data Sheet History 1. Preliminary Data Sheet: "VSP 94x5B, VSP 94x7B OPTIMUS ", Jan. 18, 2002, 6251-576-1PD . First release of the preliminary data sheet. 2. Preliminary Data Sheet: "VSP 94x5B, VSP 94x7B OPTIMUS", Oct. 21, 2002, 6251-576-2PD. Second release of the preliminary data sheet. Major changes: New revision, complete updated. 3. Preliminary Data Sheet: "VSP 94x5B, VSP 94x7B OPTIMUS", Nov. 28, 2002, 6251-576-3PD. Third release of the preliminary data sheet. Major changes: - Following sections were revised and updated: 2.3.15. Digital Prefiltering 2.3.19. Fast Blank Activity and Overflow Detection 2.7. Clock Concept 3.7. IC Bus Registers 3.12. IC Bus Command Table PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-576-3PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 234 Nov. 28, 2002; 6251-576-3PD Micronas |
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