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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
July 1998
NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
General Description
The NM27LV210 is a high performance Low Voltage Electrical Programmable read only memory. It is manufactured using Fairchild's latest EPROM technology. This technology allows the part to operate at high speeds. This Low Voltage and Low Power EPROM is designed with power sensitive hand held and portable battery products in mind. This allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and HDD. The NM27LV210 is one member of Fairchild's growing Low Voltage product family.
Features
s 3.0V to 3.6V operation s 200 ns, 250 ns maximum access time s Low current operation -- 20mA ICC active current @ 5 MHz -- 50A ICC standby current @ 5 MHz s Ultra low power operation -- 60 A standby power @ 3.3V -- 50 mW active power @ 3.3V s Surface mount package option -- 44-Pin PLCC
Block Diagram
Vcc GND Vpp OE PGM CE Output Enable Chip Enable, and Program Logic Data Outputs O0 - O15
Output Buffers
Y Decoder A0 - A15 Address Inputs 1,048,576-Bit Cell Matrix X Decoder
DS011376-1
(c) 1998 Fairchild Semiconductor Corporation
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Connection Diagrams
PLCC Pin Configuration
CE XX/VPP NC VCC XX/PGM NC A15 A14
7 O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4 17
65432 8 9 10 11 12 13 14 15 16 1
44 43 42 41 40 38 37 36 35 34 33 32 31 30
39 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 29 O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4
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CE XX/VPP NC VCC XX/PGM NC A15 A14 33 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 23 32 31 30 29 28 27 26 25 24
O13 O14 O15
44 43 42 41 40 39 38 37 36 35 34 2 3 4 5 6 7 8 9 10
18 19 20 21 22 23 24 25 26 27 28
O3 O2 O1 O0 OE NC A0 A1 A2 A3 A4
12 13 14 15 16 17 18 19 20 21 22 11 O3 O2 O1 O0 OE NC A0 A1 A2 A3 A4
Top View
DS011376-3
O13 O14 O15
DS011376-7
Commercial Temperature Range
(0C to +70C) VCC = 3.3V 0.3 Parameter/Order Number
NM27LV210 V 200 NM27LV210 V 250
Extended Temperature Range
(-40C to +85C) VCC = 3.3V 0.3 Parameter/Order Number
NM27LV210 VE 250 * All packages conform to JEDEC standard. * All versions are guaranteed to function in slower applications.
Access Time (ns)
200 250
Access Time (ns)
250
Pin Names
A0-A15 CE OE O0-O15 PGM XX NC VPP Addresses Chip Enable Output Enable Outputs Program Don't Care (During Read) No Connect Programming Voltage
* Consult the FSC representative for newly released products/ packages.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Absolute Maximum Ratings (Note 2)
Storage Temperature All Input Voltages except A9 with Respect to Ground (Note 12) VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground ESD Protection -65C to +150C
All Output Voltages with Respect to Ground (Note 11)
VCC + 1.0V to GND - 0.6V
Operating Range
-0.6V to +7V -0.6V to +14V -0.6V to +7V >2000V
Range
Commercial Extended
Temperature
0C to +70C -40C to +85C
VCC
3.3 3.3
Tolerance
0.3 0.3
DC Read Characteristics Over Operating Range with VPP = VCC
Symbol
VIL VIH VOL1 VOH1 VOL2 VOH2 ISB1 ISB2 ICC IPP ILI ILO
Parameter
Input Low Level Input High Level Output Low Voltage (TTL) Output High Voltage (TTL) Output Low Voltage (CMOS) Output High Voltage (CMOS) VCC Standby Current (TTL) VCC Standby Current (CMOS) VCC Active Current VPP Supply Current Input Load Current Output Leakage Current
Test Conditions
Min
-0.3 2.0
Max
0.7 VCC + 0.3 0.4
Units
V V V V
2.4 0.2 VCC - 0.3 CE = VIH CE = VCC 0.3V CE = OE = VIL, I/O = 0 A VPP = VCC VIN = 3.3 or GND VOUT = 3.3V or GND -1 -1 f = 5 MHz 150 50 20 10 1 10
V V A A mA A A A
AC Read Characteristics Over Operating Range with VPP = VCC
Symbol
tACC tCE tOE tDF (Note 3) tOH (Note 3)
Parameter Min
Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Output Hold from Addresses, CE or OE , Whichever Occurred First 0
200 Max
200 200 70 50 0
250 Min Max
250 250 75 60
Units
ns
0
0
Capacitance (Note 3) TA = +25C, f = 1 MHz
Symbol
CIN COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VIN = 0V VOUT = 0V
Typ
12 13
Max
20 20
Units
pF pF
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 9) 5 ns 0.45V to 2.4V 0.8V and 2V 0.8V and 2V Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level Inputs Outputs
AC Waveforms (Note 7) (Note 8) (Note 10)
ADDRESS 2.0V 0.8V 2.0V 0.8V Address Valid
CE
OE
2.0V 0.8V
OUTPUT
2.0V 0.8V
Hi-Z
t ACC
(Note 3)
Note 2: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 3: This parameter is only sampled and is not 100% tested. Note 5: The tDF and tCF compare level is determined as follows: High to TRI-STATETM, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 6: TRI-STATE may be attained using OE or CE. Note 7: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. Note 8: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 9: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL: 100 pF includes fixture capacitance. Note 10: VPP may be connected to VCC except during programming. Note 11: Inputs and outputs can undershoot to -2.0V for 20 ns Max. Note 4: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
, ,,
t CE t CF (Note 4, 5) t DF t OE (Note 4, 5) (Note 3) Valid Output Hi-Z t DH
DS011376-4
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol
tAS tOES tCES tDS tVPS tVCS tAH tDH tDF
Parameter
Address Setup Time OE Setup Time CE Setup Time Data Setup Time VPP Setup Time VCC Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay
Conditions
Min
1 1
Typ
Max
Units
s s s s s s s s
OE = VIH
1 1 1 1 0 1
CE = VIL
0
60
ns
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15) (Continued)
Symbol
tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT
Parameter
Program Pulse Width Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
CE = VIL CE = VIL PGM = VIL
Min
45
Typ
50
Max
105 100 40 50
Units
s ns mA mA C V V ns
20 6.25 12.5 5
25 6.5 12.75
30 6.75 13.0
0.0 2.4 0.8 0.8 4.0
0.45
V V
2.0 2.0
V V
Programming Waveforms (Note 14)
Program Addresses 2.0V 0.8V t AS 2.0V Data 0.8V t DS 6.25V VCC t VCS Data In Stable ADD N t DH Hi-Z Data Out Valid ADD N t DF Address N Program Verify
VPP
12.75V
t VPS
CE
0.8V t CES
PGM
2.0V 0.8V t PW t OES t OE
OE
2.0V 0.8V
DS011376-5
Note 12: Fairchild's standard product warranty applies only to devices programmed to specifications described herein. Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 15: During power up the PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Turbo LV Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION
PROGRAM ONE 50s PULSE INCREMENT n
NO
DEVICE FAILED
YES
n = 10?
FAIL
VERIFY BYTE
PASS
LAST ADDRESS ?
YES
NO
INCREMENT ADDRESS n=0
ADDRESS = FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
NO PASS
FAIL
PROGRAM ONE 50 s PULSE
LAST ADDRESS ?
YES
CHECK ALL BYTES 1ST: VCC = VPP = 5.0V 2ND: VCC = VPP = 3.0V
DS011376-6 Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time.
FIGURE 1.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in . It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 3.3V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 3.3V in the other three modes.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the "1's" state. Data is introduced by selectively programming "0's" into the desired bit locations. Although only "0's" will be programmed, both "1's" and "0's" can be presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure. The EPROM is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 F capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 s pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 s pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM.
Read Mode
The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC - tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 66 mW to 66 W. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Tying
Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Functional Description (Continued)
MODE SELECTION
The modes of operation of the NM27LV210 are listed in Table 1. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.
TABLE 1. Modes Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note 16: X can be VIL or VIH.
CE
VIL X VIH VIL VIL VIH
OE
VIL VIH X VIH VIL X
PGM
X (Note 16) X X VIL VIH X
VPP
X X X 12.75V 12.75V 12.75V
VCC
3.3V 3.3V 3.3V 6.25V 6.25V 6.25V
Outputs
DOUT High Z High Z DIN DOUT High Z
Program Inhibit
Programming multiple EPROM's in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel EPROM may be common. A TTL low level program pulse applied to an EPROM's PGM input with CE at VIL and VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROM's from being programmed.
The code is accessed by applying 12V 0.5V to address pin A9 . Addresses A1 -A8 ,A10 -A15 , and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer's code, and held at VIH for the device code. The code is read on the lower eight data pins, O0 -07 . Proper code access is only guaranteed at 25C 5C.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 6.25V. VPP must be at VCC, except during programming and program verify.
MANUFACTURER'S IDENTIFICATION CODE
The EPROM has a manufacturer's identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer's Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the NM27LV210 is "8FD6", where "8F" designates that it is made by Fairchild Semiconductor, and "D6" designates a 1 Megabit (64K x 16) part.
TABLE 2. Manufacturer's Identification Code Pins
Manufacturer Code Device Code
A0 (21)
VIL VIH
A9 (31)
12V 12V
O7 (12)
1 1
O6 (13)
0 1
O5 (14)
0 0
O4 (15)
0 1
O3 (16)
1 0
O2 (17)
1 1
O1 (18)
1 1
O0 (19)
1 0
Hex Data
8F D6
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
+0.006 0.650 -0.000 +0.15 16.51 0 PIN 1 IDENT 6 1 44 40 45X 0.045 [1.14] 0.017 0.021 TYP [0.43 0.10] 0.045 45X [1.14]
17
39
0.026-0.032 [0.66-0.81] TYP
0.610 0.020 [15.49 0.51] TYP Seating plane
17 18 0.500 TYP [12.70]
29 28 0.050 TYP [1.27]
0.020 MIN TYP [0.51] 0.105 0.015 TYP [2.67 0.38] 0.165-0.180 TYP [4.19-4.57] 0.004 [0.10]
0.690 0.005 TYP [17.53 -0.13]
44-Lead Plastic Chip Carrier (V) Order Number NM27LV210XXX Package Number V44A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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