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FEATURES Micropower: 100 A/DAC 0.1 A Typical Power Shutdown Single Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP 24-Lead Package AD7396: 12-Bit Resolution AD7397: 10-Bit Resolution 0.9 LSB Differential Nonlinearity Error APPLICATIONS Automotive Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals
LDA CS A/B DATA 12
3 V, Parallel Input Dual 12-Bit /10-Bit DACs AD7396/AD7397
FUNCTIONAL BLOCK DIAGRAM
AD7396
DACA REGISTER VDD 12 12-BIT DACA VOUTA
INPUTA REGISTER 1 INPUTB REGISTER 12 VREF
LDB
DACB REGISTER
12-BIT DACB
VOUTB AGND
DGND
RS
SHDN
GENERAL DESCRIPTION
The AD7396/AD7397 series of dual, 12-bit and 10-bit voltageoutput digital-to-analog converters are designed to operate from a single +3 V supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost and ease of use in single supply +3 V systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, making this device ideal for battery operated applications. A 12-bit wide data latch loads with a 45 ns write time allowing interface to fast processors without wait states. The double buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both LDA+LDB inputs will simultaneously update both DAC outputs. LDA and LDB can also be independently activated to immediately update their respective DAC registers. An address input (A/B) decodes DACA or DACB when the chip select CS input is strobed. Additionally, an asynchronous RS input sets the output to zero-scale at power on or upon user demand. Power shutdown to submicroamp levels is directly controlled by the active low SHDN pin. While in the power shutdown state register data can still be changed even though the output buffer is in an open circuit state. Upon return to the normal operating state the latest data loaded in the DAC register will establish the output voltage.
Both parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their applications without circuit card changes. The AD7396/AD7397 are specified for operation over the extended industrial (-40C to +85C) temperature range. The AD7397AR is specified for the -40C to +125C automotive temperature range. AD7396/AD7397s are available in plastic DIP, and 24-lead SOIC packages. The AD7397ARU is available for ultracompact applications in a thin 1.1 mm height TSSOP 24-lead package.
1.0 0.8 0.6 0.4 VDD = +3V VREF = +2.5V
DNL - LSB
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 CODE - Decimal 3072 3584 4096 TA = +25 C, +85 C, -55 C SUPERIMPOSED
Figure 1. DNL vs. Digital Code at Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD7396/AD7397-SPECIFICATIONS
AD7396 12-BIT ELECTRICAL CHARACTERISTICS (@ V
Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Relative Accuracy2 Differential Nonlinearity2 Differential Nonlinearity2 Zero-Scale Error Zero-Scale Error Full-Scale Voltage Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREF Range Input Resistance Input Capacitance3 ANALOG OUTPUT Output Current (Source) Output Current (Sink) Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 5 Chip Select Write Width DAC Select Setup DAC Select Hold Data Setup Data Hold Load Setup Load Hold Load Pulsewidth Reset Pulsewidth AC CHARACTERISTICS Output Slew Rate Settling Time6 Shutdown Recovery Time DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Shutdown Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL INL DNL DNL VZSE VZSE VFSE VFSE TCVFS VREF RREF CREF IOUT IOUT CL VIL VIH IIL CIL tCS tAS tAH tDS tDH tLS tLH tLDW tRSW SR tS tSDR Q Q VOUT/VREF Data = 000H to FFFH to 000H To 0.1% of Full Scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC +1 V p-p, Data = 000H, f = 100 kHz DNL < 1 LSB VIL = 0 V, No Load SHDN = 0, VIL = 0 V, No Load VIL = 0 V, No Load VDD = 5% Data = 800H, VOUT = 5 LSB Data = 800H, VOUT = 5 LSB No Oscillation
REF IN
= +2.5 V, -40 C < TA < +85 C, unless otherwise noted)
+3 V 12 1.75 2.0 0.9 1 4.0 8.0 8 20 -45 0/VDD 2.5 5 1 3 100 0.5 VDD - 0.6 10 10 45 30 0 30 20 20 10 30 40 0.05 70 90 65 15 -63 2.7/5.5 125/200 0.1/1.5 600 0.006 10% +5 V 12 1.75 2.0 0.9 1 4.0 8.0 8 20 -45 0/VDD 2.5 5 1 3 100 0.8 4.0 10 10 35 15 0 15 10 20 10 30 30 0.05 60 80 65 15 -63 2.7/5.5 125/200 0.1/1.5 1000 0.006 10% Units Bits LSB max LSB max LSB max LSB max mV max mV max mV max mV max ppm/C typ V min/max M typ4 pF typ mA typ mA typ pF typ V max V min A max pF max ns min ns min ns min ns min ns min ns min ns min ns min ns min V/s typ s typ s typ nV/s typ nV/s typ dB typ V min/max A typ/max A typ/max W max %/% max
Conditions
TA = +25C TA = -40C, +85C TA = +25C, Monotonic Monotonic Data = 000H, TA = +25C, +85C Data = 000H, TA = -40C TA = +25C, +85C, Data = FFFH TA = -40C, Data = FFFH
VDD RANGE IDD IDD_SD PDISS PSS
NOTES 1 One LSB = VREF/4096 V for the 12-bit AD7396. 2 The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25C. 5 All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice.
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AD7396/AD7397 AD7397 10-BIT ELECTRICAL CHARACTERISTICS (@ V
Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Relative Accuracy2 Differential Nonlinearity2 Zero-Scale Error Full-Scale Voltage Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREF Range Input Resistance Input Capacitance3 ANALOG OUTPUT Output Current (Source) Output Current (Sink) Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 5 Chip Select Write Width DAC Select Setup DAC Select Hold Data Setup Data Hold Load Setup Load Hold Load Pulsewidth Reset Pulsewidth AC CHARACTERISTICS Output Slew Rate Settling Time6 Shutdown Recovery Time DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Shutdown Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL INL DNL VZSE VFSE VFSE TCVFS VREF RREF CREF IOUT IOUT CL VIL VIH IIL CIL tCS tAS tAH tDS tDH tLS tLH tLDW tRSW SR tS tSDR Q Q VOUT/VREF Data = 000H to 3FFH to 000H To 0.1% of Full Scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC +1 V p-p, Data = 000H, f = 100 kHz DNL < 1 LSB VIL = 0 V, No Load SHDN = 0, VIL = 0 V, No Load VIL = 0 V, No Load VDD = 5% Data = 200H, VOUT = 5 LSB Data = 200H, VOUT = 5 LSB No Oscillation
REF IN
= +2.5 V, -40 C < TA < +85 C, unless otherwise noted)
+3 V 10 1.75 2.0 1 9.0 42 48 -45 0/VDD 2.5 5 1 3 100 0.5 VDD - 0.6 10 10 45 30 0 30 20 20 10 30 40 0.05 70 90 65 15 -63 2.7/5.5 125/200 0.1/1.5 600 0.006 10% +5 V 10 1.75 2.0 1 9.0 42 48 -45 0/VDD 2.5 5 1 3 100 0.8 4.0 10 10 35 15 0 15 10 20 10 30 30 0.05 60 80 65 15 -63 2.7/5.5 125/200 0.1/1.5 1000 0.006 10% Units Bits LSB max LSB max LSB max mV max mV max mV max ppm/C typ V min/max M typ4 pF typ mA typ mA typ pF typ V max V min A max pF max ns min ns min ns min ns min ns min ns min ns min ns min ns min V/s typ s typ s typ nV/s typ nV/s typ dB typ V min/max A typ/max A typ/max W max %/% max
Conditions
TA = +25C TA = -40C, +85C, +125C Monotonic Data = 000H TA = +25C, +85C, +125C, Data = 3FFH TA = -40C, Data = 3FFH
VDD RANGE IDD IDD_SD PDISS PSS
NOTES 1 One LSB = V REF/4096 V for the 10-bit AD7397. 2 The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25C. 5 All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V. 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice.
REV. 0
-3-
AD7396/AD7397
tCSW
CS
tAS tAH
A/B
B REGISTER
tDS tDH
D0-D11
1 OF 12 LATCHES OF THE 2 INPUT REGISTERS
tLS
LDA, LDB
DBx
tLH tRSW
tLDW
CS A/B RS
TO DAC REGISTERS
RS
tS
VOUT
tS
1 LSB ERROR BAND
Figure 2. Timing Diagram
Figure 3. Digital Control Logic
Table I. Control Logic Truth
CS L L L L H H X H
A/B L H L H X X X X
LDA H H H L L ^ X X
LDB H H L H L ^ X X
RS H H H H H H L ^
SHDN X X X X X X X X
Input Register Write to B Write to A Write to B Write to A Latched Latched Reset to Zero Scale Latched to Zero
DAC Register Latched with Previous Data Latched with Previous Data B Transparent A Transparent A and B Transparent Latched with New Data from Input REG Reset to Zero Scale Latched to Zero
^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V OUTA and VOUTB exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = "0."
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REV. 0
AD7396/AD7397
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . -0.3 V, +8 V VOUT to GND . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +2 V IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . +50 mA Package Power Dissipation . . . . . . . . . . . . . (TJ max - TA)/JA Thermal Resistance JA 24-Lead Plastic DIP Package (N-24) . . . . . . . . . . +63C/W 24-Lead SOIC Package (R-24) . . . . . . . . . . . . . . . +70C/W 24-Lead Thin Shrink Surface Mount (RU-24) . . +143C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C AD7397AN, AD7397AR Only . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature N-24 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . +300C R-24 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . . +215C RU-24 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . . +224C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7396AN AD7396AR AD7397AN AD7397AR AD7397ARU
Res (LSB) 12 12 10 10 10
Temperature Ranges -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +85C
Package Descriptions 24-Lead P-DIP 24-Lead SOIC 24-Lead P-DIP 24-Lead SOIC 24-Lead Thin Shrink Small Outline Package (TSSOP)
Package Options N-24 R-24 N-24 R-24 RU-24
The AD7396/AD7397 contains 1365 transistors. The die size measures 89 mil x 106 mil = 9434 sq mil.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7396/AD7397 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-5-
AD7396/AD7397
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4
Name VOUTA AGND DGND LDA DAC A Voltage Output. Analog Ground. Digital Ground. Load DAC A Register Strobe. Transfers input register data to the DAC A register. Active low inputs, Level sensitive latch. May be connected together with LDB to double-buffer load both DAC registers simultaneously. Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin. Resets Input and DAC Register to Zero Condition. Asynchronous active low input. Twelve Parallel Input Data Bits. D11 = MSB Pin 18, D0 = LSB Pin 7, AD7396. No Connect Pins 7 and 8 On the AD7397 Only. Ten Parallel Input Data Bits. D9 = MSB Pin 18, D0 = LSB Pin 9, AD7397 Only. Chip Select Latch Enable, Active Low. DAC Input Register Address Select DACA = 1 or DACB = 0. Load DAC B Register Strobe. Transfers input register data to the DAC B register. Active low inputs, Level sensitive latch. May be connected together with LDA to double-buffer load both DAC registers simultaneously. Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V. DAC Reference Input Pin. Establishes DAC full-scale voltage. DAC B Voltage Output.
5 6 7-18 7, 8 9-18 19 20 21
SHDN RS D0-D11 NC D0-D9 CS A/B LDB
22 23 24
VDD VREF VOUTB
PIN CONFIGURATIONS
VOUTA 1 AGND 2 DGND 3 LDA 4 SHDN 5 RS 6
24 23 22 21
VOUTB VREF VDD LDB A/B CS
VOUTA 1 AGND 2 DGND 3 LDA 4 SHDN 5 RS 6
24 23 22 21
VOUTB VREF VDD LDB A/B
AD7396
20 19
TOP VIEW D0 7 (Not to Scale) 18 D11
17 16 15 14 13
CS TOP VIEW NC 7 (Not to Scale) 18 D9
19
AD7397
20
D1 8 D2 9 D3 10 D4 11 D5 12
D10 D9 D8 D7 D6
NC 8 D0 9 D1 10 D2 11 D3 12
17 16 15 14 13
D8 D7 D6 D5 D4
NC = NO CONNECT
-6-
REV. 0
Typical Performance Characteristics- AD7396/AD7397
1.5
1.0 30 VDD = +2.7V VREF = +2.5V
VDD = +3V VREF = +2.5V
AD7396
TA = -55 C
0.8 0.6 0.4
INL - LSB
AD7397
AD7397
1.0
SS = 200 UNITS TA = +25 C VDD = +2.7V VREF = +2.5V
INL - LSB
0.2 0.0 -0.2 -0.4 -0.6 -0.8
0.0 -0.5 -1.0
FREQUENCY
0.5
TA = -55 C
20
TA = +25 C, +85 C
10 TA = +25 C, +85 C
-1.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE - Decimal
-1.0
0
128 256 384 512 640 768 CODE - Decimal
896 1024
0
-5
0 5 10 TOTAL UNADJUSTED ERROR HISTOGRAM - LSB
Figure 4. AD7396 INL vs. Code and Temperature
Figure 5. AD7397 INL vs. Code and Temperature
Figure 6. AD7397 TUE Histogram
1.0 0.8 0.6 0.4
FREQUENCY DNL - LSB
60
100
AD7397
VDD = +2.7V VREF = +2.5V
AD7396
SS = 200 UNITS VDD = +2.7V VREF = +2.5V TA = -40 C TO +85 C
FREQUENCY
80
SS = 200 UNITS VDD = +2.7V VREF = +2.5V TA = -40 C TO +85 C
AD7397
40
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 CODE - Decimal TA = +25 C, +85 C, -55 C SUPERIMPOSED
60
40
20
20
0 -55 -50 -45 -40 -35 -30 FULL-SCALE OUTPUT TEMPCO HISTOGRAM - ppm/ C
0
-70
-30 -60 -50 -40 FULL-SCALE TEMPCO - ppm/ C
Figure 7. AD7397 DNL vs. Code and Temperature
Figure 8. AD7396 Full-Scale Tempco Histogram
Figure 9. AD7397 Full-Scale Tempco Histogram
1.5
40
40
10
AD7396
1.0
OUTPUT NOISE DENSITY - V/ Hz
8
VDD = +5V VREF = +2.5V TA = +25 C
20
0.5
INL - LSB
20
FSE - LSB
FSE - mV
6
0 VDD = +5V TA = +25 C CODE = HALF SCALE
0
0
4
-0.5
-20
-20 VDD = +5V TA = +25 C FSE (LSB) = FSE (V) 0 1
-1.0
2
4096/VREF (V) -40 4 5
0 1 10 100 1k FREQUENCY - Hz 10k 100k
-1.5
0
-40
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF - Volts
2 3 VREF - V
Figure 10. INL Error vs. Reference Voltage
Figure 11. Full-Scale Error vs. Reference Voltage
Figure 12. Output Noise Voltage Density vs. Frequency
REV. 0
-7-
AD7396/AD7397
0 -5 -10 -15
GAIN - dB 1.257 1.262 VDD = +5V VREF = +2.5V TA = +25 C CODE = 800H TO 7FFH 5mV/DIV
IDD - A
145 140 135 130 125 120 115 VIN = 0V TO +3V VIN = +3V TO 0V VDD = +3V TA = +25 C
VDD = +3V CODE = FULL SCALE
-20 -25 -30 -35 -40 -45 -50 100 1k 10k 100k FREQUENCY - Hz 1M
VOUT - Volts
1.252
1.247
1.242
110 105
1.237 TIME - 2 s/DIV
100 0 0.5 1 1.5 2 LOGIC INPUT - VIN (Volts) 2.5 3
Figure 13. Reference Multiplying Gain vs. Frequency
Figure 14. Midscale Transition Performance
Figure 15. IDD vs. Logic Input Voltage
5.0 TA = +25 C
IOUT CURRENT SOURCING - mA
35 30 25 VDD = +3V 20 15 10 5 0 -120 VDD = +5V VREF = +2.5V TA = +25 C
45 40
IOUT CURRENT SINKING - mA
4.5 LOGIC THRESHOLD - V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 3 4 5 VDD - V 6 7 VLOGIC FROM HIGH TO LOW
VREF = +2.5V TA = +25 C
35 30 25 20 15 10 5 VDD = +3V VDD = +5V
VLOGIC FROM LOW TO HIGH
-100
-80
-60 -40 VOUT - mV
-20
0
0 0
2
4
6 8 VOUT - mV
10
12
Figure 16. Logic Threshold Voltage vs. VDD
Figure 17. IOUT Source Current vs. VOUT
Figure 18. IOUT Sink Current vs. VOUT
170 160
180 160 140
IDD - A
VDD = +3.6V, VLOGIC = +2.4V 150 140
IDD - A
VDD = +5V VDD = +3V
IDD_SD SHUTDOWN CURRENT - nA
VREF = +2.5V
200 TA = +25 C
1000 VREF = +2.5V VDD = +5V SHDN = 0V 100
130 120 110
VDD = +5V, VLOGIC = +5V
120 100 80 60 40 20 0
10
VDD = +3V, VLOGIC = +3V 100 90 80 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE - C
0
1
2 3 VREF - Volts
4
5
1 -40 -20
0
20 40 60 80 100 120 140 TEMPERATURE - C
Figure 19. IDD vs. Temperature
Figure 20. IDD vs. Reference Voltage
Figure 21. Shutdown Current vs. Temperature
-8-
REV. 0
AD7396/AD7397
1400 80
NOMINAL CHANGE IN VOLTAGE - mV
1.0
AD7396
1200 1000
IDD - A
AD7396
SAMPLE SIZE = 77 VREF = +2.5V
70 A: B: C: D: VDD = +2.7V, CODE = 555H VDD = +2.7V, CODE = 3FFH VDD = +5.5V, CODE = 155H VDD = +5.5V, CODE = 3FFH D 60
PSRR - dB
VDD = +5V,
5%
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 100 200 300 400 500 600 HOURS OF OPERATION AT +150 C CODE = 000H CODE = FFFH
50 40 30 20 VDD = +3V, 5%
800 600 400 200
C
A B
10 0
0 1k
10k 100k 1M DIGITAL INPUT FREQUENCY - Hz
10M
1
10
100 1k FREQUENCY - Hz
10k
Figure 22. IDD vs. Digital Input Frequency
OPERATION
Figure 23. PSRR vs. Frequency
Figure 24. Long-Term Drift Accelerated by Burn-In
VOUT = VREF x D/2N
(1)
The AD7396 and AD7397 are a set of pin compatible, 12-bit and 10-bit digital-to-analog converters. These single-supply operation devices consume less than 200 A of current while operating from power supplies in the +2.7 V to +5.5 V range, making them ideal for battery operated applications. They contain a voltage-switched, 12-bit/10-bit, digital-to-analog converter, rail-to-rail output op amps, and a parallel-input DAC register. The external reference input has constant 2.5 M input resistance independent of the digital code setting of the DAC. In addition, the reference input can be tied to the same supply voltage as VDD resulting in a maximum output voltage span of 0 to VDD. The parallel data interface consists of 12 data bits, DB0-DB11, for the AD7396, 10 data bits, DB0-DB9, for the AD7397, and a CS write strobe. An RS pin is available to reset the DAC register to zero scale. This function is useful for power-on reset or system failure recovery to a known state. Additional power savings are accomplished by activating the SHDN pin resulting in a 1.5 A maximum consumption sleep mode. As long as the supply voltage, remains data will be retained in the DAC and input register to supply the DAC output when the part is taken out of shutdown.
AD7396
LDA DACA REGISTER VDD 12 12-BIT DACA VOUTA
where D is the decimal data word loaded into the DAC register, and N is the number of bits of DAC resolution. In the case of the 10-bit AD7397 using a 2.5 V reference, Equation 1 simplifies to: VOUT = 2.5 x D/1024 (2) Using Equation 2, the nominal midscale voltage at VOUT is 1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step size is = 2.5 x 1/1024 = 0.0024 V. For the 12-bit AD7396 operating from a 5.0 V reference equation [1] becomes: VOUT = 5.0 x D/4096 Using Equation 3, the AD7396 provides a nominal midscale voltage of 2.50 V for D = 2048, and a full-scale output of 4.998 V. The LSB step size is = 5.0 x 1/4096 = 0.0012 V.
AMPLIFIER SECTION
(3)
CS A/B DATA
INPUTA REGISTER 12 1 VREF
INPUTB REGISTER 12
The internal DAC's output is buffered by a low power consumption precision amplifier. The op amp has a 60 s typical settling time to 0.1% of full scale. There are slight differences in settling time for negative slewing signals versus positive. Also, negative transition settling time to within the last 6 LSBs of zero volts has an extended settling time. The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 26 shows an equivalent output schematic of the rail-to-rail-amplifier with its N-channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P-channel pull-up device that can source current to GND terminated loads.
VDD P-ch
LDB
DACB REGISTER
12-BIT DACB
VOUTB AGND
DGND
RS
SHDN
Figure 25. Functional Block Diagram
D/A CONVERTER SECTION
N-ch
VOUT
The voltage switched R-2R DAC generates an output voltage dependent on the external reference voltage connected to the REF pin according to the following equation: REV. 0 -9-
AGND
Figure 26. Equivalent Analog Output Circuit
AD7396/AD7397
The rail-to-rail output stage provides 1 mA of output current. The N-channel output pull-down MOSFET shown in Figure 26 has a 35 ON resistance, which sets the sink current capability near ground. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 100 pF capacitive load driving capability.
REFERENCE INPUT
+2.7V TO +5.5V
*
CS A/B LDA LDB DATA
C REF VDD
0.1 F
+
10 F
AD7396 OR AD7397
DGND AGND
VOUTA VOUTB
The reference input terminal has a constant input resistance independent of digital code, which results in reduced glitches on the external reference voltage source. The high 2.5 M input resistance minimizes power dissipation within the AD7396/ AD7397 D/A converters. The VREF input accepts input voltages ranging from ground to the positive-supply voltage VDD. One of the simplest applications, which saves an external reference voltage source, is connection of the VREF terminal to the positive VDD supply. This connection results in a rail-to-rail voltage output span maximizing the programmed range. The reference input will accept AC signals as long as they are kept within the supply voltage range, 0 < VREF IN < VDD. The reference bandwidth and integral nonlinearity error performance are plotted in the Typical Performance Characteristics section, see Figures 10 and 13. The ratiometric reference feature makes the AD7396/AD7397 an ideal companion to ratiometric analog-to-digital converters such as the AD7896.
POWER SUPPLY
*OPTIONAL EXTERNAL
REFERENCE BYPASS
Figure 27. Recommended Supply Bypassing
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection structure (Figure 28) that allows logic input voltages to exceed the VDD supply voltage. This feature can be useful if the user is driving one or more of the digital inputs with a 5 V CMOS logic input-voltage level while operating the AD7396/AD7397 on a +3 V power supply. If this mode of interface is used, make sure that the VOL of the 5 V CMOS meets the VIL input requirement of the AD7396/AD7397 operating at 3 V. See Figure 16 for a graph for digital logic input threshold versus operating VDD supply voltage.
VDD LOGIC IN GND
The very low power consumption of the AD7396/AD7397 is a direct result of a circuit design optimizing the use of a CBCMOS process. By using the low power characteristics of CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD7396/AD7397 is the wide range of usable supply voltage. The part is fully specified and tested for operation from +2.7 V to +5.5 V.
POWER SUPPLY BYPASSING AND GROUNDING
Figure 28. Equivalent Digital Input ESD Protection
Precision analog products such as the AD7396/AD7397 require a well filtered power source. Since the AD7396/AD7397 operates from a single +3 V to +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches, hundred of millivolts in amplitude, due to wiring resistance and inductance. The power supply noise generated thereby means that special care must be taken to assure that the inherent precision of the DAC is maintained. Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the 12-bit AD7396. The AD7396 should be powered directly from the system power supply. Whether or not a separate power supply trace is available generous supply bypassing will reduce supply line-induced errors. Local supply bypassing consisting of a 10 F tantalum electrolytic in parallel with a 0.1 F ceramic capacitor is recommended in all applications (Figure 27).
In order to minimize power dissipation from input-logic levels that are near the VIH and VIL logic input voltage specifications, a Schmitt trigger design was used that minimizes the input-buffer current consumption compared to traditional CMOS input stages. Figure 15 shows a plot of incremental input voltage versus supply current showing that negligible current consumption takes place when logic levels are in their quiescent state. The normal crossover current still occurs during logic transitions. A secondary advantage of this Schmitt trigger is the prevention of false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or optoisolators are used. The logic inputs DB11-DB0, A/B CS, RS, SHDN all contain Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7396/AD7397 has a double-buffered, parallel-data input. A functional block diagram of the digital section is shown in Figure 25, while Table I contains the truth table for the logic control inputs. The chip select (CS) and A/B pins control loading of data from the data inputs on pins DB11-DB0 into the internal Input Register. The CS active low input places data into the decoded A/B input register. When CS returns to logic high within the data setup-and-hold time specifications the new value of data in the input register will be latched. See Truth Table for complete set of conditions. New data can only be transferred to the corresponding DAC register when its LDx pin is strobed active low. The LDx inputs are level-sensitive (DAC Registers are transparent latches) and can be tied active low
-10-
REV. 0
AD7396/AD7397
allowing any new Input Register data updates to directly control the DAC output voltages for single-buffered applications. For doubled-buffered applications where both DAC outputs, VOUTA and VOUTB, need to be changed simultaneously to a new value, the two inputs, LDA and LDB, can be tied together and pulsed active low in a synchronous manner.
RESET (RS) PIN Table II. Unipolar Code Table
Hexadecimal Number In DAC Register FFF 801 800 7FF 000
Decimal Number In DAC Register 4095 2049 2048 2047 0
Output Voltage (V) (VREF = 2.5 V) 2.4994 1.2506 1.2500 1.2494 0
Forcing the asynchronous RS pin low will set the Input and DAC registers to all zeros and the DAC output voltage will be zero volts. The reset function is useful for setting the DAC outputs to zero at power-up or after a power supply interruption. Test systems and motor controllers are two of many applications that benefit from powering up to a known state. The external reset pulse can be generated by the microprocessor's power-on RESET signal, from the microprocessor, or by an external resistor and capacitor. RESET has a Schmitt trigger input which results in a clean reset function when using external resistor/capacitor generated pulses. See Table I, Control-Logic Truth.
POWER SHUTDOWN (SHDN)
The circuit can be configured with an external reference plus power supply, or powered from a single dedicated regulator or reference, depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Maximum power savings can be achieved by using the power shutdown control function. This hardware-activated feature is controlled by the active low input SHDN pin. This pin has a Schmitt trigger input which helps to desensitize it to slowly changing inputs. By placing a logic low on this pin the internal consumption of the AD7397 or AD7397 is reduced to nanoamp levels, guaranteed to 1.5 A maximum over the operating temperature range. If power is present at all times on the VDD pin while in the shutdown mode, the internal DAC register will retain the last programmed data value. This data will be used when the part is returned to the normal active state by placing the DAC back to its programmed voltage setting. Shutdown recovery time measures 80 s. In the shutdown state the DAC output amplifier exhibits an open-circuit high-resistance state. Any load connected will stabilize at its termination voltage. If the power shutdown feature is not needed then the user should tie the SHDN pin to the VDD voltage thereby disabling this function.
UNIPOLAR OUTPUT OPERATION
Although the AD7397 has been designed for single supply operation, the output can easily be configured for bipolar operation. A typical circuit is shown in Figure 30. This circuit uses a clean regulated +5 V supply for power, which also provides the circuit's reference voltage. Since the AD7397 output span swings from ground to very near +5 V, it is necessary to choose an external amplifier with a common-mode input voltage range that extends to its positive supply rail. The micropower consumption OP196 has been designed just for this purpose and results in only 50 A of maximum current consumption. Connection of the equal-value 470 k resistors results in a differential amplifier mode of operation with a voltage gain of two, which produces a circuit output span of ten volts, that is, -5 V to +5 V. As the AD7397 DAC is programmed from zerocode 000H to midscale 200H to full-scale 3FFH, the circuit output voltage VO is set at -5 V, 0 V and +5 V (-1 LSB). The output voltage VO is coded in offset binary according to Equation 3. VOUT = [(D/512)-1] x 5 (4) where D is the decimal code loaded in the AD7397 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including the 470 k gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same resistor material, such as metal film). If better stability is required, the power supply could be substituted with a precision reference voltage such as the low dropout REF195, which can easily supply the circuit's 262 A of current and still provide additional power for the load connected to VO. The micropower REF195 is guaranteed to source 10 mA output drive current, but consumes only 50 A internally. If higher resolution is required, the AD7396 can be used with the addition of two more bits of data inserted into the software coding, which would result in a 2.5 mV LSB step size. Table III shows examples of nominal output voltages, VO, provided by the bipolar operation circuit application.
This is the basic mode of operation for the AD7396. As shown in Figure 29, the AD7396 has been designed to drive loads as low as 5 k in parallel with 100 pF. The code table for this operation is shown in Table II.
+2.7V TO +5.5V R 0.01 F VDD 0.1 F 10 F
AD7396
VREF EXT REF 16/14 DAC A 75k DAC B DIGITAL DGND AGND DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. 75k 100pF 100pF VOUTB VOUTA
C
Figure 29. Unipolar Output Operation
REV. 0
-11-
AD7396/AD7397
ISY < 262 A +5V 470k 200 A REF C VDD OP196 VOUTA -5V ONLY ONE CHANNEL SHOWN. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. 470k < 50 A
Table III. Bipolar Code Table
+5V VO BIPOLAR OUTPUT SWING -5V
Hexadecimal Number Decimal Number In DAC Register In DAC Register 3FF 201 200 1FF 000 1023 513 512 511 0
Analog Output Voltage (V) 4.9902 0.0097 0.0000 -0.0097 -5.0000
GND
Figure 30. Bipolar Output Operation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead SOIC Package (R-24)
0.6141 (15.60) 0.5985 (15.20)
24-Lead Narrow Body Plastic DIP Package (N-24)
1.275 (32.30) 1.125 (28.60)
24 13 12
0.4193 (10.65) 0.3937 (10.00)
24
0.2992 (7.60) 0.2914 (7.40)
13
1
PIN 1 0.210 (5.33) MAX
1
12
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.280 (7.11) 0.240 (6.10)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0138 (0.35) PLANE 0.0125 (0.32) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
24-Lead Thin Surface Mount TSSOP Package (RU-24)
0.311 (7.90) 0.303 (7.70)
24 13
1
12
0.006 (0.15) 0.002 (0.05)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
-12-
REV. 0
PRINTED IN U.S.A.
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
C3425-8-10/98
AD7397

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