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DS80CH10
DS80CH10 Green Energy Manager
PRODUCT SPECIFICATION
V2.5
020299 1/94
DS80CH10
TABLE OF CONTENTS
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2.0
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4.0
5.0
6.0
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 DETAILED FEATURE SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 ADDITIONAL REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 PIN FUNCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CORE MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 CORE MICRO OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 SPEED IMPROVEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 INSTRUCTION SET ADDITIONAL REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 INTERRUPT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MEMORY RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 DATA MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.1 Stretch Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.2 Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 EXTERNAL MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 DIRECT (SCRATCHPAD) RAM ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CORE I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 PROGRAMMABLE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 PARALLEL I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.1 Alternate Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2-WIRE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.1 2WFS - 2-Wire Frequency Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.2 2WDAT - 2-Wire Data I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.3 2WSADR - 2-Wire Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.4 2WCON - 2-Wire Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.5 2WSTAT1 - 2-Wire Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.6 2WSTAT2 - 2-Wire Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 OPERATION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.1 Master Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.2 Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.3 Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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6.3.4 Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.5 Bus Monitor Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 ANALOG POWER / SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3 REFERENCE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 SAR A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5 CONVERSION TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.6 WINDOW COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.7 A/D OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.8 A/D SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.8.1 ADCON1 - A/D Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.8.2 ADCON2 - A/D Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8.3 ADMSB - A/D Result Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8.4 ADLSB - A/D Result Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.8.5 WINHI - A/D Window Comparator High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.8.6 WINLO - A/D Window Comparator Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ACTIVITY MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2 ACTIVITY MONITOR INPUT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3 AME - ACTIVITY MONITOR ENABLE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.4 AMQ - ACTIVITY MONITOR QUALIFIER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.5 AMP - ACTIVITY MONITOR POLARITY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.6 AMF - ACTIVITY MONITOR FLAG REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 HOST INTERFACE PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2 REGISTER MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3 KBDIN / PMDIN - DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4 KBSTAT / PMSTAT - STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.5 KBDOUT / PMDOUT - OUTPUT DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 KEYBOARD SCANNING PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.2 KEY SCAN OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3 KEY SCAN INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4 KDE - KEY DETECT ENABLE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5 KDF - KEYBOARD DETECT FLAG REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MOUSE / DETACHED KEYBOARD SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.2 INTERFACE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.3 DATA TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.4.1 MSDAT / DKDAT - Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.4.2 MSCON / DKCON - Control / Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6 INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.7 DATA OUTPUT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.8 DATA INPUT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.8.1 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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PULSE WIDTH MODULATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.1 FUNCTION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2 PRESCALER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3 PWM CLOCK GENERATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.4 PWM PULSE GENERATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.5 PWM SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.5.1 PW01CS / PW23CS - PWM 0, 1 / PWM 2, 3 Clock Select Registers . . . . . . . . . . . . . . 67 12.5.2 PW01CON / PW23CON - PWM 0, 1 / PWM 2, 3 Control Register . . . . . . . . . . . . . . . . 68 12.5.3 PWnFG - PWM n Frequency Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.5.4 PWMn - PWM n Value Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MICROCONTROLLER POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.1 POWER-DOWN / POWER-UP OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.1.1 Microcontroller Power Fail Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2 LOW POWER OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2.1 Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2.2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.2.3 Stop Mode and Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 +5.0V ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.1 ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.2 MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.3 MICROCONTROLLER AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.3.1 External Program Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.3.2 MOVX Using Stretch Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.3.3 External Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.3.4 Serial Port Mode 0 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.3.5 Power Cycle Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.4 SYSTEM INTERFACE DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.5 HOST I/F AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.6 2-WIRE AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.7 MOUSE/DETACHED KEYBOARD SERIAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . 92 14.8 A/D CONVERTER SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.8.2 A/D Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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1.0 1.1
GENERAL DESCRIPTION OVERVIEW
The Green Energy Manager is a highly integrated microcontroller that provides several key features for portable systems including key scanning and control, battery and power management, hardware mouse and detached keyboard ports, as well as a 2-wire serial I/O port. It incorporates the new Dallas 8051-compatible high-speed microcontroller core which has been redesigned to eliminate wasted clock and memory cycles. Every standard 8051 instruction is executed between 1.5 and 3 times faster than the original for the same crystal speed. Looking at it another way, the high- speed core achieves the same throughput as a standard 8051 while using much less power as a result of fewer required clock cycles. As a result, the firmware can easily support many tasks required by mobile systems within a single component. The controller is designed to off-load battery and power management tasks from the host CPU and thereby make possible an efficient solution for portable systems. In addition to the microcontroller core, it incorporates an 8-channel, 10-bit A/D converter with external reference so that its firmware can perform battery management tasks without burdening the host CPU. A four-
channel 8-bit pulse-width modulator allows digital control of functions such as LCD contrast and brightness. An 8-bit port is provided for key scan inputs. A total of 80 parallel I/O pins are available for key scanning, system configuration, and power management control. The Green Energy Manager scans a key matrix and interfaces to the host CPU via an 8042-compatible port. As a result, it replaces a keyboard controller chip in a typical portable PC system design. The benefits of sophisticated power management and permanently powered functions are thereby attained without adding to the system's chip count. A 2-wire, bi-directional serial bus is incorporated to facilitate the management of slave peripheral devices on the motherboard, such as digital temperature sensors and potentiometers, and to support external low- speed I/O devices such as monitor configuration channels, pen tablets, and joysticks. Because a direct interface to the X-bus is provided, the controller is not dependent on a particular core logic chip or chip set. Independent chip select inputs for the keyboard controller and power management registers are provided.
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DS80CH10
KEYBOARD CONTROLLER BLOCK DIAGRAM Figure 1-1
P7.7 / AMI.7 / XTAL1 XTAL2 LED.7
P7.0 / AMI.0 / LED.0 HVCC
HGND
VPFW VRST GND 3
POWER MON./ CONTROL
VCC
3
uC CLK OSC.
PORT 7 / ACT. MONITOR / LED DRIVERS
POWER CONTROL
4 MHz RING OSC. SYS. CLOCK CONTROL SCRATCHPAD REGISTERS (256 BYTES)
EA ALE PSEN RST P3.7 / RD P3.6 / WR P3.5 / T1 P3.4 / T0 P3.3 / INT1 P3.2 / INT0 P3.1 / TXD0 P3.0 / RXD0 P1.7 / DKDIO P1.6 / DKCLK P1.5 / MSDIO P1.4 / MSCLK P1.3 / SDA P1.2 / SCL P1.1 / T2EX P1.0 / T2 P6.7 / SOC P6.6 P6.5 / PWI.1 P6.4 / PWI.0 P6.3 / PWO.3 P6.2 / PWO.2 P6.1 / PWO.1 P6.0 / PWO.0
TIMING / BUS CONTROL
WATCHDOG TIMER
SPECIAL FUNCTION REGISTERS uC I/F
PMC STATUS PMC OUTPUT PMC INPUT PC I/F
PMCS SMI
TIMER 2 TIMER 1 TIMER 0 INT 1 INT 0 8051 UART MOUSE / DET. KEYB. SIO HIGH SPEED 80C520 CPU CORE
PORT 3
KBC STATUS KBC OUTPUT KBC INPUT PC I/F uC I/F
KBOBF KBCS A0 IOR IOW SD7-SD0 AVCC AGND P5.7 / AI.7 PORT 5 / 10-BIT ADC
PORT 1
ACC. BUS SIO 256 x 8 DATA RAM
PORT 6 / PWM I/O
P5.0 / AI.0 VRH VRL
PORT 0
PORT 2
PORT 4 / KEYBOARD IN
PORT 8/ KEYBOARD OUT
PORT 9/ KEYBOARD OUT
P0.7 / AD7
P0.0 / AD0
P2.7 / A15
P2.0 / A8
P4.7 / KSI.7
P4.0 / P8.7/ KSI.0 KS0.7
P8.0/ P9.7/ KS0.0 KS0.15
P9.0/ KS0.8
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DS80CH10
1.2
DETAILED FEATURE SUMMARY
- High performance 4 clocks / machine cycle (8032 = 12) - Low Power: typically 1/3 power for equivalent 8032 throughput - Maximum clock speed up to 33 MHz at 5.0V - Ultra-low stop mode power (typ. 1 uA) and "IDLE" mode (typ. 10 mA) - Multiple wake-up sources from STOP including key scan, 2-wire, host I/F, mouse or detached keyboard input, or external interrupt - Three 16-bit timers, 1 serial port - 256 byte scratchpad - 256 bytes MOVX SRAM
* 2-Wire Bi-directional Serial Bus
- Master/slave multi-drop operation - Manages on-board slaves or external I/O devices
* High Speed 80C32 Compatible Core:
* Mouse / Detached Keyboard Ports
- PS/2 compatible serial I/O hardware - 2-channels for external mouse or detached keyboard applications
* Power Control
- Provides complete lithium backup for system - Generates system power on reset - Programmable power down pin states
1.3
CONVENTIONS
* Keyboard Control:
- Replaces 8042 and key scan microcontroller - 2 Parallel I/O ports for key scan outputs - One interrupt-driven 8-bit input port to initiate key-scan sequence
The following conventions are used throughout this specification:
* "GEM"
is the short form name used to indicate the Green Energy Manager. symbol (#) or backslash (\), or are indicated with an overbar.
* Input/Output:
- Total of ten 8-bit I/O ports; all pins can be individually programmed to serve as general purpose digital input/output. - Each 8-bit port supports one or more special functions: Port 0, 2, 3: External program / data memory interface Port 1, 3: UART, 2-wire serial, mouse serial, detached keyboard serial, timers, and external interrupt I/O. Port 4, 8, 9: Key scan input / output Port 5: A/D inputs Port 6: PWM Outputs Port 7: Activity monitor, LED drive
* Signals that are active low are followed by a pound * If a range of signals is described, such as SA0 through
SA10, the range is given as SA10-0, with the most- significant digit first and the least-significant digit last, separated by a hyphen.
* Numbers written in this specification can be written as
decimal, hexadecimal, or binary. Hexadecimal numbers are followed by an "H" suffix. Binary numbers are followed by a "B" suffix. For example, decimal 27 = 1BH = 00011011B.
1.4
ADDITIONAL REFERENCES
* Analog Input/Output:
- Eight-channel, 10-bit A/D with power down mode supports charging NiMH rechargeable cells - 4-channel, 8-bit PWM supports LCD brightness and contrast control
The GEM incorporates the Dallas 8051 compatible High Speed Micro core including the CPU and many of its core peripherals. The operational details of these elements are contained in the Dallas High Speed Micro User's Guide.
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DS80CH10
2.0
PIN DESCRIPTION
128-TQFP PIN ASSIGNMENT Figure 2-1
P9.7 / KSO.15 P9.6 / KSO.14 P9.5 / KSO.13 P9.4 / KSO.12 P9.3 / KSO.11 P9.2 / KSO.10 P9.1 / KSO.9 P9.0 / KSO.8 P8.7 / KSO.7 P8.6 / KSO.6 P8.5 / KSO.5 P8.4 / KSO.4 P8.3 / KSO.3 P8.2 / KSO.2 P8.1 / KSO.1 P8.0 / KSO.0 GND VCC P6.7 / SOC P6.6 P6.5 / PWI.1 P6.4 / PWI.0 P6.3 / PWO.3 P6.2 / PWO.2 P6.1 / PWO.1 P6.0 / PWO.0 P5.7 / AI.7 P5.6 / AI.6 P5.5 / AI.5 P5.4 / AI.4 P5.3 / AI.3 P5.2 / AI.2 P5.1 / AI.1 P5.0 / AI.0 GND A0 IOW IOR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 VCC XTAL2 XTAL1 GND P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 EA PSEN ALE RST P3.7 / RD P3.6 / WR
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VRST VPFW P3.5 / T1 P3.4 / T0 P3.3 / INT1 P3.2 / INT0 P3.1 / TXD0 P3.0 / RXD0 P1.7 / DKDIO P1.6 / DKCLK P1.5 / MSDIO P1.4 / MSCLK P1.3 / SDA P1.2 / SCL P1.1 / T2EX P1.0 / T2 GND VCC P4.7 / KSI.7 P4.6 / KSI.6 P4.5 / KSI.5 P4.4 / KSI.4 P4.3 / KSI.3 P4.2 / KSI.2 P4.1 / KSI.1 P4.0 / KSI.0 P7.7 / AMI.7 / LED.7 P7.6 / AMI.6 / LED.6 P7.5 / AMI.5 / LED.5 P7.4 / AMI.4 / LED.4 P7.3 / AMI.3 / LED.3 P7.2 / AMI.2 / LED.2 P7.1 / AMI.1 / LED.1 P7.0 / AMI.0 / LED.0 HVCC NC HGND HVCC
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SMI KBOBF PMCS KBCS AGND VRH VRL AVCC HGND SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 CX2 CX1 NC HVCC HGND HVCC HVCC HVCC NC
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
DS80CH10
2.1
PIN 36
PIN FUNCTION SUMMARY
SYMBOL A0 DESCRIPTION Command / Data Select: Input. Address input used by the host processor in data transfers to the keyboard controller and power management interface ports to indicate whether the transfer is command (A0=1) or data (A0=0). Analog Ground. Address Latch Enable: Output. This signal functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of 4 XTAL1 cycles. ALE is forced high when the GEM is in a Reset condition. ALE can also be disabled using the EMI reduction mode. Analog VCC. Crystal Inputs: Connections for a standard 32.768 KHz quartz crystal. The GEM must be used with a crystal that has a specified load capacitance of either 6 pF or 12.5 pF. The crystal is attached directly to the CX1 and CX2 pins. There is no need for external capacitors or resistors. Note: CX1 and CX2 are very high impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. The GEM can also be driven by an external 32.768 KHz oscillator. In this configuration, the CX1 pin is connected to the external oscillator signal and the CX2 pin is floated.
43 106
AGND ALE
46 57 56
AVCC CX1 CX2
108
EA
External Access: Input. Connect EA to ground to force the controller to use external program memory. The internal RAM is still accessible as determined by register settings. Digital circuit ground.
17 35 86 117 47 60 66 68 59 61 62 63 65 38
GND
HGND
Host Interface Ground:
HVCC
Host Interface VCC:
IOR
I/O Read: Input. I/O Read is used to signal a read operation is in effect on the host address/data bus.
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DS80CH10
PIN 37 42 40
SYMBOL IOW KBCS KBOBF
DESCRIPTION I/O Write: Input. I/O Write is used to signal a write operation is in effect on the host address/data bus. Keyboard Chip Select: (Input, active low). This is a chip select signal used to enable the keyboard control host interface port. Keyboard Output Buffer Full: (Output, active high). This signal is set when the keyboard control host interface data buffer contains data to be read by the host. KBOBF will be driven low when host reads the keyboard control data buffer register. No Connection.
64 58 67 121 122 123 124 125 126 127 128 87 88 89 90 91 92 93 94
NC
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P1.0 (T2) P1.1 (T2EX) P1.2 (SCL) P1.3 (SDA) P1.4 (MSCLK) P1.5 (MSDIO) P1.6 (DKCLK) P1.7 (DKDIO)
Port 0 / Address/Data Outputs 7-0: I/O. Port 0 is an open-drain 8-bit bi-directional I/O port. As an alternate function Port 0 can function as the multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bi-directional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-state. Pull-up resistors are required when using Port 0 as an I/O port. Port 1/ (Alternate Functions): - I/O. Port 1 provides eight lines which can be individually selected as bi-directional I/O port pins or as the alternate functions listed below: Alternate Function T2 T2EX SCL SDA MSCLK MSDIO DKCLK DKDIO
Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Description External I/O for Timer/Counter 2 Timer/Counter 2 Capture/Reload Trigger 2-Wire Serial Clock 2-Wire Serial Data Mouse Port Clock Mouse Port Data Detached Keyboard Clock Detached Keyboard Data
Note that P1.7 - P1.2 are high-drive pins which are always open-drain and must be used with external pull-ups when used as I/O port pins. P1.1 and P1.0 have internal pull-up resistors. 109 110 111 112 113 114 115 116 P2.0 (A8) P2.1 (A9) P2.2 (A10) P2.3 (A11) P2.4 (A12) P2.5 (A13) P2.6 (A14) P2.7 (A15) Port 2 / Address Outputs A15-8: - I/O. Port 2 is a pseudo-bi-directional I/O port with internal pull-up resistors. As an alternate function Port 2 can function as MSB of the external address bus.
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DS80CH10
95 96 97 98 99 100 103 104
P3.0(RXD0) P3.1 (TXD0) P3.2 (INT0) P3.3 (INT1) P3.4 (T0) P3.5 (T1) P3.6 (WR) P3.7 (RD)
Port 3 / (Alternate Functions): - I/O. Port 3 provides eight lines each of which can serve as psuedo-bi-directional I/O port pins or as the alternate functions as listed below. Internal pull-up resistors are always present on these pins. Alternate Function RXD0 TXD0 INT0 INT1 T0 T1 WR RD
Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Description Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1 Timer 0 External Input Timer 1 External Input External Data Memory Write Strobe External Data Memory Read Strobe
77 78 79 80 81 82 83 84 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P4.0 (KSI.0) P4.1 (KSI.1) P4.2 (KSI.2) P4.3 (KSI.3) P4.4 (KSI.4) P4.5 (KSI.5) P4.6 (KSI.6) P4.7 (KSI.7) P5.0 (AI.0) P5.1 (AI.1) P5.2 (AI.2) P5.3 (AI.3) P5.4 (AI.4) P5.5 (AI.5) P5.6 (AI.6) P5.7 (AI.7) P6.0 (PWO.0) P6.1 (PWO.1) P6.2 (PWO.2) P6.3 (PWO.3) P6.4 (PWI.0) P6.5 (PWI.1) P6.6 P6.7 / SOC
Port 4 / KSI.7-0: - I/O / Keyboard Scan Inputs. Port 4 provides eight lines which can be individually selected as psuedo-bi-directional I/O port pins or as an interrupt Inputs for key scanning. Port 4 pins incorporate Schmitt inputs with pull-up resistors.
Port 5 / AI.7-0: - I/O / A/D inputs. Port 5 provides eight lines which can be individually selected as open-drain psuedo-bi-directional I/O port pins or as A/D inputs. Pull-up resistors are required when using Port 5 as an I/O port.
Port 6 / PW0.3 - 0: - I/O / Pulse-Width Modulated Outputs. Port 6 provides eight lines which can all serve as psuedo-bi-directional I/O port pins with internal pull-up resistors. Six lines can be individually selected to serve the pulse-width modulator function indicated below: Alternate Function PWO.0 PWO.1 PWO.2 PWO.3 PWI.0 PWI.1 (none) SOC
Port P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7
Description PWM 0 output (active high drive when enabled) PWM 1 output (active high drive when enabled) PWM 2 output (active high drive when enabled) PWM 3 output (active high drive when enabled) Optional clock input for PWM channels 0 and 2 Optional clock input for PWM channels 1 and 3 External A / D start of conversion signal
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DS80CH10
PIN 69 70 71 72 73 74 75 76 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 41 107
SYMBOL P7.0 (AMI.0) (LED.0) P7.1 (AMI.1) (LED.1) P7.2 (AMI.2) (LED.2) P7.3 (AMI.3) (LED.3) P7.4 (AMI.4) (LED.4) P7.5 (AMI.5) (LED.5) P7.6 (AMI.6) (LED.6) P7.7 (AMI.7) (LED.7) P8.0 (KSO.0) P8.1 (KSO.1) P8.2 (KSO.2) P8.3 (KSO.3) P8.4 (KSO.4) P8.5 (KSO.5) P8.6 (KSO.6) P8.7 (KSO.7) P9.0 (KSO.8) P9.1 (KSO.9) P9.2 (KSO.10) P9.3 (KSO.11) P9.4 (KSO.12) P9.5 (KSO.13) P9.6 (KSO.14) P9.7 (KSO.15) PMCS PSEN
DESCRIPTION Port 7 / AMI.7-0 / LED.7-0: - I/O / Activity Monitor Inputs / LED drive outputs. Port 7 provides eight lines which can serve as a psuedo-bi-directional I/O port pins with internal pull-ups or as Activity Monitor inputs. When used as Activity Monitor inputs, these pins are typically connected to the chip select line of an external peripheral device, and can be programmed to sense active-high or active-low signals. Any pin which is programmed as an Activity Monitor input by setting its AMEn bit to a 1 will have its pull-up device disabled and thereby function as an open-drain pin in order to eliminate unnecessary current drain. All port 7 pins are capable of driving LED's.
Port 8 / KSO.7-0:- I/O. Port 8 provides eight lines of open-drain psuedo-bi-directional I/O port pins. Typically, these lines are used for key-scan outputs.
Port 9 / KSO.15-8: - I/O. Port 9 provides eight lines of open-drain psuedo-bi-directional I/O port pins. Typically, these lines are used for key-scan outputs.
Power Management Chip Select: (Input, active low). This is a chip select signal used to enable the power management host interface port. Program Store Enable: Output. This signal goes low when off-chip program memory is being accessed via Ports 0 and 2. It is commonly connected to optional external ROM memory as a chip enable. PSEN will provide an active low pulse and is driven high when external ROM is not being accessed. Reset: Input, active high The RST input pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pull-down resistor to allow for a combination of wired OR external Reset sources. An RC is not required for power-up, as the controller provides this function internally. System Data Bus: (Bi-directional). SD7-0 are data bus lines used for data transfers between the host processor and the keyboard interface buffer and power management interface buffer.
105
RST
55 54 53 52 51 50 49 48
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
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DS80CH10
PIN 39
SYMBOL SMI
DESCRIPTION System Management Interrupt: (Output, active low). This signal is driven low when the power management host interface data buffer contains data to be read by the host. SMI will be returned to a high level when host reads the power management data buffer register. Digital Power Supply Input: For microcontroller and associated functions.
18 85 120 101 44 45 102 118 119
VCC
VPFW VRH VRL VRST XTAL1 XTAL2
Power Fail Warning: Output, active low. The VPFW pin signals an impending power failure when VCC drops below VPFW voltage threshold. A/D Positive Voltage Reference: The VRH pin is the positive reference (upper voltage limit) of the A/D Converter. A/D Negative Voltage Reference: The VRL pin is the negative reference (lower voltage limit) of the A/D Converter. Power Fail Reset: Output, active low. The VRST pin signals a "power not good" condition to the system when system VCC has dropped below the VRST voltage threshold. C Crystal Oscillator Inputs. XTAL1 and XTAL2 provide support for parallel resonant, AT cut crystals. XTAL1 acts also as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier.
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DS80CH10
2.2
PIN CHARACTERISTICS
NAME A0 AGND ALE AVCC CX1 CX2 EA GND GND GND GND HGND HGND HGND HVCC HVCC HVCC HVCC HVCC HVCC IOR IOW KBCS KBOBF NC NC NC P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 POWER DOWN MODE STATE - - Low - (note 2) (note 2) - - - - - - - - - - - - - - - - - Hold - - - High-Z High-Z High-Z I/O BUFFER TYPE I - O - I O I - - - - - - - - - - - - - I I I O - - - Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) RESET STATE - - Low - (note 2) (note 2) - - - - - - - - - - - - - - - - - Low - - - High-Z High-Z High-Z
PIN 36 43 106 46 57 56 108 17 35 86 117 60 66 47 68 65 63 62 59 61 38 37 42 40 64 58 67 121 122 123
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2.2 PIN CHARACTERISTICS (cont'd)
PIN 124 125 126 127 128 87 88 89 90 91 92 93 94 109 110 111 112 113 114 115 116 95 96 97 98 99 NAME P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 P1.0 / T2 P1.1 / T2EX P1.2 / SCL P1.3 / SDA P1.4 / MSCLK P1.5 / MSDIO P1.6 / DKCLK P1.7 / DKDIO P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P2.5 / A13 P2.6 / A14 P2.7 / A15 P3.0 / RXD0 P3.1 / TXD0 P3.2 / INT0 P3.3 / INT1 P3.4 / T0 POWER DOWN MODE STATE High-Z High-Z High-Z High-Z High-Z Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold I/O BUFFER TYPE Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) Open-Drain (port) CMOS drive (bus) Pull-up Pull-up Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up RESET STATE High-Z High-Z High-Z High-Z High-Z Weak High Weak High High-Z High-Z High-Z High-Z High-Z High-Z Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High
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DS80CH10
2.2 PIN CHARACTERISTICS (cont'd)
PIN 100 103 104 77 78 79 80 81 82 83 84 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 69 NAME P3.5 / T1 P3.6 / WR P3.7 / RD P4.0 / KSI.0 P4.1 / KSI.1 P4.2 / KSI.2 P4.3 / KSI.3 P4.4 / KSI.4 P4.5 / KSI.5 P4.6 / KSI.6 P4.7 / KSI.7 P5.0 / AI.0 P5.1 / AI.1 P5.2 / AI.2 P5.3 / AI.3 P5.4 / AI.4 P5.5 / AI.5 P5.6 / AI.6 P5.7 / AI.7 P6.0 / PWO.0 P6.1 / PWO.1 P6.2 / PWO.2 P6.3 / PWO.3 P6.4 / PWI.0 P6.5 / PWI.1 P6.6 P6.7 / SOC P7.0 / AMI.0 / LED.0 POWER DOWN MODE STATE Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold I/O BUFFER TYPE Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Pull-up (PWMn disabled) CMOS drive (PWMn enabled) Pull-up (PWMn disabled) CMOS drive (PWMn enabled) Pull-up (PWMn disabled) CMOS drive (PWMn enabled) Pull-up (PWMn disabled) CMOS drive (PWMn enabled) Pull-up Pull-up Pull-up Pull-up Pull-up RESET STATE Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High Weak High
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DS80CH10
2.2 PIN CHARACTERISTICS (cont'd)
PIN 70 71 72 73 74 75 76 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 41 107 105 55 NAME P7.1 / AMI.1 / LED.1 P7.2 / AMI.2 / LED.2 P7.3 / AMI.3 / LED.3 P7.4 / AMI.4/ LED.4 P7.5 / AMI.5/ LED.5 P7.6 / AMI.6/ LED.6 P7.7 / AMI.7/ LED.7 P8.0 / KSO.0 P8.1 / KSO.1 P8.2 / KSO.2 P8.3 / KSO.3 P8.4 / KSO.4 P8.5 / KSO.5 P8.6 / KSO.6 P8.7 / KSO.7 P9.0 / KSO.8 P9.1 / KSO.9 P9.2 / KSO.10 P9.3 / KSO.11 P9.4 / KSO.12 P9.5 / KSO.13 P9.6 / KSO.14 P9.7 / KSO.15 PMCS PSEN RST SD0 POWER DOWN MODE STATE Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold Hold - Low - (note 2) I/O BUFFER TYPE Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain I O I Bi-directional RESET STATE Weak High Weak High Weak High Weak High Weak High Weak High Weak High High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z - Low - (note 2)
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DS80CH10
2.2 PIN CHARACTERISTICS (cont'd)
PIN 54 53 52 51 50 49 48 39 18 85 120 101 44 45 102 118 119 NAME SD1 SD2 SD3 SD4 SD5 SD6 SD7 SMI VCC VCC VCC VPFW VRH VRL VRST XTAL1 XTAL2 POWER DOWN MODE STATE (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) Hold - - - (note 3) - - (note 3) - H I/O BUFFER TYPE Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional O - - - O - - O I O RESET STATE (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) High - - - (note 3) - - (note 3) - -
PIN STATE DESCRIPTIONS
High-Z Enabled Unchanged High Impedance Power applied; electrically functioning input Previous state not affected
NOTES:
1. As shown above, the original port pins P1.7-P1.2 have been modified to open-drain instead of having "Internal" pull-up resistors. 2. This signal is independently powered from the HVCC on pin 68. As a result, the state of the reset pin and the power down mode have no effect on its operation. 3. VRST and VPFW reflects the state of VCC with respect to the power-fail reset and power-fail warning trip points, respectively, and is unaffected by the RST pin and power down mode state.
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3.0 3.1
CORE MICROCONTROLLER CORE MICRO OVERVIEW
run at 4 clocks per increment cycle to take advantage of higher speed operation. The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the "MOVX A, @ DPTR" instruction and the "MOV direct, direct" instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the GEM, the MOVX instruction can be done in two machine cycles or 8 oscillator cycles but the "MOV direct, direct" uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times from each other. This is because in most cases, the GEM uses one cycle for each byte. The timing of each instruction should be examined for familiarity with the changes. Note that a machine cycle now requires just four clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the original architecture, all were one or two cycles except for MUL and DIV.
The GEM incorporates the Dallas High Speed Micro core which is a fully static CMOS 8051 compatible microcontroller with a new internal architecture designed for high performance. The higher speed operation of the microcontroller core comes not just from increasing the clock frequency, but from a newer, more efficient design of the internal architecture. The major features of the High Speed Micro Core include:
* 4 clocks/machine cycle (8032 = 12) * Wasted cycles removed * Runs DC to 33 Mhz clock rates @ 5V * Single-cycle instruction in 121 ns * Uses less power for equivalent work * Dual data pointer * Optional variable
RAM /peripherals length MOVX to access fast/slow
INSTRUCTION SET SUMMARY Table 3-1 3.2 INSTRUCTION SET SUMMARY
Legends: A Rn direct @Ri rel bit #data #data 16 addr 16 addr 11 - - - - - - - - - - Accumulator Register R7-R0 Internal Register address Internal Register pointed-to by R0 or R1 (except MOVX) 2's complement offset byte direct bit-address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address All instructions in the GEM perform the same functions as their 80C32 counterparts. Their affect on bits, flags, and other status functions are identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops will need to be calculated using the table below. However, counter/timers default to run at the older 12 clocks per increment. Therefore, while software runs at higher speed, timer-based events need no modification to operate as before. Timers can be set to
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INSTRUCTION SET SUMMARY Table 3-1 (cont'd)
OSCILLATOR CYCLES 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 8 12 4 8 4 8 8 12 OSCILLATOR CYCLES 4 4 8 4 12 4 4 8 4 20 20 4 4 8 4 8 8 12 4 4 4 4 4 4 4
INSTRUCTION Arithmetic Instructions: ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data Logical Instructions: ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data Data Transfer Instructions: MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct1, direct2 MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data 16
BYTE 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 3 1 2 1 2 2 3
INSTRUCTION INC A INC Rn INC direct INC @Ri INC DPTR DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV AB DA A XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A
BYTE 1 1 2 1 1 1 1 2 1 1 1 1 1 2 1 2 2 3 1 1 1 1 1 1 1
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3
4 8 4 8 4 8 8 8 8 12 8 12 4 8 8 12
MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri
1 1 1 1 1 1 2 2 1 2 1 1
12 12 8-36 8-36 8-36 8-36 8 8 4 8 4 4
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INSTRUCTION SET SUMMARY Table 3-1 (cont'd)
Bit Manipulation Instructions: CLR C CLR bit SETB C SETB bit CPL C CPL bit Program Branching Instructions: ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JMP @A+DPTR JZ rel JNZ rel DJNZ Rn, rel DJNZ direct, rel
1 2 1 2 1 2
4 8 4 8 4 8
ANL C, bit ANL C, bit ORL C, bit ORL C, bit MOV C, bit MOV bit, C
2 2 2 2 2 2
8 8 8 8 8 8
2 3 1 1 2 3 2 1 2 2 2 3
12 16 16 16 12 16 12 12 12 12 12 16
CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @ Ri, #data, rel NOP JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel
3 3 3 3 1 2 2 3 3 3
16 16 16 16 4 12 12 16 16 16
The Table above shows the speed for each class of instruction. Note that many of the instructions have multiple opcodes. There are 255 opcodes for 111 instructions. Of the 255 opcodes, 159 are three times faster than the original 80C32. While a system than emphasizes those instructions will see the most improvement, the large total number that receive a three to one improvement assure a dramatic speed increase for any system. The speed improvement summary is provided below.
3.4 INSTRUCTION SET ADDITIONAL REFERENCES
The user should refer to the Dallas High Speed Micro User's Guide for a complete description of the instruction set including its address modes, coding, and timing for the GEM.
3.5
RESET
The High-Speed Micro has three ways of entering a reset state:
3.3
SPEED IMPROVEMENT
The following table summarizes the speed improvement of the High Speed Micro core over a standard 12 clock / machine cycle 8052 device. #Opcodes 159 51 43 2 255 Speed Improvement 3.0 x 1.5 x 2.0 x 2.4 x Average: 2.5
* Power-On / Fail Reset * Watchdog Timer Reset * External Reset
The operation of the CPU timing and states during a reset are documented in the Dallas High Speed Micro User's Guide under the "Reset Conditions" section. The Watchdog Timer reset is documented in the Watchdog Timer section of the Dallas High Speed Micro User's Guide. The operation of the Power-On / Fail reset is described in the Power Management section of this document.
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3.6
INTERRUPT CONTROL
neously, the hardware-determined precedence given below determines which is a acted upon. Except for the PFI, all interrupts that are new to the 8051 family have a lower natural priority than the originals.
The GEM provides 16 sources of interrupt with three priority levels. The Power-fail Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user selectable priorities: high and low. If two interrupts that have the same priority occur simulta-
INTERRUPT PRIORITY Table 3-2
NAME PFI INT0 TF0 INT1 TF1 SCON0 TF2 AMI 2WI ADI MSI KBI PBI KDI WDI DKI DESCRIPTION Power Fail Interrupt External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 TI0 or RI0 from Serial Port 0 Timer 2 Activity Monitor Interrupt 2-Wire Serial Port A/D End of Conversion Mouse Serial I/O Keyboard Buffer Input Power Mgmt. Buffer Input Key Detect Input WatchDog Periodic Interrupt Detached Keyboard Input VECTOR 33h 03h 0Bh 13h 1Bh 23h 2Bh 3Bh 43h 4Bh 53h 5Bh 63h 6Bh 73h 7Bh NATURAL PRIORITY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8051/DALLAS DALLAS 8051 8051 8051 8051 8051 8051 DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS
INTERRUPT CONTROL SUMMARY Table 3-3
INTERRUPT SOURCE Power Fail External 0 Timer 0 External 1 Timer 1 Serial Port 0 Timer 2 Activity monitor FLAG(S) PFI IE0 TF0 IE1 TF1 RI0,TI0 TF2 AMF7-0 FLAG LOC. WDCON.4 TCON.1 TCON.5 TCON.3 TCON.7 SCON0.0/ SCON0.1 T2CON.7 AMF.7-0 ENABLE EPFI EX0 ET0 EX1 ET1 ES0 ET2 EAM ENABLE LOC. WDCON.5 IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 IE.6 PRIORITY N/A PX0 PT0 PX1 PT1 PS0 PT2 PAM PRIORITY LOC. N/A IP.0 IP.1 IP.2 IP.3 IP.4 IP.5 IP.6
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INTERRUPT CONTROL SUMMARY Table 3-3 (cont'd)
INTERRUPT SOURCE 2-Wire Serial Port A/D End of Conv. Mouse Serial I/O FLAG(S) 2WIF EOC MSBI, MSTXI, MSRXI KIBF PIBF KDF7-0 WDIF DKBI, DKTXI, DKRXI FLAG LOC. 2WCON.4 ADCON1.6 MSCON.2 MSCON.1 MSCON.0 KBSTAT.1 PMSTAT.1 KDF.7-0 WDCON.3 DKCON.2 DKCON.1 DKCON.0 ENABLE E2W EAD EMS ENABLE LOC. EIE.0 EIE.1 EIE.2 PRIORITY P2W PAD PMS PRIORITY LOC. EIP.0 EIP.1 EIP.2
Keyboard Buffer Power Mgmt. Buffer Key Detect Input WatchDog periodic Detached Keyboard
EKB EPB EKD EWDI EDK
EIE.3 EIE.4 EIE.5 EIE.6 EIE.7
PKB PPB PKD PWDI PDK
EIP.3 EIP.4 EIP.5 EIP.6 EIP.7
A complete description of the interrupt structure of the microcontroller core including operation of the priority scheme and acknowledgment operation is contained in the Dallas High Speed Micro User's Guide.
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4.0 4.1
MEMORY RESOURCES OVERVIEW
The GEM contains the following memory resources and features:
SRAM is between 0000h and 00FFh. Any MOVX instruction that uses this area will go to the on-chip RAM while enabled. MOVX addresses greater than 256 automatically go to external memory through Ports 0 & 2. When disabled, the 256 bytes of memory area is transparent to the system memory map. Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 & 2. This also is the default condition. This default allows the GEM to drop into an existing system that uses these addresses for other hardware and still have full compatibility. The on-chip data area is selected by software using two bits in the Power Management Register at location C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0 (PMR.0). Their operation is described in Table 4-1.
* 256 bytes of on-chip direct (scratchpad) RAM * 256 bytes of on-chip MOVX data RAM * Off-chip program and data memory expansion * Software enable/disable of on-chip data memory
4.2 DATA MEMORY ACCESS
Unlike many 8051 derivatives, the GEM contains on- chip data memory. Although physically on-chip, software accesses this area in the same way off-chip data memory is accessed: via the MOVX instruction. The 256 bytes of SRAM is located between address 0000h and 00FFh. Access to the on-chip data RAM is optional under software control. When enabled by software, the data
DATA MEMORY ACCESS CONTROL Table 4-1
DME1 0 0 1 1 DME0 0 1 0 1 DATA MEMORY ADDRESS 0000h - FFFFh 0000h - 00FFh 0100h - FFFFh Reserved 0000h - 00FFh 0100h - FFFBh FFFCh FFFDh - FFFFh MEMORY FUNCTION External Data Memory (Default condition) Internal SRAM Data Memory External Data Memory Reserved Internal SRAM Data Memory Reserved - no external access Read access to the status of lock bits Reserved - no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the programmed status of the security lock bits LB3-LB1. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed. These status bits allow software to verify that the part has been locked before running if desired. The bits are read only.
4.2.1
Stretch Memory Cycle
The GEM allows software to adjust the speed of off-chip data memory access. The micro is capable of performing the MOVX in as little as two instruction cycles. The on-chip SRAM uses this speed and any MOVX instruction directed internally uses two cycles. However, the time can be stretched for interface to external devices. This allows access to both fast memory and slow memory or peripherals with no glue logic. Even in high- speed systems, it may not be necessary or desirable to
perform off-chip data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as LCDs or UARTs that are slow. Operation of the Stretch MOVX function is fully documented in the Dallas High Speed Micro User's Guide.
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4.2.2
Dual Data Pointer
A second data pointer register (DPTR 1) is incorporated into the GEM in addition to the standard one in the 8051. This feature allows faster execution of many operations involving data memory access, such as block moves. Operation of the dual data pointer function is fully documented in the Dallas High Speed Micro User's Guide.
standard 80C52 compatible device. A full description of this memory along with the instructions that access it is contained in the Dallas High Speed Micro User's Guide.
4.5
SPECIAL FUNCTION REGISTERS
4.3
EXTERNAL MEMORY INTERFACE
Interface techniques for interfacing external memory as program or data storage to the GEM via Ports 0 and 2 are described in the Dallas High Speed Micro User's Guide.
4.4
DIRECT (SCRATCHPAD) RAM ACCESS
Special Function Registers (SFRs) control most special features of the GEM. This allows the GEM to have many new features but use the same instruction set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is the only change needed to access the new function. The GEM duplicates the SFRs contained in the standard 80C52. Table 4-2 is a summary of the values loaded into the GEM's SFR's on reset. Table 4-3 is a summary of all of the SFR's and the control bits they contain.
The GEM incorporates a full 256 bytes of direct RAM. This RAM is accessed in a manner identical to that of a
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SPECIAL FUNCTION REGISTER RESET VALUES Table 4-2 * New functions are in bold
F8h F0h E8h E0h
EIP 00000000 B 00000000 EIE 00000000 ACC 00000000 WDCON MSDAT 00000000 DKDAT 00000000 T2MOD 11111100 MSCON 00000000 DKCON 00000000 RCAP2L 00000000 RCAP2H 00000000 PORT7 11111111 TL2 00000000 PMR 010X0000 IP 10000000 PORT3 11111111 IE 00000000 PORT2 11111111 SCON0 00000000 PORT1 11111111 TCON 00000000 PORT0 11111111 SBUF0 00000000 EXIF 0000XXX0 TMOD 00000000 SP 00000111 2WSADR 00000000 AME 00000000 TL0 00000000 DPL 00000000 2WDAT 00000000 AMQ 00000000 TL1 00000000 DPH 00000000 SADDR0 00000000 SADEN0 00000000 ADCON1 00000000 ADCON2 00000000 PORT6 11111111 ADMSB 00000000 PORT5 11111111 PORT4 11111111 2WFS 00000000 AMP 00000000 TH0 00000000 DPL1 00000000 PORT9 11111111 PORT8 11111111 PW23CON 00000000 PW23CS 00000000 PW01CON 00000000 PW01CS 00000000 TH2 00000000 STATUS 00000000 PMSTAT XXXXXX00 ADLSB 00000000 KBSTAT XXXXXX00 KDE 00000000 2WCON 00000000 AMF 00000000 TH1 00000000 DPH1 00000000 CKCON 00000001 DPS 00000000 PCON 00110000 PMDIN XXXXXXXX WINHI 00000000 KBDIN XXXXXXXX KDF 00000000 2WSTAT1 00000000 2WSTAT2 00000000 TA 11111111 PMDOUT XXXXXXXX WINLO 00000000 KBDOUT XXXXXXXX PWM2 00000000 PW2FG 00000000 PWM0 00000000 PW0FG 00000000 PWM3 00000000 PW3FG 00000000 PWM1 00000000 PW1FG 00000000
FFh F7h EFh E7h DFh D7h CFh C7h BFh B7h AFh A7h 9Fh 97h 8Fh 87h
D8h 0X0X0XX0 D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h
PSW 00000000 T2CON 00000000
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SPECIAL FUNCTION REGISTER LOCATIONS Table 4-3 * New functions are in bold
REGISTER PORT0 SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON PORT1 EXIF AME AMQ AMP AMF SCON0 SBUF0 2WSADR 2WDAT 2WFS 2WCON 2WSTAT1 2WSTAT2 PORT2 PORT4 KDE KDF IE SADDR0 2WEN BER BB P2.7 P4.7 KDE7 KDF7 EA STA ARL ADM P2.6 P4.6 KDE6 KDF6 EAM STO RSTO X/R P2.5 P4.5 KDE5 KDF5 ET2 2WIF TXI ACKS P2.4 P4.4 KDE4 KDF4 ES0 BMM RXI - P2.3 P4.3 KDE3 KDF3 ET1 ANAK TSTA - P2.2 P4.2 KDE2 KDF2 EX1 - RSTA - P2.1 P4.1 KDE1 KDF1 ET0 - - - P2.0 P4.0 KDE0 KDF0 EX0 WD1 P1.7 - AME7 AMQ7 AMP7 AMF7 SM0/FE SB7 SLA6 WD0 P1.6 - AME6 AMQ6 AMP6 AMF6 SM1 SB6 SLA5 T2M P1.5 - AME5 AMQ5 AMP5 AMF5 SM2 SB5 SLA4 T1M P1.4 - AME4 AMQ4 AMP4 AMF4 REN SB4 SLA3 T0M P1.3 XT/RG AME3 AMQ3 AMP3 AMF3 TB8 SB3 SLA2 MD2 P1.2 RGMD AME2 AMQ2 AMP2 AMF2 RB8 SB2 SLA1 MD1 P1.1 RGSL AME1 AMQ1 AMP1 AMF1 TI0 SB1 SLA0 MD0 P1.0 BGS AME0 AMQ0 AMP0 AMF0 RI0 SB0 - 0 SMOD TF1 GATE 0 SMOD0 TR1 C/T 0 - TF0 M1 0 - TR0 M0 0 GF1 IE1 GATE 0 GF0 IT1 C/T 0 STOP IE0 M1 SEL IDLE IT0 M0 BIT 7 P0.7 BIT 6 P0.6 BIT 5 P0.5 BIT 4 P0.4 BIT 3 P0.3 BIT 2 P0.2 BIT 1 P0.1 BIT 0 P0.0 ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 92h 93h 94h 95h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A4h A5h A6h A8h A9h
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SPECIAL FUNCTION REGISTER LOCATIONS Table 4-3 (cont'd) * New functions are in bold
REGISTER PORT5 KBSTAT KBDIN KBDOUT PORT3 ADCON1 ADCON2 ADMSB ADLSB WINHI WINLO IP SADEN0 PORT6 PMSTAT PMDIN PMDOUT PMR STATUS TA T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PSW DKDAT DKCON PORT7 CY DKD7 - P7.7 AC DKD6 DKEN P7.6 F0 DKD5 DKWU P7.5 RS1 DKD4 DKFE P7.4 RS0 DKD3 DKPE P7.3 OV DKD2 DKBI P7.2 FL DKD1 DKTXI P7.1 P DKD0 DKRXI P7.0 TF2 - EXF2 - RCLK - TCLK - EXEN2 - TR2 - C/T2 T2OE CP/ RL2 DCEN CD1 PIP CD0 HIP SWB LIP - XTUP XTOFF - ALEOFF - DME1 SPTA0 DME0 SPRA0 P6.7 PST7 P6.6 PST6 P6.5 PST5 P6.4 PST4 P6.3 PC/D P6.2 PST2 P6.1 PIBF P6.0 POBF - PAM PT2 PS0 PT1 PX1 PT0 PX0 P3.7 STRT/ BSY OUTCF ADC9/ 0 ADC7 P3.6 EOC MUX2 ADC8/ 0 ADC6 P3.5 CONT/ SS MUX1 ADC7/ 0 ADC5 P3.4 ADEX MUX0 ADC6/ 0 ADC4 P3.3 WCQ APS3 ADC5/ 0 ADC3 P3.2 WCM APS2 ADC4/ 0 ADC2 P3.1 ADON APS1 ADC3/ ADC9 ADC1 P3.0 WCIO APS0 ADC2/ ADC8 ADC0 BIT 7 P5.7 KST7 BIT 6 P5.6 KST6 BIT 5 P5.5 KST5 BIT 4 P5.4 KST4 BIT 3 P5.3 KC/D BIT 2 P5.2 KST2 BIT 1 P5.1 KIBF BIT 0 P5.0 KOBF ADDRESS ACh ADh AEh AFh B0h B2h B3h B4h B5h B6h B7h B8h B9h BCh BDh BEh BFh C4h C5h C7h C8h C9h CAh CBh CCh CDh D0h D1h D2h D4h
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SPECIAL FUNCTION REGISTER LOCATIONS Table 4-3 (cont'd) * New functions are in bold
REGISTER PW01CS PW0FG PW1FG WDCON MSDAT MSCON PW01CON PWM0 PWM1 ACC PORT8 PW23CS PW2FG PW3FG EIE PORT9 PW23CON PWM2 PWM3 B EIP PDK PWDI PKD PPB PKB PMS PAD P2W EDK P9.7 PW2 F EWDI P9.6 PW2 DC EKD P9.5 PW2 OE EPB P9.4 PW2 T/C EKB P9.3 PW3 F EMS P9.2 PW3 DC EAD P9.1 PW3 OE E2W P9.0 PW3 T/C P8.7 PW2S2 P8.6 PW2S1 P8.5 PW2S0 P8.4 PW2EN P8.3 PW3S2 P8.2 PW3S1 P8.1 PW3S0 P8.0 PW3EN SMOD MSD7 - PW0 F POR MSD6 MSEN PW0 DC EPFI MSD5 MSWU PW0 OE PFI MSD4 MSFE PW0 T/C WDIF MSD3 MSPE PW1 F WTRF MSD2 MSBI PW1 DC EWT MSD1 MSTXI PW1 OE RWT MSD0 MSRXI PW1 T/C BIT 7 PW0S2 BIT 6 PW0S1 BIT 5 PW0S0 BIT 4 PW0EN BIT 3 PW1S2 BIT 2 PW1S1 BIT 1 PW1S0 BIT 0 PW1EN ADDRESS D5h D6h D7h D8h D9h DAh DDh DEh DFh E0h E4h E5h E6h E7h E8h ECh EDh EEh EFh F0h F8h
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5.0
CORE I/O RESOURCES
5.3
WATCHDOG TIMER
The GEM incorporates a full complement of the 80C52-compatible I/O resources as well as a number of specialized I/O resources which are associated with the Dallas High-Speed micro core. These features are described in this section.
To prevent software from losing control, the GEM includes a programmable Watchdog Timer. The Watchdog is a free running timer that sets a flag if allowed to reach a preselected time-out. It can be (re)started by software. A typical application is to select the flag as a reset source. When the Watchdog times out, it sets its flag which generates reset. Software must restart the timer before it reaches its time-out or the processor is reset. Software can select one of four time-out values. Then, it restarts the timer and enables the reset function. After enabling the reset function, software must then restart the timer before its expiration or hardware will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected by a "Timed Access" circuit. This prevents errant software from accidentally clearing the Watchdog. Time-out values are precise since they are a function of the crystal frequency as shown below in Table 5-1. For reference, the time periods at 25 MHz also are shown. The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source. The interrupt is independent of the reset. A common use of the interrupt is during debug, to show developers where the Watchdog times out. This indicates where Watchdog must be restarted by software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor. The Watchdog function is controlled by the Clock Control (CKCON - 8Eh), Watchdog Control (WDCON - D8h), and Extended Interrupt Enable (EIE - E8h) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively and they select the Watchdog time-out period as shown in Table 5-1. A complete operational description for the Watchdog Timer is given in the Dallas High Speed Micro User's Guide.
5.1
PROGRAMMABLE TIMERS
Three programmable timers are included which are compatible with the standard 80C52. All of the functions are duplicated and all of the control bits and registers associated with these functions are in their standard locations. The standard operating modes of each timer are fully described in the Dallas High Speed Micro User's Guide. There is one important difference between the Dallas High Speed Micro Core and the 8051 regarding timers. The original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The High Speed Micro architecture normally uses 4 clocks per machine cycle. However, in the area of timers and serial port, the High Speed Micro will default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as baud rates to operate properly. If an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4 clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the relevant CKCON bit is a logic 1, the High Speed Micro core uses 4 clocks per cycle to generate timer speeds. When the bit is a 0, the High Speed Micro core uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.
5.2
SERIAL PORT
The GEM provides a serial port (UART) that is identical to the 80C52. The duplicate serial port implemented as described in the Dallas High Speed Micro User's Guide is not present. Operation of the original serial port, which is called Serial Port 0, is fully described in the User's Guide.
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WATCHDOG TIMER INTERRUPT / RESET TIMEOUT VALUES Table 5-1
WD1 0 0 1 1 WD0 0 1 0 1 INTERRUPT TIME-OUT 217 clocks 220 clocks 223 clocks 226 clocks TIME (25 MHz) 5.243 ms 41.94 ms 335.54 ms 2684.35 ms Port 4: Port 5: Port 6: Port 7: Port 8: Port 9: RESET TIME-OUT 217 + 512 clocks 220 + 512 clocks 223 + 512 clocks 226 + 512 clocks 0A4H 0ACH 0BCH 0D4H 0E4H 0ECH TIME (25 MHz) 5.263 ms 41.96 ms 335.56 ms 2684.38 ms
5.4
PARALLEL I/O PORTS
The GEM incorporates the original four pseudo-bi- directional parallel I/O ports found in the 80C52: Ports 0, 1, 2 and 3. All of these ports operate logically as documented in the Dallas High Speed Micro User's Guide. All of the Port 0, 1, 2, and 3 pins exhibit the same electrical characteristics as documented in the user's guide except for P1.7 - P1.2 which are open-drain pins. In addition to these basic ports, the GEM adds an additional six 8-bit ports. All of these additional ports incorporate the same logical I/O structure as the original four, Ports 0 through 3. Therefore, they are programmed the same as Ports 0-3. The SFR addresses for the new ports are as follows:
5.4.1
Alternate Pin Function Summary
A number of port pins on the GEM offer an optional alternate function. These functions are individually selectable; i.e. each pin can be programmed for use as a general purpose I/O or to serve the alternate function. In order to use the alternate function, the associated port latch must be programmed to a 1. The alternate functions are summarized in Table 5-2 below.
PORT PIN ALTERNATE FUNCTIONS Table 5-2
PIN(S) P0.7 - P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 - P2.0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 ALTERNATE PIN(S) AD7 - AD0 DKDIO DKCLK MSDIO MSCLK SDA SCL T2EX T2 A15 - A8 RD WR T1 T0 INT1 INT0 TXD0 ALTERNATE FUNCTION(S) Mux. addr. / data bus Detached Keyboard port data input/output Detached Keyboard port data clock Mouse serial port data input / output Mouse serial port clock 2-Wire serial port data input / output 2-Wire serial port clock Timer 2 capture / reload input Timer 2 output pulse Address bus outputs Read strobe output Write strobe output Timer 1 input Timer 0 input External interrupt 1 input (active low) External interrupt 0 input (active low) UART Transmit
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DS80CH10
PORT PIN ALTERNATE FUNCTIONS Table 5-2 (cont'd)
P3.0 P4.7 - P4.0 P5.7 - P5.0 P6.7 P6.6 P6.5 - P6.4 P6.3 - P6.0 P7.7 - P7.0 P8.7 - P8.0 P9.7 - P9.0 RXD0 KSI.7 - KSI.0 AI.7 - AI.0 SOC - PWI.1 - PWI.0 PWO.3 - PWO.0 AMI.7 - AMI.0 LED.7 -LED.0 KSO.7 - KSO.0 KSO.15 - KSO.8 UART Receive Keyboard scan inputs A/D analog inputs A/D start of conversion input (None) PWM channels 1 and 0 inputs PWM channels 3, 2, 1, and 0 outputs Activity monitor inputs / LED drive outputs Keyboard Scan Outputs Keyboard Scan Outputs
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6.0 6.1
2-WIRE SERIAL INTERFACE INTRODUCTION
* Serial clock synchronization allows devices with different bit rates to communicate via the same serial bus.
The GEM provides an industry standard 2-wire serial interface for processor-processor and processor- slave bi-directional communication. The major features of this bus include:
* Devices can be added to or removed from the bus
without affecting any other circuit on the bus. The on-chip 2-wire port supports four modes of operation: Master transmitter, Master receiver, Slave transmitter, Slave receiver. Byte-oriented data transport, clock generation, address recognition, and bus control arbitration are all performed by the hardware. Double- buffering is provided on receive, allowing a full word time to service the port during multiple byte data transfers. Figure 6-1 is a block diagram which illustrates the hardware of the 2-wire serial port.
* Only two bus lines are required: * Each
a serial clock line (SCL) and a serial data line (SDA). device connected to the bus is software addressable by a unique address. ter-receiver.
* Masters can operate as Master-transmitter or Mas* Multiple master capability via collision detection and
arbitration to prevent data corruption if two or more masters simultaneously initiate a data transfer.
2-WIRE SERIAL PORT BLOCK DIAGRAM Figure 6-1
GEM INTERNAL DATA BUS
R/W 09AH
EN
2WSADR - ADDRESS REGISTER
R/W 09EH RD 09FH
2WSTAT1 - STATUS REGISTER 2WSTAT2 - STATUS EN REGISTER
EN
ADDRESS COMPARE
RD 09BH
EN
2WDAT - RECEIVE DATA BUFFER
SDA PIN R/W 09DH 2WCON - CONTROL REGISTER
DOUT
EN
WR 09BH
EN
SHIFT REGISTER
DIN
ACK
MSB
LSB
tMCLK R/W 09CH
2WFS - FREQUENCY SELECT EN
TIMING & CONTROL LOGIC
ARBITRATION LOGIC
SCL PIN
DIVIDE BY 8 PRESCALE
DIVIDE BY RELOAD VALUE SERIAL CLOCK GEN.
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6.2
REGISTER DESCRIPTION
The microcontroller interface to the 2-wire serial port consists of six Special Function Registers (SFR's)
which are documented below. None of these registers are bit addressable.
6.2.1
2WFS - 2-Wire Frequency Select Register
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2WFS; SFR ADDR.=09CH BIT 7
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The 2-Wire Frequency Select Register is an 8-bit read/ write register which is used by the microcontroller to set the 2-Wire clock data rate. The value programmed into this register sets the reload value for an 8-bit auto-reload timer, which is clocked by the CPU machine clock (tMCLK) through a divide-by-8 prescaler. The CPU machine clock period is the oscillator clock period (tCLK) multiplied times 4, 64, or 1024 as determined by the pro-
gramming of the system clock divider bits (CD1, CD0) in the PMR register. The 2-wire clock frequency can therefore be calculated using the following formula: f2W = fMCLK/ [(8 * Reload) +2]; t2WCL = 1 / f2W where Reload=(2WFS register value) for 2-255, and Reload=(256) for 2WFS value=0 Reload=(1) is invalid
6.2.2
2WDAT - 2-Wire Data I/O Registers
2WDAT; SFR ADDR.=09BH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The Data I/O Registers consist of the transmit buffer and the receive buffer. Both registers are located at SFR address 9BH. A write to this location results in a write to the transmit buffer register, while a read results in a read from the receive buffer register.
During transmit, a write to this location results in 8-bits of data being transmitted on the 2-wire bus when either master or slave transmit mode is established. When master or slave receive mode is in effect, 8-bits are shifted in via the shift register and immediately transferred to the receive buffer. All data is shifted MSB first.
6.2.3
2WSADR - 2-Wire Slave Address Register
2WSADR; SFR ADDR.=09AH BIT 7 SLA6 BIT 6 SLA5 BIT 5 SLA4 BIT 4 SLA3 BIT 3 SLA2 BIT 2 SLA1 BIT 1 SLA0 BIT 0 -
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset
SLA6-0 - Slave Address bits
SLA6-0 are used to establish the 7-bit address recognized by the 2-wire port when it is operating in slave
mode. The 7-bit slave address is MSB justified when it is read or written by the firmware. When read, bit 0 is always returned as a 0.
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6.2.4
2WCON - 2-Wire Control Register
2WCON; SFR ADDR.=09DH BIT 7 2WEN BIT 6 STA BIT 5 STO BIT 4 2WIF BIT 3 BMM BIT 2 ANAK BIT 1 - BIT 0 -
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The 2-Wire Control Register bits <7:2> can be read or written by the microcontroller. Bit <1,0> are reserved for future use and should be ignored by the firmware. Refer to the bit description below for specific set/reset conditions.
STO - 2-Wire Stop
If STO=1 when the hardware has control of the bus as a master, a stop condition is issued on the bus after the transmit or receive of any byte currently in progress is completed. When the STOP condition is transmitted on the bus, the STO flag will automatically be cleared to 0. If both STA and STO are set in the master mode, the STOP condition will be generated first. After the STO bit is cleared a START will be generated. When STO=0, no STOP condition is generated.
2WEN - 2-Wire Enable
When 0, the 2-Wire port is disabled. SCL and SDA pins are off (high-Z), no internal processing or bus monitoring is performed, and all internal registers are reset. If SDA and SCL are left connected to the 2-wire bus with 2WEN = 0, the serial interface hardware will not generate or respond to activity on the bus. Also when 2WEN = 0, SDA and SCL can be used as open drain general purpose I/O port pins (P1.3 and P1.2, respectively) and are accessible via the port 1 latch register. When 2WEN = 1, the 2-Wire interface is enabled. P1.3 and P1.2 port latches must be set to 1 in order for the serial interface to operate.
2WIF - 2-Wire Interrupt Flag
2WIF serves as the main interrupt flag bit for the 2-Wire port. If BMM = 0, (in 2WCON register) 2WIF is set to 1 whenever operating as a master or as an addressed slave and one or more of the following interrupt source bits in 2-Wire Status Register (2WSTAT1) are set (active): BER, ARL, RSTO, TXI, RXI, TSTA. When BMM=1, the 2WIF flag will be set when any of the following source bits are set: BER, ARL, RSTO, TXI, RXI, TSTA, RSTA. Note that in this case RSTA also generates an interrupt. Regardless of the state of the BMM bit, the 2WIF bit will be cleared when all of its source bits are cleared.
STA - 2-Wire Start
The firmware can generate a start or a repeat start condition by setting STA=1 with STO=0. The hardware will then wait for the bus to be free, and generate a start condition on the bus in an attempt to gain control of the bus as a master. If the start condition fails, or if the port loses arbitration, the hardware will repeat its attempt until it is successful as long as STA=1. When the START condition is successfully asserted, the TSTA flag will be set. If the STA bit remains set while in the master mode throughout the time that a byte is being transmitted or received, then a repeat START condition will be asserted at the end of the byte transfer. Again, TSTA will be set when the repeat start is successfully asserted. If STA is cleared to 0, no further START or repeat START will be attempted.
BMM - Bus Monitor Mode
When BMM=0, the 2-wire port will only generate interrupts if it is operating as a master or being addressed as a slave. If bus monitoring is enabled with BMM = 1, the port can "listen" to (receive) packets sent from external masters to external slaves on the 2-wire bus. In this mode the port will generate an interrupt for every action on the bus even when it is not operating as a master or being addressed as a slave. As a result, when a transfer takes place between an external master and slave, the port will be notified of a transmitted START condition, will
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receive the subsequent address and data bytes on the bus, and will finally be notified of a transmitted STOP condition.
ANAK - Assert Negative AcKnowledge
If ANAK is set to 1, a negative acknowledge bit will be returned on the next serial word received. If it is 0, a positive acknowledge bit will be returned.
6.2.5
2WSTAT1 - 2-Wire Status Register 1
2WSTAT1; SFR ADDR.=09EH BIT 7 BER BIT 6 ARL BIT 5 RSTO BIT 4 TXI BIT 3 RXI BIT 2 TSTA BIT 1 RSTA BIT 0 -
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset
BER - Bus ERror
BER is a status flag which will be set to 1 in the event that a stop condition is received with greater or less than 8 bits shifted. BER is cleared when the 2WSTAT1 register is read.
from the slave. The TXI flag must be cleared by firmware before any data written to the transmit buffer can be transmitted, or after setting STA or STO bits. If TXI is not cleared the 2-Wire bus will be held low until it is cleared.
RXI - Receive Interrupt Flag
During receive, RXI is set when the receive buffer register is loaded with a byte of data which has just been shifted in. The RXI flag must be cleared by firmware before the next byte of data can be shifted in.
ARL - ARbitration Loss
This bit is set to a 1 when the 2-wire hardware loses arbitration to another master on the bus. ARL is cleared when the 2WSTAT1 register is read. If arbitration is lost, the bus will enter the not-addressed slave state and will receive data beginning with the byte where arbitration was lost.
TSTA - Transmitted Start
TSTA will be set to a 1 when a START condition has been successfully transmitted on the 2-Wire bus. The TSTA must be cleared by firmware before the transmission can begin if not the 2-Wire bus will be held low until it is cleared.
RSTO - Received STOp
RSTO is set when a valid stop condition is received when operating as a slave. RSTO is cleared when the 2WSTAT1 register is read.
RSTA - Received Start
RSTA = 1 when a START condition has been detected on the bus. RSTA will be cleared to 0 when the 2WSTAT1 register is read. If BMM = 0, RSTA does not affect the setting of 2WIF. If BMM = 1, then RSTA will set 2WIF.
TXI - Transmit Interrupt Flag
During transmit, TXI is set when a byte has been completely shifted out and the acknowledge bit received
6.2.6
2WSTAT2 - 2-Wire Status Register 2
2WSTAT2; SFR ADDR.=09FH BIT 7 BB BIT 6 ADM BIT 5 X/R BIT 4 ACKS BIT 3 - BIT 2 - BIT 1 - BIT 0 -
Read/Write Access: Read Only. Initialization: 00H on any type of reset
(or transmission) of a START and will be reset at detection (or transmission) of STOP.
BB - Bus Busy
This bit is used to signal the microcontroller that the 2-Wire bus is currently in use either by another master or by the microcontroller itself. It will be set at detection
ADM - ADdress Match
This bit is set to a 1 when an address has been received which either matches the value stored in the Address
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Register or is the General Call address (00H). The received address is available in the receive buffer. RXI will also be set when an address is received. ADM will stay set until a STOP or repeat START is generated.
X/R - Xmit / Receive
When X/R is set to 1, the 2-Wire port has entered transmit mode. When X/R is cleared to 0, receive mode operation is signaled.
2. Data transfer from a slave transmitter to a master receiver. The first byte is again the slave address, this time with the R/W bit set to 1 (read). The slave returns an acknowledge bit for this first byte. Next, the slave will transmit the pre-determined number of data bytes to the master. The master returns an acknowledge bit after each byte is received for all but the last byte. At the end of the last byte, the master returns a negative acknowledge. This action signals the slave to stop transmitting. In both types of transfers, the master generates all of the serial clock pulses as well as the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the 2-wire bus will not be released in this case. The on-chip 2-wire port supports four modes of operation: Master transmitter, Master receiver, Slave transmitter, and Slave Receiver. Operating the port in these four modes is described in detail below. Following any type of reset, the 2-Wire port will be configured in slave receive mode.
ACKS - ACKnowledge Status
ACKS reflects the state of the acknowledge bit at the end of a byte transfer on the bus. If a positive acknowledge was detected, ACKS will be set to 1. If a negative acknowledge is detected, ACKS will be cleared to 0.
6.3
OPERATIONAL DESCRIPTION
A typical 2-Wire bus configuration is shown in Figure 6-2 and Figure 6-3 illustrates how a data transfer is performed. Two types of data transfers are possible on the 2-wire bus: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address with the R/W bit set to 0 (write), followed by a number of data bytes. The slave returns an acknowledge bit after each received byte.
TYPICAL 2-WIRE BUS CONFIGURATION Figure 6-2
VCC RP RP
SDA SCL
P1.3 / SDA
P1.2 / SCL DS1307 SERIAL RTC DS1621 DIGITAL THERMOMETER 8-BIT uC w/ 2-WIRE I/F
GEM
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DATA TRANSFER ON THE 2-WIRE BUS Figure 6-3
R/W DIR. BIT SDA MSB SLAVE ADDRESS ACK FROM RECEIVER 7 8 9 ACK 1 2 ACK FROM RECEIVER 3, 8 9 ACK STOP OR REPEAT START CONDITION NAK FROM RECEIVER CONDITION STOP REPEAT START
SCL
1
2
3, 6
START CONDITION
CLOCK LINE HELD LOW XMIT: UNTIL SHIFT REG. LOAD RECEIVE: REC. BUF. FULL
REPEATED FOR MULTI-BYTE XFERS
6.3.1
Master Transmit
In the master transmit mode, the GEM is configured as a master device and transfers a number of data bytes to a slave receiver. A timing diagram in Figure 6-4 illustrates the interaction between the firmware and hardware with respect to events on the 2-Wire bus. The master transmit mode can now be entered by setting the STA bit. The 2-Wire port logic will test the 2-Wire bus and generate a start condition as soon as the bus is free. As soon as the start condition is trans-
mitted, the TSTA flag will be set. In addition, the X/R bit will be set to a 1, indicating transmit operation is in effect.
In response to TSTA being set, the firmware can now write to the transmit buffer an initial byte for the message as follows:
7
6
5
4
3
2
1
0 0
7-bit Slave Address
MASTER TRANSMIT OPERATION TIMING Figure 6-4
SDA/SCL
STA BIT
X/R BIT
TSTA BIT
XMIT BUF WRITE TXI BIT
ACKS BIT STO BIT
ACTION TAKEN BY FIRMWARE
ALTERNATIVE CONDITION
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CCC CCC ECCCC CCC E C CCCCCCEEECCCCCCCCEEECC CCCCCEEECCCCCCCCEEECC C CCC ECCCC CCC E
S SLAVE ADDR. R/W 0 A DATA A DATA A/A Sr SLAVE ADDR. R/W A DATA A/A P 0
C C C
MASTER TO SLAVE XFER
SLAVE TO MASTER XFER
A = ACKNOWLEDGE (SDA LOW) A = NEGATIVE ACKNOWLEDGE (SDA HIGH) S = START CONDITION Sr = REPEAT START CONDITION P = STOP CONDITION
DS80CH10
The desired slave address is placed in the most significant 7-bits and a "0" in the least significant bit (direction bit position) indicating a write operation. Transmission of this byte will begin immediately upon writing the byte. After writing the byte, the firmware must clear the TSTA and STA bits. The firmware can now exit the interrupt service routine or otherwise wait until the initial byte is transmitted. When the slave address and direction bit have been sent and a positive acknowledge bit received back from the slave, the TXI bit will be set, indicating the transmission is complete. At this point the firmware can load the first data byte into the transmit buffer and then clear the TXI bit. Because transmit mode is now in effect, clearing TXI causes the hardware to load the contents of the buffer into the shift register. Therefore loading the buffer before clearing TXI will insure that the hardware will not load the previous byte into the shift register and thereby re-transmit it. Subsequent data bytes can be successfully transmitted each time TXI is set by repeating the above procedure. In the event that a negative acknowledge bit is received back from the slave after sending any bytes, the transmission can be aborted by issuing a repeat START or STOP condition as described below. As shown in the diagram, a repeat start condition can be sent following the transmission of a data byte. In this case the firmware should first set STA to a 1 after detecting that the TXI flag is set. Since the port logic has control of the bus, a repeat START condition will be issued immediately, resulting in TSTA being set to 1. The firmware must then reset TSTA, write the next slave address and direction bit (0 = master transmit) to the transmit buffer, and clear TXI to 0. This sequence will insure that the repeat start is sent before the data containing the slave address is transmitted. Finally, the STA bit should be cleared to 0 so that another repeat START will not be sent following the slave address byte. Subsequent data bytes can then be transmitted as described above. When TXI is set after the last byte of data has been transmitted, a STOP condition can be issued by setting the STO bit to a 1. The TXI bit must be cleared at this point by firmware; this action will not cause any additional data to be sent since the port will be in receive mode as a result of setting STO. After the STOP condition is sent, the STO bit will be automatically cleared and X/R will be cleared to 0.
In the Master transmit mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 2-Wire bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and the port logic immediately changes from Master transmit mode to Slave Receive mode. The port logic will continue to output clock pulses on SCL until transmission of the current serial byte is complete. At the completion of the byte, the ARL bit will be set to a 1. The resulting transmitted serial word from the master which won the arbitration will be available in the receive buffer. If arbitration was lost during the transmission of the slave address and the resulting address matches the port's programmed slave address in 2WSADR, then the ADM bit will also be set to 1.
6.3.2
Master Receive
Figure 6-5 illustrates Master Receive operation. In Master Receive mode, the GEM is configured as a master and one or more data bytes are received from a slave device. The transfer is initiated as in the Master Transmit mode, beginning with either a start condition or a repeat start condition, followed by the transmission of the slave address. However, in this case the direction bit should be set to a 1 to signal Master Receive operation. When the acknowledge bit for the slave address is sampled, the TXI bit will be set to a 1 and ACKS bit will reflect the state of the bit returned from the slave. Since the direction bit was set to 1, the X/R bit will be cleared to 0 indicating receive operation is now in effect. The TXI bit must be cleared to 0 by firmware to remove the interrupt condition. No further bytes will be transmitted in the packet since the port logic is in receive mode. If it is desired to return a positive acknowledge bit upon the receipt of subsequent data byte(s), the ANAK bit should be cleared to 0. Upon the receipt of the data byte, the RXI bit will be set at the time the acknowledge bit is transmitted. The firmware should read the incoming byte from the receive buffer register followed by a clear of RXI to 0. Subsequent incoming data bytes are handled in the same manner. After each byte is received and loaded into the receive buffer and the RXI flag cleared, the next byte will begin to be shifted in immediately.
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MASTER RECEIVE OPERATION TIMING Figure 6-5
SDA/SCL
STA BIT
TSTA BIT
X/R BIT
DATA BUF: WRITE READ TXI BIT
RXI BIT
ACKS BIT
ANAK BIT
STO BIT
In response to RXI being set on the next to the last data byte, the ANAK bit can be set so that a negative acknowledge bit is returned to the slave when the last data byte is received. This action signals the slave to stop transmitting bytes and return to receive mode. If there is only one byte to be received from the slave device, the ANAK bit can be set at the time the slave address is transmitted so that the negative acknowledge signal will be transmitted after the reception of the single byte. When the last data byte is received and RXI cleared, the STOP condition can be issued by setting the STO bit to a 1. ANAK can be returned to a 0 at this time to return a positive acknowledge on future received bytes (e.g. received slave address). After the STOP condition is sent the STO bit will be automatically cleared and X/R will remain at 0, indicating the port hardware is still in receive mode.
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CCC CCCC CCC E C CCCCCCCCCCCEEECC CCCCCCCCCCEEECC C CCCC CCC E CCCCCCCCCCCEEECC CC CCCC CCC E
S (Sr) SLAVE ADDR. R/W 1 A DATA A DATA A DATA A P
Arbitration with another master may be lost during the transmission of the slave address as described above in the Master Transmit mode. Once receive operation is in progress in the Master Receive mode, then arbitration loss can only occur while a negative acknowledge is being returned on the bus. In this case arbitration is lost when another master on the bus pulls this signal low. Since this occurs at the end of a serial byte, no further clock pulses are generated. The ARL flag will be set to signal this event.
6.3.3
Slave Receive
Figure 6-6 illustrates the timing for Slave Receive operation. In this mode another master transfers one or more bytes to the GEM which is addressed as a slave device. When the 2-Wire port is initialized following a reset, the GEM's 7-bit slave address is established by program-
DS80CH10
ming the 2WSADR register with the address value left- justified. The ANAK bit should be cleared to 0 to allow a
positive acknowledge bit to be issued when the GEM's slave address is received.
SLAVE RECEIVE OPERATION TIMING Figure 6-6
SDA/SCL
X/R BIT
ADM BIT
RCV BUF. READ
RXI BIT
ACKS BIT
ANAK BIT
RSTO BIT
The transfer is initiated by the external master beginning with either a START or Repeat START condition, followed by the transmission of the GEM's slave address with the direction bit cleared to 0. This byte will be shifted in and loaded into the receive buffer register at the time the acknowledge bit is returned to the master, resulting in RXI being set to 1. In addition, an address match condition will occur as indicated by the ADM flag set to 1. Upon detecting these flags, the firmware should respond by reading the receive buffer in order to determine if the programmed slave address or the general call address was received. Following the read of the buffer, the RXI flag must be cleared. Also at this time the firmware should insure that the 2WIF bit is cleared to 0, so that the interrupt flag will be set in response to subsequent received data byte(s) and STOP condition. Upon the receipt of the first data byte, the RXI bit will be set at the time the acknowledge bit is transmitted. The firmware should read the incoming byte from the receive
CCCCCCCCCCCEEECC CC CCCC CCC E CCC CCCC CCC E C CCCCCCCCCCCEEECC CCCCCCCCCCEEECC C CCCC CCC E
S SLAVE ADDR. R/W A DATA A DATA A DATA A/A P
0
buffer register followed by a clear of RXI to 0. Subsequent incoming data bytes are handled in the same manner. If desired, the ANAK bit can be set to cause a negative acknowledge to be issued upon receipt of the next byte. When the last byte of data has been sent, the bus master will issue a STOP condition, which will result in the RSTO flag set to a 1. At this time, the port hardware returns to the not-addressed slave mode.
6.3.4
Slave Transmit
Figure 6-7 illustrates the timing for Slave Transmit mode operation. In this mode the GEM, addressed as a slave, transfers one or more bytes to the bus master. The transfer is initiated by the external master beginning with either a START or Repeat START condition, followed by the transmission of the GEM's slave address
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with the direction bit set to 1. This byte will be shifted in and loaded into the receive buffer register at the time the acknowledge bit is returned to the master, resulting in
RXI being set to 1. In addition, an address match condition will occur as indicated by the ADM flag set to 1.
SLAVE TRANSMIT OPERATION TIMING Figure 6-7
SDA/SCL
X/R BIT
ADM BIT
DATA BUF: WRITE READ
RXI BIT
TXI BIT
ACKS BIT
RSTO BIT
Upon detecting these flags, the firmware should respond by reading the receive buffer in order to determine if the programmed slave address or the general call address was received. Following the read of the buffer, the RXI flag must be cleared. Also at this time the firmware should insure that the 2WIF bit is cleared to 0, so that the interrupt flag will be set in response to subsequent received data byte(s) and STOP condition. If the programmed slave address was received, the firmware can now send the first data byte by a write to the transmit buffer. After the first data byte is transmitted and the acknowledge bit received, the TXI flag will be set to 1. If the acknowledge bit ACKS is returned as a 1, the next byte can be loaded into the transmit buffer and the TXI bit cleared. Successive bytes can be handled in the same manner. Whenever any data is transmitted from the 2-wire port, the byte actually transferred on the
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CCCCCCCCCCCEEECC CC CCCC CCC E CCCCCCCCCCCEEECC CC CCCC CCC E
S (Sr) SLAVE ADDR. R/W 1 A DATA A DATA A DATA A P
bus will be shifted back in and loaded into the receive buffer. If the acknowledge bit ACKS is returned as a 0 on a transmitted byte, then the master is signaling this as the last data byte in the packet. In this event, the X/R bit will be automatically cleared to 0 and the firmware should not write any more data bytes to the transmit buffer. The TXI bit must be cleared at this point by firmware; this action will not cause any additional data to be sent since the port is now in receive mode. When the last byte of data has been sent, the bus master will issue a STOP condition, which will result in the RSTO bit set to a 1. At this time, the port hardware returns to the not-addressed slave mode.
DS80CH10
6.3.5
Bus Monitor Mode Operation
The bus monitor mode is provided to allow the GEM to "listen" as a third party to conversations between external master and slave devices. This mode can be useful for diagnostic purposes, or to help the system recover from a detected error condition. When the BMM bit is set to 1, bus monitoring is enabled. In this mode the port will generate an interrupt for every action on the bus even when it is not operating as a master or being addressed as a slave. As a result, when a transfer takes place between an external master and slave, the port will be notified of a transmitted START condition, will receive the subsequent address and data bytes on the bus, and will finally be notified of a transmitted STOP condition. If the GEM is receiving a transfer between an external master and an external slave device, the timing is nearly identical to that for Slave Receive operation as shown in Figure 6-6. The exceptions to this timing are summarized as follows: 1) An additional interrupt will be gener-
ated when a Receive START condition is detected as indicated by RSTA = 1. This will inform the firmware of the start of a message and allow it to identify the next byte as an address. 2) A positive acknowledge pulse will never be generated. 3) SCL will never be held low to prevent data in the receive buffer from being overwritten. Other than these differences bytes are received and all other status is flagged as described for Slave Receiver operation. When BMM = 1 and the GEM is operating as a master or is being addressed as a slave, the Master Transmit, Master Receive, Slave Transmit, and Slave Receive modes will all operate exactly as documented above with the exception that RSTA becomes an additional interrupt flag that is set whenever a START condition is detected on the bus. When BMM = 0, bus monitoring is disabled and interrupt flags are only generated when the port is operating as a master or being addressed as a slave device. Transfers between external devices are ignored.
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7.0 7.1
A/D CONVERTER OVERVIEW
A self-contained A/D converter is provided on the GEM. Its major features are summarized below:
* 10-bit resolution * True 9-bit accuracy:
LSB's total error no greater than + 2
variety of applications, the A/D result can be programmed to be presented either as eight msbs and eight lsbs in separate registers, or as a right justified 10-bit result with the most significant two bits of the result right-justified in the most significant byte. An A/D conversion can be performed in a minimum of 16 sec. An interrupt can be programmed to occur at the end of a conversion. A digital window comparator is available to allow automatic monitoring of external signals without burdening the software. The window comparator allows software to select an upper and lower limit for comparison. In addition, the hardware can be programmed to look inside or outside of the window. By adjusting the window location, the hardware can automatically look for results that are above a number, below a number, inside of a range, or outside of a range. When the window comparator qualifier function is used, an end-of-conversion interrupt will only be generated when selected criteria for the conversion result has been met.
* Monotonic with no missing codes * eight multiplexed inputs * Shared analog/digital pins with 60 dB isolation * Digital window comparator / alarm * Low power consumption
The A/D subsystem consists of a 10-bit successive approximation analog to digital converter, an 8 input analog multiplexor, a programmable reference block, a digital window comparator, and a control block as depicted in Figure 7-1. The multiplexor selects 1 of 8 analog inputs for conversion. A conversion is initiated either by a software or hardware generated start of conversion signal. An optional mode enables continuous conversions on a selected channel. At the completion of a conversion the A/D generates an end of conversion signal indicating that the conversion is complete and the results may be read. An end of conversion can also be used to generate an interrupt. After the conversion is complete, the 10-bit result is available in two registers. In order to accommodate a
7.2
ANALOG POWER / SLEEP MODE
The A/D block provides separate VCC and ground pins to provide power to the analog circuits. This allows the A/D to operate from a clean supply if available. Analog power is supplied through AVCC and AGND. While these pins do supply power, they are not the source of the A/D reference. The converter will draw a maximum of 1 mA during full operation. A minimum time of tAD required for the analog circuitry to stabilize. The ADON bit is cleared to 0 following a reset - leaving the A/D converter powered down.
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A/D CONVERTER BLOCK DIAGRAM Figure 7-1
CPU CLOCK
/ 2N PRESCALE ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 AVCC AGND VRH VRL REFHI REFLO DIGITAL WINDOW COMPARATOR
ACLK 8-CHAN. ANALOG INPUT MUX START/BUSY SAMPLE & HOLD PWR EOC SS/CONT 10-BIT SUCESSIVE APPROXIMATION A/D CONTROL LOGIC STADC
10-BIT LATCH
A/D MS BYTE
A/D LS BYTE
LOWER LIMIT
UPPER LIMIT
7.3
REFERENCE OPTION
7.4
SAR A/D CONVERTER
An A/D conversion is the process of assigning a digital code to an analog input voltage. This code represents the input value as a fraction of the reference voltage range, which divided by the A/D converter into 1024 codes (10-bits). The reference voltage is connected to the internal nodes called REFHI and REFLO as shown in Figure 7-1. The REFHI and REFLO signals are connected to the VRH and VRL pins, respectively. The result can always be calculated from the following formula: Result = 1024 x ( VIN - REFLO) / ( REFHI - REFLO )
Figure 7-2 is a simplified block diagram of the successive approximation A/D converter. As with all successive approximation converters it contains a digital to analog converter (DAC), a comparator, a successive approximation register (SAR) and some control logic. A conversion is initiated by the internal start signal issued from the control logic. The successive approximation logic sets bits of the DAC starting with bit 9 and proceeding to bit 0 on each successive clock (ACLK). After each bit is set the DAC output is compared with the sampled analog input. If the DAC output is less than the analog input the bit remains set. If the DAC output is greater than the analog input the bit is reset. After all bits have been tested and set or reset accordingly, the binary value in SAR[9..0] is a digital representation of the analog input value.
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SAR A/D SIMPLIFIED BLOCK DIAGRAM Figure 7-2
ACLK START EOC CONTROL LOGIC 2 SUCCESSIVE APPROXIMATION REGISTER OFFSET SAR [9..0] RESOLUTION
ANALOG IN
REFHI REFLO
10-BIT SAMPLING D/A CONVERTER CVT ZRO (SAMPLE)
- COMP +
7.5
CONVERSION TIME
An internal clock signal called ACLK is used to clock the successive approximation logic in performing the A/D conversion. ACLK is derived from the microcontroller clock signal through divide-down logic. A total of 16 clock cycles are required to perform the conversion. The minimum ACLK period is 1 s, a faster clock can result in erroneous results. At the other extreme, the maximum clock period is 6.25 s due the dynamic nature of the internal sample-hold circuitry. In order to meet these requirements and accommodate a wide range of CPU clock frequencies a programmable prescaler is provided to generate appropriate converter clock (ACLK) from the CPU clock. Based on the micro's CPU clock, the ACLK frequency can be set to one of 16 values via the four A/D clock prescaler (APS) bits in the ADCON2 register. This results in a conversion clock frequency as given by the formula below: tACLK = tMCLK * (N+1)
where tACLK is the analog clock period, tMCLK is the CPU machine clock period, and N is the clock prescale value ranging from 0 to 15 as programmed in the APS bits. The CPU machine clock period is the oscillator clock period (tCLK) multiplied times 4, 64, or 1024 as determined by the programming of the system clock divider bits (CD1, CD0) in the PMR register. The resulting tACLK must meet the criteria of 1.00 s < tACLK < 6.25 s Table 7-1 gives a set of conversion times at usable A/D clock prescaler settings for a range of microcontroller clock frequencies, assuming that the microcontroller machine clock is at its default value of 4 crystal clock periods.
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A/D CONVERSION TIMES (S)
PRESCALE SETTING 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NOTES: 1. Conversion times given in microseconds (s) 2. ( - ) = not a usable setting 0.640 MHz 100.00 - - - - - - - - - - - - - - - 4.000 MHz 16.00 32.00 48.00 64.00 80.00 96.00 - - - - - - - - - - 8.000 MHz - 16.00 24.00 32.00 40.00 48.00 56.00 64.00 72.00 80.00 88.00 96.00 - - - - 12.000 MHz - - 16.00 21.33 26.67 32.00 37.33 42.67 48.00 53.33 58.67 64.00 69.33 74.67 80.00 85.33 16.000 MHz - - - 16.00 20.00 24.00 28.00 32.00 36.00 40.00 44.00 48.00 52.00 56.00 60.00 64.00 20.000 MHz - - - - 16.00 19.20 22.40 25.60 28.80 32.00 35.20 38.40 41.60 44.80 48.00 51.20 25.000 MHz - - - - - - 17.92 20.48 23.04 25.60 28.16 30.72 33.28 35.84 38.40 40.96 33.000 MHz - - - - - - - - 17.45 19.39 21.33 23.27 25.21 27.51 29.09 31.03
7.6
WINDOW COMPARATOR
The window comparator allows software to identify a range of potential digital A/D results that are considered interesting. The window comparator will monitor each conversion result against user programmed selections. Results that meet the criteria will cause the comparator to set the WCM flag. By setting the WCQ bit, the end of conversion interrupt source is qualified so that only results which fall within the programmed range cause the interrupt. This feature allows software to ignore uninteresting results without actually reading the converter result. User software can select two 8-bit comparator values. These values will be compared against the most signifi-
cant 8-bits of each A/D result, designated as ADR9-2. The user also can identify whether the target result is inside of the range bounded by the upper and lower limit or outside through programming of the WCIO bit. In practice, this allows the comparator to look for A/D results that are above a number, below a number, inside of a range, or outside of a range. The state of the WCM flag can be expressed by the following Boolean equation: WCM = WCIO (WINHI < ADR9-2) (WINLO < ADR9-2) Figure 7-3 illustrates the ranges that can be examined using the window comparator.
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WINDOW COMPARATOR OPERATION Figure 7-3
3FFH 3FFH
WINHI
WINHI
WCIO = 0 WINLO WINLO
WCIO = 1
000H
000H
WINHI VALUE >ADR9-2 >ADR9-2 WINLO VALUE >ADR9-2 ADR9-2 WCM (WCIO=0) 0 1 1 0
WCM (WCIO=1) 1 0 0 1
WINDOW STATUS Outside Inside Inside Outside
Note that there is no hardware significance to upper and lower designations. The upper comparison value can be selected as less than the lower comparison value, although doing so provides no additional function.
7.7
A/D OPERATION
Prior to initiating a conversion, software must select several parameters. First, the conversion channel must be selected. The next selection is whether this signal will be constantly monitored or simply converted once. Thus, software chooses continuous conversion or single shot. The window comparator can then be programmed to look for particular result ranges. The conversion time must be programmed using the prescale value. This is a function of the urgency of getting a result and the operating frequency. If interrupt operation is desired, the EAD bit (EIE.1) must be set. At this time, the converter is ready to operate. Software may either begin a conversion by setting the start conversion bit, or enable the external start conversion pin. If enabled, a falling edge on the pin will start conversion. At this time, the A/D hardware will set the start/busy bit to a logic 1. Once a conversion has been started, it can only be interrupted by powering down the converter. An interval of 16 A/D clocks at the prescale frequency is used to time the conversion process. The selected input channel will be sampled by a sample and hold for five A/D clocks. Ten A/D clocks are used to perform the successive approximation conversion. On the final
clock cycle, the hardware will set the EOC bit to a logic 1. If A/D interrupts are enabled via EAD, an interrupt condition will be generated every time that EOC is set to 1 when WCQ = 0. When WCQ = 1, an interrupt will be generated at the end of a conversion when EOC and WCM both are set to 1. In all cases EOC should be cleared to 0 by software after the result is read in order to clear the interrupt condition. If continuous operation is selected, the A/D will then automatically restart the process on the next machine cycle after completing the conversion. Thus, in this case the busy flag appears to be set at all times. If the single shot mode is selected subsequent to operation in the continuous mode, single shot operation will take effect when the converter finishes the current conversion. Power control of the A/D is a manual operation . The converter defaults to a power-down condition. If software disables power to the converter, it will require a period of tAD to restart when software re-enables the power.
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7.8
A/D SPECIAL FUNCTION REGISTERS
The following is a description of the Special Function Registers used to control the on-chip A/D converter.
7.8.1
ADCON1 - A/D Control Register 1
ADCON1; SFR ADDR.=0B2H BIT 7 STRT/ BSY BIT 6 EOC BIT 5 CONT/ SS BIT 4 ADEX BIT 3 WCQ BIT 2 WCM BIT 1 ADON BIT 0 WCIO
Read/Write Access: (Read at any time, See individual bit description for write operation) Initialization: 00h on any type of reset
STRT/BSY - Start/Busy.
Setting this bit to a 1 from a 0 condition will initiate an A/D conversion. The bit will then remain set for the duration of the conversion, regardless of any attempt to write it to 0. Thus, the bit serves as a busy flag as well. When a conversion is complete, the A/D hardware will clear this bit to 0.
occur only when EOC and WCM are both set to a 1 at the end of a conversion. When cleared to a 0, an interrupt can result each time that EOC is set at the end of any conversion.
WCM - Window Comparator Match.
At the end of conversion, WCM is updated. WCM will be set when the window comparator detects an A/D result that matches the selected criteria. If the A/D result does not match the criteria for the window as specified in the WINHI and WINLO limit registers as well as the WCIO, WCM will not be set.
EOC - End of Conversion.
The A/D will set this bit to a 1 when a conversion is complete. EOC also serves the function of an interrupt flag which may be qualified via the WCQ bit described below.
ADON - A/D ON. CONT/SS - Continuous/Single Shot.
When set to a 1, the A/D will repeatedly run conversions without software intervention once a conversion is initiated. When cleared to a 0, the A/D will perform the requested conversion then halt. Setting the bit from a 1 to a 0 (taking it out of continuous mode) will cause the converter to halt when the current conversion is completed. Setting this bit to a 1 applies power to the analog circuit functions, and must be set in order to perform an A/D conversion. The A/D requires a warm up period of tAD when setting this bit from a 0 to a 1 condition before a proper conversion can be performed. In order to assure a very low power STOP mode or to save power in other states, this bit should be cleared to 0. Clearing ADON to 0 will abort any conversion in progress and will reset STRT/BSY to a 0.
ADEX - A/D External Start.
When this bit is set to a 1, an A/D can be initiated by a falling edge detected on an external pin. When set to a 0, the external pin has no effect. When a pin is used to initiate a conversion, the A/D will write a 1 to the STRT/ BSY bit to indicate that a conversion has started. When ADEX = 1, the STRT bit can still be used.
WCIO - Window Comparator Inside / Outside.
When set to a 1, the window comparator looks for A/D results that are outside of the window bounded by the WINHI and WINLO limits. When set to a 0, the comparator looks for A/D results that are inside of the window bounded by WINHI and WINLO.
WCQ - Window Comparator Qualifier.
Setting this bit to a 1 enables the window comparator qualifier function. When WCQ = 1, an interrupt can
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7.8.2
ADCON2 - A/D Control Register 2
ADCON2; SFR ADDR.=0B3H BIT 7 OUTCF BIT 6 MUX2 BIT 5 MUX1 BIT 4 MUX0 BIT 3 APS3 BIT 2 APS2 BIT 1 APS1 BIT 0 APS0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset
OUTCF - Output Conversion Format.
Selects whether the conversion output most-significant 8-bits or the most-significant 2-bits are presented in the A/D MSB register. When OUTCF = 1, the MSB register returns the upper 2 conversion bits, ADR8 and ADR9 in bit locations 0 and 1 respectively. When OUTCF = 0, the MSB register returns the upper 8 bits with result bit ADR9 located in bit position 7 and result bit ADR2 in bit position 0.
MUX2 0 0 0 0 1 1
MUX1 0 0 1 1 0 0 1 1
MUX0 0 1 0 1 0 1 0 1
PIN AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7
A/D CHANNEL Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
MUX2-0 - Multiplexor Select.
MUX2-0 selects the A/D channel that will be sampled and converted when the next conversion is initiated. The table to the right shows the decoding.
1 1
APS3-0 - A/D Clock Prescale Select.
APS3-0 are used to determine the prescale setting from the micro's CPU clock to the A/D converter. The CPU machine clock will be divided by the value of (N+1) where N is the 4-bit value represented by APS3-0.
7.8.3
ADMSB - A/D Result Most Significant Byte
ADMSB; SFR ADDR.=0B4H BIT 7 ADR9/ 0 BIT 6 ADR8/ 0 BIT 5 ADR7/ 0 BIT 4 ADR6/ 0 BIT 3 ADR5/ 0 BIT 2 ADR4/ 0 BIT 1 ADR3/ ADR9 BIT 0 ADR2/ ADR8
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset Depending on the programming of the OUTCF bit, this register contains either the most significant 8-bits or 2-bits of the conversion result. If OUTCF = 0 bits 7-0 contain bits 9-2, respectively, of the result. If OUTCF=1, bits 7-2 contain 0, and bits 1 and 0 contain result bits 9 and 8, respectively.
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7.8.4 ADLSB - A/D Result Least Significant Byte
ADLSB; SFR ADDR.=0B5H BIT 7 ADR7 BIT 6 ADR6 BIT 5 ADR5 BIT 4 ADR4 BIT 3 ADR3 BIT 2 ADR2 BIT 1 ADR1 BIT 0 ADR0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset ADLSB always returns the least significant 8-bits of the conversion result.
7.8.5 WINHI - A/D Window Comparator High Byte
WINHI; SFR ADDR.=0B6H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset Upper limit for the window comparator. These 8-bits are compared against the most significant 8-bits of the previous A/D result. A match of the desired magnitude causes the comparator to set the WCM flag. The match condition is selected by the WCIO bit in ADCON1.
7.8.6
WINLO - A/D Window Comparator Low Byte
WINLO; SFR ADDR.=0B7H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset Lower limit for the window comparator. These 8-bits are compared against the most significant 8-bits of the previous A/D result. A match of the desired magnitude causes the comparator to set the WCM flag. The match condition is selected by the WCIO bit in ADCON1.
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8.0 8.1
ACTIVITY MONITOR OVERVIEW
During periods of inactivity, varying levels of standby and suspend modes of operation can be initiated by the GEM. Inactivity can be detected by the GEM and then action can be taken to reduce the power consumption of the system and thereby conserve operating power. Activity monitoring is performed by the special logic provided as an alternate function on all lines of Port 7. This alternate function allows any combination of the Port 7 pins to be configured as activity monitor inputs. In this mode, these pins are intended for connection to the chip select signals of external peripheral subsystems, such as the hard disk, floppy, etc. These pins can be optionally qualified by the IOR and IOW input control signals. When inactivity is detected, peripheral devices such as the LCD display, hard disk, floppy disk, and modem are turned off as required by the microcontroller firmware. This is accomplished via parallel I/O pins as assigned by the user. When CPU accesses to memory or I/O locations which are connected to the activity monitor inputs are detected, accessed peripheral devices can be turned back on by the firmware. As an option, the host CPU can be notified of the power on sequence by writing a word to the power management host interface port, which activates the SMI.
programmed into a bit in the AMP register selects a low state signal as active for the pin (default case) while a "1" selects a high state signal. When an active state is detected on an enabled activity monitor pin, the associated bit in the Activity Monitor Flag (AMF-095H) will be set. In order to avoid false triggering of the activity monitor inputs due to glitches from an external address decoder, the inputs can be optionally qualified by the IOR and IOW lines via the Activity Monitor Qualify register (AMQ-093H). When a bit is set to 1 in the AMQ register, the associated pin will not be active unless it is accompanied by a valid IOR or IOW signal. When AMQ bits are 0, the associated pins qualify function is disabled (default case). Interrupts initiated from the enabled activity monitor pins are enabled by the EAM bit (IE.6), and their priority can be adjusted via PAM (IP.6). When activity monitor interrupts are enabled and an active state occurs, an interrupt will be generated, and the GEM firmware should read the AMF register to determine the source of the interrupt. The interrupt flag can be cleared by writing a "0" to the flag bit; writing a 1 will have no effect. When all peripheral devices in the system are fully powered, host accesses to them may occur very often. So often in fact, that if these accesses were to initiate interrupts during this time the GEM may be bogged down in unnecessary interrupt service routines servicing the interrupts. Typically, it is necessary only to ascertain whether each monitored device has been accessed by the host over the past, say, 16-second period. In order to eliminate any unnecessary interrupt processing burden, it may be desirable to disable the interrupts from the activity monitor inputs (e.g., by clearing EAM) and reading the register once during each such period. This period can be easily set up via the Power Down Periodic Interrupt described below.
8.2 ACTIVITY MONITOR INPUT OPERATION
The activity monitor enable bits in the Activity Monitor Enable (AME-092H) register select the associated pins from Port 7 as activity monitor inputs. In order to function properly, each enabled pin must have a 1 programmed into its Port 7 output latch bit. The current state of the Port 7 pins can always be read through the Port 7 input buffer regardless of the programming of the activity monitor enable bits. Figure 8-1 shows the logic associated with each Activity Monitor Input. The active state for each pin is programmed via the Activity Monitor Polarity register (AMP-094H). A "0"
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ACTIVITY MONITOR INPUTS Figure 8-1
RD_P7.n
AMI.n BIT AMP.n
BIT AME.n
BIT AMQ.n
IOR IOW
ACTIVITY MONITOR INTERRUPT
WR_"0"_AMF.n RD_AMF.n
When one or more peripheral devices have been powered down due to inactivity, it may be desirable at that time to enable interrupts to at least those devices. When an access is attempted by the host, the GEM can take the appropriate action to apply power to the periph-
eral. During such time, the GEM can activate the SMI interrupt by writing power management host interface output buffer register with a status word reflecting the current condition.
8.3
AME - ACTIVITY MONITOR ENABLE REGISTER
AME; SFR ADDR.=092H BIT 7 AME7 BIT 6 AME6 BIT 5 AME5 BIT 4 AME4 BIT 3 AME3 BIT 2 AME2 BIT 1 AME1 BIT 0 AME0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset When an AME bit is set to 1, it enables the corresponding line of Port 7 as an activity monitor interrupt source. An interrupt condition will exist when the associated activity monitor flag bit is set (see below). When AME is cleared to 0, the associated pin is disabled as an interrupt source. The associated Port 7 latch bit must be set to 1 when a pin is to be programmed as an activity monitor input.
8.4
AMQ - ACTIVITY MONITOR QUALIFIER REGISTER
AMQ; SFR ADDR.=093H BIT 7 AMQ7 BIT 6 AMQ6 BIT 5 AMQ5 BIT 4 AMQ4 BIT 3 AMQ3 BIT 2 AMQ2 BIT 1 AMQ1 BIT 0 AMQ0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset
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When an AMQ bit is set to 1, the corresponding activity monitor input pin is qualified with IOR or IOW. As a result, the corresponding AMF bit will not be set unless the programmed state on the AMI.n pin is accompanied
with a valid IOR or IOW signal. This prevents false triggering of activity monitor inputs from chip select outputs due to address decoding glitches.
8.5
AMP - ACTIVITY MONITOR POLARITY REGISTER
AMP; SFR ADDR.=094H BIT 7 AMP7 BIT 6 AMP6 BIT 5 AMP5 BIT 4 AMP4 BIT 3 AMP3 BIT 2 AMP2 BIT 1 AMP1 BIT 0 AMP0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset The bits in the AMP register are used to select the polarity of a valid state on the activity monitor input pins. When an AMP bit is set to 1, a high state is selected as valid on the corresponding AMI pin. When and AMP bit = 0, a low state is selected as valid.
8.6
AMF - ACTIVITY MONITOR FLAG REGISTER
AMF; SFR ADDR.=095H BIT 7 AMF7 BIT 6 AMF6 BIT 5 AMF5 BIT 4 AMF4 BIT 3 AMF3 BIT 2 AMF2 BIT 1 AMF1 BIT 0 AMF0
Read/Write Access: Unrestricted. Initialization: 00h on any type of reset An AMF bit will be set whenever a valid state is detected on the associated AMI.n pin. A valid state is determined by the programming of the Activity Monitor Polarity register and the Activity Monitor Qualifier register, both described above. If the associated AME bit is set, the AMF bit is enabled as an interrupt source. An GEM interrupt will be recognized if the EAM is also set, enabling activity monitor interrupts. Upon receiving an activity monitor interrupt, the system should read the AMF register to determine the source of interrupt. An AMF bit can be cleared by writing it to a 0 to clear the interrupt source condition. Writing a 1 has no effect.
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9.0 9.1
HOST INTERFACE PORTS OVERVIEW
inputs as it does with the 8042 in these systems. The other port can be assigned as a communication channel to the GEM to support power management and/or other functions.
The GEM provides two interface ports to the host CPU which are hardware-compatible with the interface to the 8042 keyboard controller IC as it is used in conventional PC system designs. One of the interface ports is intended to be assigned to the standard keyboard controller function. The host thereby communicates to the GEM as a slave microcontroller in receiving key scan
MICROCONTROLLER SYSTEM INTERFACE PORTS Figure 9-1
INTERNAL DATA BUS A0 KBCS REGISTER ENABLE DECODE KBSTAT STATUS REG. KBDIN INPUT DATA BUFFER KBDOUT OUTPUT DATA BUFFER R/W 0ADH
IOW SD7-SD0 IOR KBOBF
RD 0AEH
R/W 0AFH
PMCS
REGISTER ENABLE DECODE
PMSTAT STATUS REG.
R/W 0BDH
PMDIN INPUT DATA BUFFER
RD 0BEH
SMI
PMDOUT OUTPUT DATA BUFFER
R/W 0BFH
9.2
REGISTER MAPPING
The KBCS line is used by the host system in selecting the keyboard system interface port, while the PMCS line selects the identical power management interface port. Each set of system interface registers occupy three
memory locations in the GEM, but only two in the host. Table 9-1 summarizes access of the two interface ports by the host system, and Table 9-2 summarizes access to the port registers by the GEM.
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SYSTEM DATA TRANSFER SUMMARY Table 9-1
KBCS 0 0 0 0 0 1 1 1 1 1 PMCS 0 1 1 1 1 0 0 0 0 1 A0 X 0 1 0 1 0 1 0 1 X IOR X 0 0 1 1 0 0 1 1 X IOW X 1 1 0 0 1 1 0 0 X REGISTER SELECTED Undefined KBDOUT KBSTAT KBDIN KBDIN PMDOUT PMSTAT PMDIN PMDIN None Undefined Read Keyboard Data Out Read Keyboard Status Write Keyboard Data In; Set KC/D = 0 Write Keyboard Command; Set KC/D = 1 Read Pwr. Mgr. Data Out Read Pwr. Mgr. Status Write Pwr. Mgr. Data In; Set PC/D = 0 Write Pwr. Mgr. Command; Set PC/D = 1 System interface port disabled OPERATION
GEM SYSTEM I/F REGISTER ACCESS SUMMARY Table 9-2
SFR ADDR. 0ADH 0AEH 0AFH 0BDH 0BEH 0BFH REGISTER KBSTAT KBDIN KBDOUT PMSTAT PMDIN PMDOUT READ/WRITE ACCESS Read / Write (write on selected bits) Read Only Read / Write Read / Write (write on selected bits) Read Only Read / Write
9.3
KBDIN / PMDIN - DATA REGISTERS
KBDIN; SFR ADDR.=0AEH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PMDIN; SFR ADDR.=0BEH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Read only. Initialization: Undefined on any type of reset Each input data register (KBDIN or PMDIN) is a read- only register to the GEM and a write-only register to the host. The associated input buffer full flag (KIBF or PIBF) will be set when the host CPU writes to one of the input
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buffers. The GEM can enable an "input buffer full" interrupt on either port by setting the associated interrupt enable bit (EKB or EPB). Upon interrupt, the GEM's firmware should check to see if the incoming byte is a
command or data by reading the command/data flag, i.e., KC/D or PC/D, in the status register followed by a read of the input data register. The contents of the input data registers are unaffected by any type of reset.
9.4
KBSTAT / PMSTAT - STATUS REGISTERS
KBSTAT; SFR ADDR.=0ADH BIT 7 KST7 BIT 6 KST6 BIT 5 KST5 BIT 4 KST4 BIT 3 KC/D BIT 2 KST2 BIT 1 KIBF BIT 0 KOBF
PMSTAT; SFR ADDR.=0BDH BIT 7 PST7 BIT 6 PST6 BIT 5 PST5 BIT 4 PST4 BIT 3 PC/D BIT 2 PST2 BIT 1 PIBF BIT 0 POBF
Read/Write Access: Unrestricted. Initialization: XXXXXX00B on any type of reset The operation of the bits in the status registers of both ports are summarized below: These flags also serve as interrupt pending flags. A Keyboard Buffer Interrupt (KBI) will be generated if the Keyboard Buffer Interrupt Enable (EKB) bit is set. Likewise, a Power Management Buffer Interrupt (PBI) will be generated if the Power Management Buffer Interrupt Enable (EPB) is set. Both of these bits are automatically cleared to 0 following a read of the associated input data registers. In addition, both bits are cleared to 0 following any type of reset.
KST7-KST4, KST2/PST7-4, PST2 - Keyboard / Power Mgr. Status.
KST7-4, KST2, PST7-4, PST2 bits are RAM locations which can be used to communicate user-defined status conditions to the host system. They are read/write by the microcontroller and read-only by the host CPU. The KST7-4 bits are traditionally used by the keyboard control firmware for parity error, receive timeout, transmit timeout, and inhibit switch status. All of these bits are unaffected by any type of reset.
KOBF / POBF - Keyboard / Power Mgr. Output Buffer Full.
KOBF an POBF are read-only status bits which are set to 1 when the associated output data buffer register is written by the GEM. Each of these bits are automatically cleared to 0 when the host system reads the associated output data registers. When the KOBF flag is set, an active high interrupt signal to the host will be generated through the KBOBF pin and will remain active until the output buffer is read by the host. Similarly, when POBF flag is set, an active low interrupt signal will be issued to the host via the SMI pin. There are no output buffer-related interrupts to the GEM. Both of these bits are cleared to 0 following any type of reset.
KC/D / PC/D - Keyboard / Power Mgr. Command / Data.
KC/D AND PC/D each specify whether the associated input data register contains data or a command (0 = data, 1 = command). During a host write operation, the associated C/D bit will be set to a 1 if A0 = 1 or will be cleared to 0 if A0 = 0. Both KC/D and PC/D are read- only status bits to both the GEM and the host CPU. They cannot be written directly, they only can be written as a result of the host write operation described above. Both of these bits are unaffected by any type of reset.
KIBF / PIBF - Keyboard / Power Mgr. Input Buffer Full.
The KIBF or PIBF flag is set to 1 whenever the host system writes data into the associated input data register.
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9.5
KBDOUT / PMDOUT - OUTPUT DATA REGISTERS
KBDOUT; SFR ADDR.=0AFH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PMDOUT; SFR ADDR.=0BFH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: Undefined on any type of reset The output data registers can be read or written by the GEM but are read only to the host When the GEM writes to one of the output data registers, the associated output buffer full flag will be set to alert the host that the output data is available. The contents of the output data registers are unaffected by any type of reset.
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10.0 KEYBOARD SCANNING PORTS 10.1 OVERVIEW
Three 8-bit I/O ports are provided which can be used for key matrix scan line outputs and inputs. Ports 8 and 9 are intended for scan line outputs, while port 4 is intended for scan line inputs.
capable of generating an interrupt on a low-going transition. As a result, the GEM can initiate a keyboard scan only when a key is pressed instead of doing it periodically. Thus, battery drain is minimized. In order to use a Port 4 pin as a key scan input, its output latch bit in the Port 4 SFR register must be first written to a 1, which configures the pin as an input. Negative transition detection on each pin is enabled by setting the matching KDEn enable bit in the Keyboard Detect Enable Register to a 1. Then, when a negative transition occurs on an enabled input, the corresponding interrupt flag bit will be set in the Keyboard Detect Flag Register. If the Key Detect Interrupt Enable bit is set (EKD; register EIE.5), a keyboard interrupt will then be recognized by the GEM core. Upon interrupt, the system should scan the keyboard matrix via other output ports (typically ports 8 and 9) to identify the location of the pressed key. The set keyboard interrupt flag bits should be cleared by firmware to clear the interrupt condition before exiting the interrupt service routine.
10.2 KEY SCAN OUTPUTS
Ports 8 and 9 together provide 16 open-drain lines which are intended for use as key scan outputs. These lines are logically accessed and operated as normal pseudo-bi-directional I/O port pins. As a result, lines which are not required for the key scan function can be used as general purpose I/O for the control of other functions.
10.3 KEY SCAN INPUTS
Port 4 is a parallel I/O port which is logically and electrically tailored for keyboard matrix scan inputs. All of the port 4 pins are Schmitt triggered inputs and are internally pulled high by a resistor. In addition, all pins are
10.4 KDE - KEY DETECT ENABLE REGISTER
KDE; SFR ADDR.=0A5H BIT 7 KDE7 BIT 6 KDE6 BIT 5 KDE5 BIT 4 KDE4 BIT 3 KDE3 BIT 2 KDE2 BIT 1 KDE1 BIT 0 KDE0
Read/Write Access: Unrestricted. Initialization: Undefined on any type of reset
KDE7-KDE0 - Key Detect Enable Bits
When a KDEn enable bit is set, it enables negative- edge transition detection on the corresponding line of
port 4. When a KDEn bit is cleared no transition detection is performed on the corresponding line.
10.5 KDF - KEYBOARD DETECT FLAG REGISTER
KDF; SFR ADDR.=0A6H BIT 7 KDF7 BIT 6 KDF6 BIT 5 KDF5 BIT 4 KDF4 BIT 3 KDF3 BIT 2 KDF2 BIT 1 KDF1 BIT 0 KDF0
Read/Write Access: Unrestricted read; all bits write only to 0. Initialization: 00H on any type of reset KDFn are flag bits for the keyboard activity detection. If a port 4-pin has its KDEn bit set, the corresponding KDFn is set when an negative edge is detected on that pin. An GEM interrupt will be recognized if the KDEn bit is set and the interrupts are enabled. Upon receipt of the interrupt, the system should read this register to determine on which scan line the key closure occurred. The firmware can then scan the keyboard matrix using Ports 8 and 9 as outputs to identify the location of the depressed key. In order to clear the interrupt condition, the firmware should clear the interrupting KDF bit(s) by writing 00H to the KDF register prior to exiting the interrupt service routine.
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11.0 MOUSE / DETACHED KEYBOARD SERIAL I/O 11.1 OVERVIEW
The GEM incorporates two identical serial ports which provide hardware support for industry standard serial communication to a PS/2 style mouse or detached keyboard. The major features of these hardware ports include:
notation is used in referring to bits, pins, or registers which are identical in function in either the mouse or detached keyboard ports. For example, the designation of "xDAT" is used to refer to both the MSDAT and DKDAT registers. Figure 11-1's a block diagram which illustrates the hardware for both the mouse and detached keyboard serial ports.
* Byte-oriented
keyboard.
transfers to / from external mouse /
* Request to send delay generation * Parity generation and checking * Acknowledgment status
In the following description, the mouse or detached keyboard is referred to as the input device. A short form
MOUSE / DETACHED KEYBOARD SERIAL PORT BLOCK DIAGRAM Figure 11-1
MSDAT / DKDAT RECEIVE DATA BUFFER RD 0D9H / 0D1H
EN WR
MSDIO / DKDIO PIN
DOUT LOAD MSB
WR 0D9H / 0D1H
SHIFT REGISTER
DIN SHIFT LSB
GEM INTERNAL DATA BUS
TIMING / CONTROL LOGIC 32 KHz
MSCLK / DKCLK PIN
MSCON / DKCON CONT. / STAT. REGISTER RD / WR 0DAH / 0D2H
EN
PARITY LOGIC
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11.2 INTERFACE PINS
The GEM mouse / detached keyboard serial I/O ports both communicate with an input device over "clock" and "data" lines as defined for an AT or PS/2-compatible personal computer. The input devices' clock and data lines are tied to the xCLK and xDIO pins, respectively; both of which are open-drain input/output port pins. xCLK and xDIO refer to MSCLK and MSDIO for the mouse port, and to DKCLK and DKDIO for the detached keyboard serial port. MSCLK and MSDIO are the alter-
nate function of P1.4 and P1.5 general purpose parallel I/O port pins, respectively. DKCLK and DKDIO are the alternate function of the P1.6 and P1.7, respectively . In order to use either serial port, the associated Port 1 latch bits must both be programmed with a "1". The open-drain structure of xCLK and xDIO allow either the input device or the GEM to force a line to the negative level. When no communication is occurring, both the xCLK and xDIO lines are at a positive level.
11.3 DATA TRANSMISSION
Data transmission in or out of the input device serial port consist of 11-bit data streams that are sent serially over the "data" line. Table 11-1 shows the format of the serial data word. The parity bit is either 1 or 0, with the eight data bits plus the parity bit always equal to an odd number. When the GEM sends data to the input device, it forces the clock line to a negative level and after an initial delay of 100 s allows the clock line to go to a positive level. When the input device sends data to, or receives data from the system, it generates the clock signal to time the data. The GEM can prevent the input device from sending data by forcing the xCLK line to a negative level; the xDIO line may go high or low during this time. Transmitted data from either GEM or the input device is valid after the rising edge and before the falling edge of the xCLK line.
INPUT DEVICE SERIAL WORD FORMAT Table 11-1
BIT 1 2 3 4 5 6 7 8 9 10 11 Start Bit
FUNCTION
Data Bit 0 (least significant) Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 (most significant) Parity Bit (always odd) Stop Bit (always 1)
11.4 REGISTER DESCRIPTION
The microcontroller interface to each serial port consists of 2 Special Function Registers (SFR's) which are documented below. None of these registers are bit addressable.
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11.4.1 MSDAT / DKDAT - Data Registers
MSDAT; SFR ADDR.=0D9H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DKDAT; SFR ADDR.=0D1H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The Data Register provides access to the shift register during transmit and to the receive buffer during receive. For each port, the shift register and receive buffer is located at a common address. A write to this location results in a write to the shift register, while a read results in a read from the receive buffer register. During transmit, a write to this location results in 8-bits of data being loaded into the shift register and a request-to-send condition being issued on the clock and data lines. The contents of both the shift register and the receive buffer are cleared to zero following any type of reset.
11.4.2 MSCON / DKCON - Control / Status Registers
MSCON; SFR ADDR.=0DAH BIT 7 - BIT 6 MSEN BIT 5 MSWU BIT 4 MSFE BIT 3 MSPE BIT 2 MSBI BIT 1 MSTXI BIT 0 MSRXI
DKCON; SFR ADDR.=0D2H BIT 7 - BIT 6 DKEN BIT 5 DKWU BIT 4 DKFE BIT 3 DKPE BIT 2 DKBI BIT 1 DKTXI BIT 0 DKRXI
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset
MSEN / DKEN - Mouse / Detached Keyboard Serial Enable.
When set to a 1, xEN enables the input device for operation. The port will then monitor the xCLK, and xDIO lines to receive data from the input device, and will initiate a transmit when data is written to the xDAT register. The associated Port 1 bits for the serial port must be set to a 1 for proper operation. When xEN is cleared to 0, the serial port is disabled: no transmit or receive actions occur and no interrupt flags are set.
MSWU / DKWU - Mouse / Detached Keyboard Serial Wake-Up.
When set to a 1, xWU allows the input device port hardware to "wake-up" the GEM from a low power standby mode in response to transmission initiated by the input device. During normal speed operation, xWU should be cleared to 0.
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MSFE / DKFE - Mouse / Detached Keyboard Framing Error.
The xFE bit will be set whenever data is received from the input device with the start bit set to a 1 and / or the stop bit set to 0, or when the input device responds with a "1" on the data line during the 11th clock of a transmission from the GEM.
bit (EIP.7, 0F8H). Each ports xBI, xTXI, and xRXI flag bits are all potential interrupt sources when the associated interrupt enable bit is a 1. Upon interrupt, the firmware should examine these three flags to determine the condition causing the interrupt. In order to clear the interrupt condition, the interrupting flag bit(s) should be cleared to 0.
MSPE / DKPE - Mouse / Detached Keyboard Parity Error.
The xPE bit reflects the result of the parity test performed when the last byte of data received from the input device was received. If xPE = 1, the last received eight bits plus the parity bit was an even number (error). If xPE = 0, the last received 8 bits plus parity was odd (normal case).
11.6 INITIALIZATION
Either serial port is initialized for operation by first clearing the three flag bits (xBI, xTXI, and xRXI) and then setting the xEN bit. If interrupts are to be enabled, the associated interrupt enable bit should also be set.
11.7 DATA OUTPUT OPERATION
Data is sent to the input device by writing to the xDAT register. This action will load the byte to be transmitted into the shift register and will automatically issue the request-to-send state by pulling the clock line low for 100 s. Hardware will wait for the input device to clock out the transmit data. The 100 s delay is derived from the 32 KHz frequency. Therefore, a 32 KHz crystal or clock signal must be supplied on the crystal pins CX1 and CX2 in order for the input device to operate. If the GEM firmware writes to the data register while data is being received from the input device before the tenth clock pulse has been issued, the shifted-in data will be overwritten in the shift register. In this event, the input device will detect the request-to-send state and stop sending data and will then begin to clock out the data transmitted from the GEM. If the write occurs to the data register following the rising edge of the tenth clock, the input data will already have been transferred to the receive buffer register and the parity flag will have been updated. If desired, the firmware can check to see if the input device is sending data by monitoring the xBI bit before writing to the data register. If the xBI bit has been set since the last time xRXI was set or since a reset, then the input device is in the process of shifting in a serial data word. Following a write to the xDAT register, an AT or PS/2 input device has a 15 ms limit in which to begin clocking the data out. The firmware should therefore begin a 15 ms timeout check following a write to the xDAT register. When the input device issues the first clock pulse, the xBI flag will be set. Assuming that this event occurs
MSBI / DKBI - Mouse / Detached Keyboard Start Bit Interrupt.
xBI will be set to a 1 when the input device initiates a transmission to the GEM. xBI is set at the time that the start bit of this incoming data byte is shifted in. The setting of this bit can initiate an interrupt if interrupts are enabled. xBI should be used to initiate the 2 ms timeout required for the entire data byte to be received. xBI must be cleared by firmware to remove the flagged condition.
MSTXI / DKTXI - Mouse / Detached Keyboard Transmit Interrupt Flag.
xTXI will be set when the data has been completely shifted out in the transmitter. The setting of xTXI can initiate an interrupt if the port interrupt is enabled. xTXI must be cleared by firmware to remove the flagged condition.
MSRXI / DKRXI - Mouse / Detached Keyboard Receive interrupt Flag.
xRXI will be set when the data has been completely shifted in. The incoming word can be read in the xDAT register, and the xPE bit will be updated at this time. The setting of xRXI can initiate an interrupt if the port interrupt is enabled. xRXI must be cleared by firmware to remove the flagged condition.
11.5 INTERRUPTS
Interrupts for the mouse serial port are enabled via the EMS bit (EIE.2, 0E8H) and priority is controlled via the PMS bit (EIP.2, 0F8H). Similarly, interrupts for the detached keyboard serial port are enabled via the EDK bit (EIE.7, 0E8H) and priority is controlled via the PDK
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within 15 ms, the firmware should then initiate the 2 ms timeout count for the entire word to be shifted out; also specified for an AT or PS/2 input device. These timeout checks can be accomplished using one of the programmable timers operating as an interval timer. During a normal transmit, the input device will generate 10 clock pulses to clock out data bits 0-7, the parity bit, and the stop bit. If the transmit data was properly received by the input device, it will generate an 11th clock pulse and pull the data line low as an acknowledgment. When the 11th clock is received, the xTXI flag bit will be set. If the input device returns a "1" as the acknowledgment bit, the xFE bit will also be set at this time to indicate a transmission error to the GEM firmware. AT- or PS/2 compatible input devices must send back a response to a properly transmitted word within 20 ms. The setting of the xTXI flag should cause the firmware to begin a timeout count to check this response time.
event should cause the firmware to initiate the 2 ms timeout until the entire word is shifted in. When all 11 bits are shifted in from the input device, the xRXI interrupt flag will be set, and an interrupt will be generated if the associated enable bit is set. During transmission, the input device checks the clock line for a positive level at least every 60 s. If the GEM's firmware initiates a transmission by a write to the data register before the rising edge of the tenth clock (parity bit), the input device will stop sending data. If the write to the transmit register occurs after the rising edge of the tenth clock pulse, the incoming data will be loaded into the receive buffer before the shift register is written with data to be sent to the input device.
11.8.1 Wake-Up
For proper serial port operation, the microcontroller clock frequency must be faster than the clock signal generated by the input device. The GEM's slow clock and STOP modes allow the internal clock frequency to be slower than the input device clock signal. The xWU bit provides a way to wake-up the GEM in response to data being received from the input device. When xWU is set, the serial port will detect a request to transmit by the peripheral, set the xBI bit, and hold the xCLK line low until the firmware clears xBI. This allows time for the internal clocks to be restored to normal frequency from a slow clock or STOP condition with no loss of received data from the input device.
11.8 DATA INPUT OPERATION
When the input device is ready to send data, it first checks for an inhibit or request-to-send status on the GEM's data (xDIO) and clock (xCLK) pins. If the clock line is low (inhibit status), the input device will store the data in its buffer. If the clock line is high and the data line is low (request-to-send), data is stored in the input device's buffer, and it receives system data. If clock and data are both high, the input device sends the data word described in Table 11-1. When the input device clocks in the start bit, the xBI flag will be set. This
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12.0 PULSE WIDTH MODULATORS 12.1 FUNCTIONAL OVERVIEW
The GEM includes four independent timer channels which can generate pulse-width modulated outputs. All four pulse width modulator channels incorporate a clock selector which generates an independent clock source
for each channel. As a result, an independent clock frequency can be selected for each pulse width modulator. Each pulse width modulator is capable of generating a waveform which has a programmable duty cycle of n/256% where 0PWM BLOCK DIAGRAM Figure 12-1
*1 *4 *16 *64 PWM 0 CLOCK GENERATOR
tMCLK (uC MACHINE CLOCK)
PRESCALER
PWM 0 PULSE GENERATOR
PWO.0 (P6.0 ALT. FUNCITON) PWI.0 (P6.4 ALT. FUNCITON)
PWM 1 CLOCK GENERATOR
PWM 1 PULSE GENERATOR
PWO.1 (P6.1 ALT. FUNCITON) PWI.1 (P6.5 ALT. FUNCITON)
PWM 2 CLOCK GENERATOR
PWM 2 PULSE GENERATOR
PWO.2 (P6.2 ALT. FUNCITON)
PWM 3 CLOCK GENERATOR
PWM 3 PULSE GENERATOR
PWO.3 (P6.3 ALT. FUNCITON)
12.2 PRESCALER
This block creates and distributes four clock outputs which are supplied to the clock selectors. The prescaler takes the microcontroller machine clock and divides it to produce reduced speed frequencies. The CPU machine clock period (tMCLK) is the oscillator clock period (tCLK) multiplied times 4, 64, or 1024 as determined by the programming of the system clock divider bits (CD1, CD0) in the PMR register. The prescaler provides four frequencies: tMCLK *1, tMCLK *4, tMCLK *16, tMCLK *64. These frequencies are free running and are not specifically enabled or selected. They are simultaneously available to the four PWM clock selectors as described below.
pin as inputs. PWI.0 may be selected as the clock generator input for PWM channels 0 and 2, and PWI.1 may be selected as the clock generator input for channels 1 and 3. If PWI.1 or PWI.0 are to be selected as the clock input source, then associated port bit latch (P6.5 or P6.4) must be programmed as an input (set to 1) in order to enable the alternate function of these pins. If selected, PWI.1 and PWI.0 will be sampled and synchronized to internal microcontroller timing as with other 8051 compatible timer inputs. Thus, for all clock generators there are five choices for the input clock source, which is used to drive an 8-bit auto-reloadable counter. This counter output provides a divide by N+1 selectable frequency for the PWM channel, where N is the value programmed into the counter register. When a value of 00H is programmed into the counter the input clock frequency will be passed through as the clock output to the channel's pulse generator. A value of 0FFH will result in the clock input being divided by 256 and output to the pulse generator.
12.3 PWM CLOCK GENERATORS
Within the PWM function there are four identical but separate clock generators for each of the four independent PWM channels. The clock generator function is illustrated in Figure 12-2. All four clock generators accept the four prescaler clock outputs and an external
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PWM CHANNEL CLOCK GENERATOR (1 OF 4) Figure 12-2
/1 /4 /16
1/4 PWM n FREQUENCY SELECT REGISTER EN
/64 PWI.n 8-BIT AUTO-RELOAD DIVIDE-BY-N COUNTER PWM n CLOCK
12.4 PWM PULSE GENERATORS
Figure 12-3 illustrates the pulse generators for each of the four PWM channels. Each pulse generator has an 8-bit free running timer which accepts a clock input from the associated PWM clock generator. The timer value is compared to zero and to a user selectable value. Each time that the timer value reaches zero (once every 256 clocks), the zero comparator sets a flip-flop. When the timer reaches the user-selected PWM match value, this comparator clears the flip-flop. The user-selected PWM value thereby determines the PWM duty cycle. If the channel's associated output enable bit is set (PWnOE), the output of this flip-flop is driven on the associated port 6 pin. Note that when the output enable bit is set, a full complementary push-pull driver is enabled on the corresponding pin, replacing the weak-p pull-up. When the PWnOE bit is set, the associated general purpose port bit function is logically disconnected from the pin. The zero rollover condition will cause an "interrupt" flag to be set for the associated channel. However, there is no interrupt vector in the GEM which is dedicated to any PWM channel's flag. As a result, the flag is useful only for polling purposes.
The PWM compare value can be read from or written to the PWM n SFR with the PWnT/C bit for the pair of PWM channel's cleared to 0. The PWM channel timer value can be accessed via the PWM n SFR register with the PWnT/C bit set to 1. The PWM value will be transferred from the SFR to the comparator after the next match occurs. Thus a selection value can be changed once per 256 clocks. This prevents software from creating glitches on the PWM pin. The comparator match flag indicates when a match occurs and consequently when the new value has been updated. At this time, software can change the duty cycle if desired for update on the next cycle. A PWM value of 00h will create a PWM output that is always zero. This is deglitched to prevent a simultaneous set and reset. A PWM value of FFh will create a waveform that is high for 255 of 256 clocks. A DC override bit is provided for each channel which forces a constant "1" state on the PWM output. All PWM functions described above are duplicated for all four PWM channels. For each, there is a single value SFR used to access the channel's Timer value and a PWM value registers, a timer/compare select bit, an output enable bit, a DC override bit, and a rollover flag bit.
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PWM CHANNEL BLOCK DIAGRAM Figure 12-3
REGISTER PWM n CLOCK 8-BIT TIMER
ZERO COMPARATOR
MATCH COMPARATOR
BIT PWn DC
BIT S Q R PWn OE
PWn F
PWM VALUE
BIT BIT PWn T/C PWO.n (P6.n ALT. PIN FUINCTION)
12.5 PWM SPECIAL FUNCTION REGISTERS
A total of 12 SFR's are used to control the four PWM channels. The operation of these registers are summarized below:
12.5.1 PW01CS / PW23CS - PWM 0, 1 / PWM 2, 3 Clock Select Registers
PW01CS; SFR ADDR.=0D5H BIT 7 PW0S2 BIT 6 PW0S1 BIT 5 PW0S0 BIT 4 PW0EN BIT 3 PW1S2 BIT 2 PW1S1 BIT 1 PW1S0 BIT 0 PW1EN
PW23CS; SFR ADDR.=0E5H BIT 7 PW2S2 BIT 6 PW2S1 BIT 5 PW2S0 BIT 4 PW2EN BIT 3 PW3S2 BIT 2 PW3S1 BIT 1 PW3S0 BIT 0 PW3EN
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset
PWnS2-0 - PWM n Clock Select Bits.
These three bits select one of four prescale frequencies or an external pin as the input to the PWM n frequency generator, which is then used as the clock source for PWM channel n. The bit selections operate as follows: PWnS2 0 0 0 0 1 PWnS1 0 0 1 1 X PWnS0 0 1 0 1 X
PWM n CLOCK FREQ. tMCLK* 1 tMCLK* 4 tMCLK* 16 tMCLK* 64 PWI.n pin*
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*Note: For channels 0 and 2, this selection assigns PWI.0 as the input clock source. For channels 1 and 3, this selection assigns PWI.1 as the input clock source.
clock selected by PWnS2-0. When PWnEN = 0, no clock is generated.
PWnEN - PWM n Frequency Generator Enable.
Enables the frequency generator for PWM n. When PWnEN = 1, the frequency generator operates from the
12.5.2 PW01CON / PW23CON - PWM 0, 1 / PWM 2, 3 Control Register
PW01CON; SFR ADDR.=0DDH BIT 7 PW0 F BIT 6 PW0 DC BIT 5 PW0 OE BIT 4 PW0 T/C BIT 3 PW1 F BIT 2 PW1 DC BIT 1 PW1 OE BIT 0 PW1 T/C
PW23CON; SFR ADDR.=0EDH BIT 7 PW2 F BIT 6 PW2 DC BIT 5 PW2 OE BIT 4 PW2 T/C BIT 3 PW3 F BIT 2 PW3 DC BIT 1 PW3 OE BIT 0 PW3 T/C
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset
PWnF - PWM n Flag.
Indicates that the PWM n timer has rolled over to a zero after a total of 256 counts. This bit must be cleared by software to remove the flagged condition.
complementary push-pull output drive. When cleared to 0, the PWM function is disconnected, and the normal port pin function is restored.
PWnDC - PWM n D. C. Override.
Setting this bit to a 1 forces the PWMn output to a 1 regardless of the PWM match value.
PWnT/C - PWM n Timer / Compare Value Select.
PWnT/C controls whether the read/write access of the PWM channel's value register results in access of the timer or the compare values. When PWnT/C = 1, the Timer values are accessed via the PWM n SFR. When PWnT/C = 0, the Compare values are accessed via the PWM n SFR.
PWnOE - PWM n Output Enable.
When set to a 1, PWnOE enables the PWM channel's output on the associated port pin. The port pin's normal psuedo-bi-directional function is switched over to a full
12.5.3 PWnFG - PWM n Frequency Generator Registers
PW0FG; SFR ADDR.=0D6H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
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PW1FG; SFR ADDR.=0D7H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PW2FG; SFR ADDR.=0E6H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PW3FG; SFR ADDR.=0E7H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The PWM channel n operating frequency is derived from the frequency selected by PWnS2-0 (described above) divided by the value of (PWnFG) + 1. Thus if (PWnFG) = 0, divisor is 1, (PWnFG) = 1, divisor = 2, (PWnFG) = 2, divisor = 3, etc. This value is the reload value for the frequency generator's 8-bit auto-reloadable timer. The timer's sole purpose is to generate the clocking frequency for PWM n and is not otherwise accessible. The PWM frequency will be correct after one reload has occurred.
12.5.4 PWMn - PWM n Value Registers
PWM0; SFR ADDR.=0DEH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PWM1; SFR ADDR.=0DFH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PWM2; SFR ADDR.=0EEH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
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PWM3; SFR ADDR.=0EFH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Read/Write Access: Unrestricted. Initialization: 00H on any type of reset Used to access the PWM n timer and the PWM n compare values that selects the PWM duty cycle. This register provides read/write access to both. The selection of the active function is controlled by the PWnT/C bit. When PWnT/C = 0, then PWM n register accesses the PWM compare value. Writing a new value to PWM n will then select a new duty cycle. The new value will be loaded from the register into the PWM comparator when the timer reaches the previous PWM compare value. When PWnT/C = 1, the register accesses the PWM n timer value. This allows software to monitor the progress through the duty cycle or to use PWM channel n as an 8-bit timer.
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13.0 MICROCONTROLLER POWER MANAGEMENT 13.1 POWER-DOWN / POWER-UP OPERATION
The GEM incorporates a complete on-chip power monitoring and control function which performs the following tasks:
Slow Clock mode. This mode allows the processor to continue functioning, yet save power compared with full operation mode. The GEM also features several enhancements to STOP mode that make it more useful.
13.2.1 Slow Clock Mode
The Slow Clock Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to continue to run software but to use substantially less power. During default operation, the GEM uses 4 clocks per machine cycle. Thus the instruction cycle rate is Clock / 4. At 33 MHz crystal speed, the instruction cycle speed is 8.25 MHz (33/4). In Slow Clock Mode, the microcontroller continues to operate but uses an internally divided version of the clock source. This creates a lower power state without external components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed below). The speeds are (Clock / 64) and (Clock / 1024). The microcontroller firmware is the only mechanism that can invoke the Slow Clock Mode. Table 13-1 illustrates the instruction cycle rate in Slow Clock Mode for several common crystal frequencies. Since power consumption is a direct function of operating speed, Slow Clock Mode ( / 64) eliminates most of the power consumption while still allowing a reasonable speed of processing. Slow Clock Mode ( / 1024) runs very slow and provides the lowest power consumption without stopping the CPU. This is illustrated in Table 13-2. Note that Slow Clock Mode provides a lower power condition than IDLE mode. This is because in IDLE, all clocked functions such as timers run at a rate of crystal divided by 4. Since wake-up from Slow Clock Mode is as fast as or faster than from IDLE and Slow Clock Mode allows the CPU to operate (even if doing NOPs), there is little reason to use IDLE in new designs.
* Power Fail Reset generation * Power Fail Warning interrupt
13.1.1 Microcontroller Power Fail Reset
The GEM incorporates a precision band-gap voltage reference and internal monitoring circuit to determine if VCC is out of tolerance. The power fail reset feature operates completely without the need for external components. During a power up or power down condition, the GEM's CPU and its I/O circuitry are held in a reset state for the entire time that VCC is below the VRST threshold. In addition, the VRST pin is held low so that the rest of the system can be held in a reset state during this time. When VCC rises above the VRST level during a power up condition, the internal monitor circuit manages a restart of the GEM's microcontroller as follows: First, the crystal oscillator is enabled and a delay of 65536 CPU clock cycles is executed in order to allow time for the microcontroller clock oscillator to stabilize. Then, the VRST pin is taken inactive and the microcontroller core is released from the reset state and begins code execution at the reset vector location (0000h). Software can then determine that a power-on reset has occurred by reading the Power On Reset flag (WDCON.6) which will be set to a 1. The software should clear the POR flag after reading it so that the next reset source can be properly determined.
13.2 LOW POWER OPERATING MODES
Along with the standard IDLE and power down (STOP) modes of the standard 80C52, the GEM provides the
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SLOW CLOCK MODE INSTRUCTION CYCLE RATE Table 13-1
CRYSTAL SPEED 1.8432 MHz 11.0592 MHz 22 MHz 25 MHz 33 MHz FULL SPEED (4 CLOCKS) 460.8 KHz 2.765 MHz 5.53 MHz 6.25 MHz 8.25 MHz SLOW CLOCK (64 CLOCKS) 28.8 KHz 172.8 KHz 345.6 KHz 390.6 KHz 515.6 KHz SLOW CLOCK (1024 CLOCKS) 1.8 KHz 10.8 KHz 21.6 KHz 24.4 KHz 32.2 KHz
SLOW CLOCK MODE OPERATING CURRENT ESTIMATES Table 13-2
CRYSTAL SPEED 1.8432 MHz 3.57 MHz 11.0592 MHz 16 MHz 22 MHz 25 MHz 33 MHz FULL SPEED (4 CLOCKS) 3.1 mA 5.3 mA 15.5 mA 21 mA 25.5 mA 31 mA 36 mA SLOW CLOCK (64 CLOCKS) 1.2 mA 1.6 mA 4.8 mA 7.1 mA 8.3 mA 9.7 mA 12.0 mA SLOW CLOCK (1024 CLOCKS) 1.0 mA 1.1 mA 4.0 mA 6.0 mA 6.5 mA 8.0 mA 10.0 mA
13.2.1.1 Crystaless Slow Clock Mode
A major component of power consumption in Slow Clock Mode is the crystal amplifier circuit. The GEM allows the user the option to switch CPU operation to an internal ring oscillator and turn off the crystal amplifier. The CPU would then have a clock source of approximately 4 MHz, divided by either 4, 64, or 1024. The ring oscillator as a time base is not precise and as a result software can not perform precision timing. However, this mode allows an additional saving of between 0.5 and 6.0 mA depending on the actual crystal frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a major contribution when running in Slow Clock Mode.
There are two ways of exiting Slow Clock Mode. Software can remove the condition by reversing the procedure that invoked Slow Clock Mode or hardware can (optionally) remove it. To resume operation at a divide by 4 rate under software control, simply select 4 clocks per cycle, then crystal based operation if relevant. When disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated with restarting the crystal operation. Details are described below. There are three registers containing bits that are concerned with Slow Clock Mode functions. They are Power Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h)
13.2.1.2 Slow Clock Mode Operation
Software invokes the Slow Clock Mode by setting the appropriate bits in the SFR area. The basic choices are divider speed and clock source. There are three speeds (4, 64, 1024) and two clock sources (crystal, ring). Both the decisions and the controls are separate. Software will typically select the clock speed first. Then, it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if desired.
13.2.1.3 Clock Divider
Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as follows: CD1 0 0 CD0 0 1 Cycle rate Reserved 4 clocks (default)
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1 1
0 1
64 clocks 1024 clocks
13.2.1.5 Status
Information in the Status register assists decisions about switching into Slow Clock Mode. This register contains information about the level of active interrupts and the activity on the serial ports. The GEM supports three levels of interrupt priority. These levels are Power-fail, High, and Low. Bits STATUS.7-5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority; STATUS.7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority; STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in service. Software should not rely on a lower priority level interrupt source to remove Slow Clock Mode (Switchback) when a higher level is in service. Check the current priority service level before entering Slow Clock Mode. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering Slow Clock Mode. Alternately, software can prevent an undesired exit from Slow Clock Mode by entering a low priority interrupt service level before entering Slow Clock Mode. This will prevent other low priority interrupts from causing a Switchback. Status also contains information about the state of the serial port. Serial Port Zero Receive Activity (SPRA0; STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1. Serial Port Zero Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a serial transmission. While one of these bits is set, hardware prohibits software from entering Slow Clock Mode (CD1 & CD0 are write protected) since this would corrupt the corresponding serial transmissions.
The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the clock divider choice applies to all functions including timers. Since baud rates are altered, it will be difficult to conduct serial communication while in Slow Clock Mode. There are minor restrictions on accessing the clock selection bits. The processor must be running in a 4 clock state to select either 64 (Slow Clock Mode1) or 1024 (Slow Clock Mode2) clocks. This means software cannot go directly from divide-by-64 to divide-by-1024 or visa versa. It must return to a 4 clock rate first.
13.2.1.4 Switchback
To return to a 4 clock rate from Slow Clock Mode, software can simply select the CD1 & CD0 clock control bits to the 4 clocks per cycle state. However, the GEM provides several hardware alternatives for automatic Switchback. If Switchback is enabled, then the GEM will automatically return to a 4 clock per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. A Switchback will also occur when the serial port detects the beginning of a serial start bit if the serial receiver is enabled. Note the beginning of a start bit does not generate an interrupt; this occurs on reception of a complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial reception. Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt, Switchback will occur only if the interrupt source could really generate the interrupt. For example, if INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is servicing a high priority interrupt. A serial Switchback will occur only if the serial receiver function is enabled (REN=1, SCON0.4). When SWB = 1, the user software will not be able to select a reduced clock mode if the UART is active. For example, the processor will prohibit the Slow Clock Mode by not allowing a write to CD1 and CD0 if a serial start bit arrived and SWB = 1. Since the reception of a serial start bit or an interrupt priority lockout is normally undetectable by software in an 8051, the Status register features several new flags that are useful. These are described below.
13.2.1.6 Crystal / Ring Operation
The GEM allows software to choose the clock source as an independent selection from the instruction cycle rate. The user can select crystal-based or ring oscillator- based operation under software control. Power-on reset default is the crystal (or external clock) source. The ring may save power depending on the actual crystal speed. To save still more power, software can then
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disable the crystal amplifier. This process requires two steps. Reversing the process also requires two steps. The XT/RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/RG = 1 selects the crystal. Setting XT/RG = 0 selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating the active clock source. RGMD = 0 indicates the CPU is running from the crystal. RGMD = 1 indicates it is running from the ring. When operating from the ring, disable the crystal amplifier by setting the XTOFF bit (PMR.3) to a 1. This can only be done when XT/RG = 0. When changing the clock source, the selection will take effect after a one instruction cycle delay. This applies to changes from crystal to ring and vise versa. However, this assumes that the crystal amplifier is running. In most cases, when the ring is active, software previously disabled the crystal to save power. If ring operation is being used and the system must switch to crystal operation, the crystal must first be enabled. Set the XTOFF bit to a 0. At this time, the crystal oscillation will begin. The
GEM then provides a warm-up delay to make certain that the frequency is stable. Hardware will set the XTUP bit (STATUS.4) to a 1 when the crystal is ready for use. Then software should write XT/RG to a 1 to begin operating from the crystal. Hardware prevents writing XT/RG to a 1 before XTUP = 1. The delay between XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks. Switchback has no effect on the clock source. If software selects a reduced clock divider and enables the ring, a Switchback will only restore the divider speed. The ring will remain as the time base until altered by software. If there is serial activity, Switchback usually occurs with enough time to create proper baud rates. This is not true if the crystal is off and the CPU is running from the ring. If sending a serial character that wakes the system from crystaless Slow Clock Mode, then it should be a dummy character of no importance with a subsequent delay for crystal startup. The flow chart in Figure 13-1 illustrates a typical decision set associated with Slow Clock Mode.
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Table 13-3 is a summary of the bits relating to Slow Clock Mode and its operation.
ENTERING / EXITING SLOW CLOCK MODE Figure 13-1
ENTER SLOW CLOCK MODE EXITING SLOW CLOCK MODE
ALLOW HARDWARE TO CAUSE A SWITCHBACK ? Y
N SOFTWARE DECIDES TO EXIT SWB=1 AND EXTERNAL ACTIVITY OCCURS
CD1, CD0 = 01 FOR 4 SET SWB=1
HARDWARE AUTOMATICALLY SWITCHES CD1, CD0
CHECK STATUS=0 ?
N CHECK AND CLEAR IMPENDING ACTIVITY
CHECK STATUS=0 ?
N
Y
Y
DONE
INVOKE SLOW CLOCK MODE CLOCK SPEED = 64 OR 1024 CD1, CD0=10 FOR 64 CD1, CD0=11 FOR 1024
XTOFF = 1 ?
N
Y OPERATE WITHOUT CRYSTAL ? N XTOFF = 0 DONE
XT/RG=1
DONE
Y
XT/RG=0 XTUP = 1 ?
N
Y DISABLE CRYSTAL? (NO FAST SWITCH TO XTAL) N XT/RG=1
Y
DONE DONE
XTOFF = 1
LOWEST POWER OPERATING STATE
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SLOW CLOCK MODE CONTROL AND STATUS BIT SUMMARY Table 13-3
BIT NAME XT/RG LOCATION EXIF.3 FUNCTION Control. XT/RG=1, runs from crystal or external clock; XT/RG=0, runs from internal Ring Oscillator. Status. RGMD=1, CPU clock = ring; RGMD=0, CPU clock = crystal. Control. CD1,0=01, 4 clocks; CS1,0=10, Slow Clock Mode 1; CD1,0=11, Slow Clock Mode 2. Control. SWB=1, hardware invokes switchback to 4 clocks, SWB=0, no hardware switchback. Control. Disables crystal operation after ring is selected. Status. 1 indicates a power-fail interrupt in service. Status. 1 indicates high priority interrupt in service. Status. 1 indicates low priority interrupt in service. Status. 1 indicates that the crystal has stabilized. Status. Serial transmission on serial port 0. Status. Serial word reception on serial port 0. RESET X WRITE ACCESS 0 to 1 only when XTUP=1 and XTOFF=0 None Write CD1,0=10 or 11 only from CD1,0=01 Unrestricted
RGMD CD1, CD0
EXIF.2 PMR.7, PMR.6 PMR.5
0 0, 1
SWB
0
XTOFF PIP HIP LIP XTUP SPTA0 SPRA0
PMR.3 STATUS.7 STATUS.6 STATUS.5 STATUS.4 STATUS.1 STATUS.0
0 0 0 0 1 0 0
1 only when XT/RG=0 None None None None None None
13.2.2 IDLE MODE
Setting the lsb of the Power Control register (PCON; 87h) invokes the IDLE mode. IDLE will leave internal clocks, serial port and timers running. Power consumption drops because the memory is not being accessed. Since clocks are running, the IDLE power consumption is a function of crystal frequency. It should be approximately 1/2 of the operational power at a given frequency. The CPU can exit the IDLE state with any interrupt or a reset. IDLE is available for backward software compatibility. The system can now reduce power consumption to below IDLE levels by using Slow Clock Mode / 64 or / 1024 and running NOPs .
serial port, watchdog) are not useful since they require clocking activity. The GEM provides two enhancements to the STOP mode. The GEM incorporates a band-gap reference which is used to determine Power-fail Interrupt and Reset thresholds and to provide a reference for the on- chip A/D converter. The default state is that the band- gap reference is off while in STOP mode. This allows the extremely low power state mentioned above. A user can optionally choose to have the band-gap enabled during STOP mode. With the band-gap reference enabled, PFI and Power-fail reset are functional and are valid means for leaving STOP mode. This allows software to detect and compensate for a brown-out or power supply sag, even when in STOP mode. In this condition, ICC will be approximately 100 uA compared with 1 uA with the band-gap off. If a user does not require a Power-fail Reset or Interrupt while in STOP mode, the band-gap can remain disabled. In addition, the VRST output pin will be at a low (active) level. In this manner, the GEM and the rest of
13.2.3 STOP MODE AND ENHANCEMENTS
Setting bit 1 of the Power Control register (PCON; 87h) invokes the STOP mode. STOP mode is the lowest power state since it turns off all internal clocking. The ICC of a standard STOP mode is approximately 1 uA (but is specified in the Electrical Specifications). The CPU will exit STOP mode from an external interrupt or a reset condition. Internally generated interrupts (timer,
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the system under the control of the VRST pin is prepared for a power down condition should it occur while STOP with the band-gap disabled is in effect. The control of the band-gap reference is located in the Extended Interrupt Flag register (EXIF; 91h). Setting BGS (EXIF.0) to a 1 will keep the band-gap reference enabled during STOP mode. The default or reset condition is with the bit at a logic 0. This results in the band- gap being off during STOP mode. Note that this bit has no control of the reference during full power, Slow Clock Mode, or IDLE modes. The second feature allows an additional power saving option while also making STOP easier to use. This is the ability to start instantly when exiting STOP mode. It is the internal ring oscillator that provides this feature. This ring can be a clock source when exiting STOP mode in response to an interrupt. The benefit of the ring oscillator is as follows. Using STOP mode turns off the crystal oscillator and all internal clocks to save power. This requires that the oscillator be restarted when exiting STOP mode. Actual start-up time is crystal dependent, but is normally at least 4 mS. A common recommendation is 10 mS. In an application that will wake-up, perform a short operation, then return to sleep, the crystal start-up can be longer than the real transaction. However, the ring oscillator will start instantly. Running from the ring, the user can
perform a simple operation and return to sleep in less time than it takes to start the crystal. If a user selects the ring to provide the start-up clock and the processor remains running, hardware will automatically switch to the crystal once a power-on reset interval (65536 clocks) has expired. Hardware uses this value to assure proper crystal start even though power is not being cycled. The ring oscillator runs at approximately 4 MHz but will not be a precise value. Do not conduct real-time precision operations (including serial communication) during this ring period. Figure 13-2 shows how the operation would compare when using the ring, and when starting up normally. The default state is to exit STOP mode without using the ring oscillator. The RGSL - Ring Select bit at EXIF.1 (EXIF; 91h) controls this function. When RGSL = 1, the CPU will use the ring oscillator to exit STOP mode quickly. As mentioned above, the processor will automatically switch from the ring to the crystal after a delay of 65,536 crystal clocks. For a 3.57 MHz crystal, this is approximately 18 mS. The processor sets a flag called RGMD- Ring Mode, located at EXIF.2, that tells software that the ring is being used. The bit will be a logic 1 when the ring is in use. Attempt no serial communication or precision timing while this bit is set, since the operating frequency is not precise.
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RING OSCILLATOR EXIT FROM STOP MODE Figure 13-2
STOP MODE WITHOUT RING STARTUP
4-10 ms CRYSTAL OSCILLATION uC OPERATING uC OPERATING
uC ENTERS STOP MODE
INTERRUPT; CLOCK STARTS
POWER
STOP MODE WITH RING STARTUP
uC OPERATING
RING OSCILLATION
POWER
DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN 18 mS TO COMPLETE.
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IIIII IIIII
IIIII
CRYSTAL OSCILLATION
uC ENTERS STOP MODE
INTERRUPT; RING STARTS
IIIIIIII IIIIIIII
CLOCK STABLE uC OPERATING uC ENTERS STOP MODE POWER SAVED
IIIII IIIII
uC ENTERS STOP MODE
DS80CH10
14.0 +5.0V ELECTRICAL SPECIFICATIONS 14.1 ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
14.2 MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Power Fail Warning Minimum Operating Voltage Supply Current Active Mode @ 33 MHz Supply Current Idle Mode @ 33 MHz Supply Current Stop Mode Band-gap Disabled Supply Current Stop Mode Band-gap Enabled Input Low Level (All except KSI.7-0, SDA, and SCL pins) Input Low Level (KSI.7-0 pins) Input Low Level (SDA, SCL pins) Input High Level (All except XTAL1, RST, SDA, and SCL pins) Input High Level (XTAL1 and RST) Input High Level (SDA, SCL) Output Low Voltage: Ports 1.0, Ports 1.1, Ports 3, 4, 6, 7, 8, and 9 @ IOL=1.6 mA Output Low Voltage: Ports 0 and 2, ALE, PSEN @ IOL=3.2 mA Output Low Voltage: Ports 1.2 - Ports 1.7, Port 5 @ IOL=8 mA Output High Voltage: Ports 1.0, Ports 1.1, Ports 2, 3, 6 (PWM disabled), 7, ALE, PSEN @ IOH= -50 A SYMBOL VCC VPFW VRST ICC IIDLE ISTOP ISPBG VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 -0.3 -0.3 -0.3 2.0 3.5 3.5 MIN 4.5 4.30 4.0 TYP 5.0 4.38 4.13 50 10 1 100
(0C to 70C; VCC=5.0 10%)
MAX 5.5 4.55 4.30 UNITS V V V mA mA A A +0.8 +0.6 +0.3 VCC VCC+0.3 VCC+0.3 VCC+0.3 V V V V V V NOTES 1 1 1 2 3 4 4 1 1 1 1 1 1
VOL1 VOL2 VOL3
0.15 0.15 0.15
0.45 0.45 0.8
V V V
1 1 1
VOH1
2.4
V
1, 6
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14.2 MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS (cont'd)
Output High Voltage: Ports 1.0, Ports 1.1, Ports 2, 3, 4, 7 transition mode, and Ports 6.0-Ports 6.3 pins with PWM channel enabled @ IOH= -1.5 mA Output High Voltage: Port 0 (bus mode) @ IOH = -8 mA Input Low Current: Ports 1.0, Ports 1.1, Ports 2, 3, 6 (PWM disabled), 7 @ 0.45V Transition Current from 1 to 0 Ports 1.0, Ports 1.1, Ports 2, 3, 6 (PWM disabled), 7 @ 2V Input Leakage: Port 0 pins (I/O Mode) and EA Input Leakage: Port 0 pins (Bus Mode) RST Pull-down Resistance Internal Port Resistors (KSI7-0)
(0C to 70C; VCC=5.0 10%)
VOH2
2.4
V
1, 7
VOH3
2.4
V
1, 5
IIL
-55
A
ITL IL IL RRST RP -10 -300 50 4
-650 +10 +300 200 20
A A A K K
8 10 9
NOTES
1. All voltages are referenced to ground. 2. Active current is measured with a 33 MHz clock source driving XTAL1, VCC=RST=+5.5V. All other pins disconnected. 3. Idle mode current is measured with a 33 MHz clock source driving XTAL1, VCC=+5.5V, RST at ground, all other pins disconnected. 4. Stop mode current measured with XTAL1 and RST grounded, VCC=+5.5V, all other pins disconnected. This value is not guaranteed. Users that are sensitive to this specification should contact Dallas Semiconductor for more information. 5. This specification applies to Port 0 when external memory is accessed. 6. RST=VCC. This condition mimics operation of pins in I/O mode. Port 0 is tristated in reset and when at a logic high state during I/O mode. 7. During a 0 to 1 transition, a one-shot drives the ports hard for two oscillator clock cycles. This measurement reflects port in transition mode. In addition, this specification applies to any of the Port 6.0-Port 6.3 pins when the associated PWM channel is enabled. 8. Ports 1, 2, and 3 source transition current when being pulled down externally. Current reaches its maximum at approximately 2V. 9. 0.45020299 80/94
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14.3 MICROCONTROLLER AC ELECTRICAL CHARACTERISTICS 14.3.1 EXTERNAL PROGRAM MEMORY CHARACTERISTICS
33 MHz PARAMETER Oscillator Frequency ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float after PSEN Port 0 Address to Valid Instruction In Port 2 Address to Valid Instruction In PSEN Low to Address Float SYMBOL 1/tCLCL tLHLL tAVLL tLLAX1 tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV1 tAVIV2 tPLAZ 0 25 70 81 0 10 56 41 0 tCLCL-5 3tCLCL-20 3.5tCLCL-25 0 MIN 0 40 10 10 56 (tCLCL/2)-5 2tCLCL-5 2tCLCL-20 MAX 33 MIN 0 (3tCLCL/2)-5 (tCLCL/2)-5 (tCLCL/2)-5 2.5tCLCL-20
(0C to 70C; VCC=5.0 10%)
VARIABLE CLOCK MAX 33 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns
NOTES:
1. All signals rated over operating temperature. 2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF. 3. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not damage the parts, but will cause an increase in operating current.
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14.3.2 MOVX USING STRETCH MEMORY CYCLES
VARIABLE CLOCK PARAMETER Data Access ALE Pulse Width Address Hold after ALE Low for MOVX Write RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold after Read Data Float after Read ALE Low to Valid Data In Port 0 Address to Valid Data In Port 2 Address to Valid Data In ALE Low to RD or WR Low Port 0 Address to RD or WR Low Port 2 Address to RD or WR Low Data Valid to WR Transition Data Hold after Write RD Low to Address Float RD or WR High to ALE High SYMBOL tLHLL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV1 tAVDV2 tLLWL tAVWL1 tAVWL2 tQVWX tWHQX tRLAZ tWHLH 0 tCLCL-5 0.5tCLCL-5 tCLCL-5 tCLCL-5 2tCLCL-5 1.5tCLCL-5 2.5tCLCL-5 -5 tCLCL-5 2tCLCL-5 0 tCLCL-5 2tCLCL-5 MIN 1.5tCLCL-5 2tCLCL-5 0.5tCLCL-5 tCLCL-5 2tCLCL-5 tMCS-10 2tCLCL-5 tMCS-10 MAX
(0C to 70C; VCC=5.0 10%)
UNITS ns ns ns ns 2tCLCL-20 tMCS-20 ns ns ns ns ns ns ns ns ns ns ns -0.5tCLCL-5 10 tCLCL+5 ns ns tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 STRETCH tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0
2.5tCLCL-20 tMCS+tCLCL-40 3tCLCL-20 tMCS+1.5tCLCL-20 3.5tCLCL-20 tMCS+2tCLCL-20 0.5tCLCL+5 tCLCL+5
NOTE:
tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection. M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 MOVX CYCLES 2 machine cycles 3 machine cycles (default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles tMCS 0 4 tCLCL 8 tCLCL 12 tCLCL 16 tCLCL 20 tCLCL 24 tCLCL 28 tCLCL
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14.3.3 EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCH tCHCL MIN 15 15 TYP
(0C to 70C; VCC=5.0 10%)
MAX UNITS ns ns 10 10 ns ns NOTES
14.3.4 SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER Serial Port Clock Cycle Time SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Setup to Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Hold from Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Input Data Hold after Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Clock Rising Edge to Input Data Valid SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle SYMBOL tXLXL 12tCLCL 4tCLCL tQVXH 10tCLCL 3tCLCL tXHQX 2tCLCL tCLCL tXHDX tCLCL tCLCL tXHDV 11tCLCL 3tCLCL MIN TYP
(0C to 70C; VCC=5.0 10%)
MAX UNITS ns ns ns ns ns ns ns ns NOTES
ns ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t A C D H L I P Q R V W X Z Time Address Clock Input data Logic level high Logic level low Instruction PSEN Output data RD signal Valid WR signal No longer a valid logic level Tri-state
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14.3.5 POWER CYCLE TIMING CHARACTERISTICS
PARAMETER Cycle Start-up Time Power-on Reset Delay SYMBOL tCSU tPOR MIN TYP 1.8
(0C to 70C; VCC=5.0 10%)
MAX UNITS ms 65536 tCLCL NOTES 1 2
NOTES:
1. Start-up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crystal manufactured by Fox. 2. Reset delay is a synchronous counter of crystal oscillations after crystal start-up. At 33 MHz, this time is 1.99 ms.
EXTERNAL PROGRAM MEMORY READ CYCLE Figure 14-1
tLHLL tLLIV ALE tAVLL tPLPH tPLIV PSEN
tLLPL tPXIZ tPLAZ tLLAX1 tPXIX
PORT 0
ADDRESS A0-A7 tAVIV1 tAVIV2
INSTRUCTION IN
ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
ADDRESS A8-A15 OUT
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EXTERNAL DATA MEMORY READ CYCLE Figure 14-2
tLHLL2 tLLDV
ALE tWHLH tLLWL PSEN RD tLLAX1 tRLRH tAVLL tRLAZ tAVWL1 tRLDV tRHDZ tRHDX
PORT 0
INSTRUCTION IN
ADDRESS A0-A7
DATA IN
ADDRESS A0-A7
tAVDV1 tAVDV2 PORT 2
ADDRESS A8-A15 OUT
tAVWL2
EXTERNAL DATA MEMORY WRITE CYCLE Figure 14-3
ALE tWHLH tLLWL PSEN tLLAX2 tWLWH WR tAVLL tWHQX
PORT 0
INSTRUCTION IN
ADDRESS A0-A7 tQVWX tAVWL1
DATA OUT
ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
tAVWL2
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DATA MEMORY WRITE WITH STRETCH=1 Figure 14-4
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle MOVX Instruction C1 CLK C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 Third Machine Cycle Next Instruction Machine Cycle
ALE
PSEN WR
PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Instruction Address
Next Instr. Address MOVX Instruction Next Instruction Read A8-A15
MOVX Data Address
MOVX Data
PORT 2
A8-A15
A8-A15
A8-A15
DATA MEMORY WRITE WITH STRETCH=2 Figure 14-5
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle Third Machine Cycle Fourth Machine Cycle Next Instruction Machine Cycle C4 C1 C2 C3 C4
MOVX Instruction C1 CLK C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3
ALE
PSEN WR
PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Instruction Address
Next Instr. Address MOVX Instruction Next Instruction Read A8-A15
MOVX Data Address
MOVX Data
PORT 2
A8-A15
A8-A15 FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE=2
A8-A15
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DS80CH10
EXTERNAL CLOCK DRIVE Figure 14-6
tCLCL
tCHCX XTAL1 tCHCL tCLCX tCLCH
SERIAL PORT MODE 0 TIMING Figure 14-7
SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4
ALE PSEN tQVXH WRITE TO SBUF RXD DATA OUT TXD CLOCK tXLXL TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD CLOCK RI tXHDV tXHDX
D0 D1 D2 D3 D4 D5 D6 D7 D0
tXHQX
D1 D2 D3 D4 D5 D6 D7
TRANSMIT
RECEIVE
SERIAL PORT 0 (SYNCHRONOUS MODE) SM2=0=>TXD CLOCK=XTAL/12
ALE PSEN 1/(XTAL FREQ/12) WRITE TO SBUF TRANSMIT RXD DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RECEIVE RXD DATA IN TXD CLOCK RI
D0 D1 D6 D7 D0 D1 D6 D7
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DS80CH10
POWER CYCLE TIMING Figure 14-8
VCC VPFW VRST
VSS
INTERRUPT SERVICE ROUTINE tCSU
XTAL1 tPOR
INTERNAL RESET
14.4 SYSTEM INTERFACE DC ELECTRICAL CHARACTERISTICS
PARAMETER Power Supply Voltage Average HVCC Power Supply Current Input Logic 1: Input Logic 0: Input Leakage Current (Any Input) Output Logic 1 Voltage @ IOH = -1.0 mA Output Logic 0 Voltage @ IOL = +2.1 mA Power Fail Trip Point I/O Leakage SYMBOL HVCC HICC1 VIH VIL IIL VOH VOL VPF ILO 4.25 -1 4.37 2.8 -0.3 -1 2.4 MIN 4.5 TYP 5.0 7
(0C to 70C; VCC=5.0 10%)
MAX 5.5 15 VCC +0.3 0.6 +1 UNITS V mA V V A V 0.4 4.5 +1 V V A 4 NOTES 1 2, 3 1, 6 1, 6 6 7 7
NOTES:
1. All voltages referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Applies to the SD0-SD7 pins, when each are in a high impedance state. 5. Measured with a load of 50 pF + 1 TTL gate.
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DS80CH10
6. Applies to system interface inputs which are powered via the HVCC supply: A0, IOR, KBCS, IOW, PMCS, and SD7-SD0. 7. Applies to system interface outputs which are powered via the HVCC supply: KBOBF, SMI.
14.5 HOST I/F AC TIMING CHARACTERISTICS
PARAMETER Cycle Time Input Rise and Fall Time Chip Select, A0 Setup Time Before IOR, IOW IOR, IOW Low Time IOR, IOW High Time Delay From IOR to Data Data Hold Time After IOR Data Turn Off Time After IOR Data Setup Time to IOW Data Hold Time From IOW Chip Select, A0 Hold From IOR, IOW SYMBOL tCYC tR, tF tCIO tIOL tIOH tIRD tIRDH tIRDZ tIWDS tIWDH tIOCH 45 0 20 5 10 50 80 MIN 160 TYP
(0C to 70C; VCC=5.0 10%)
MAX DC 15 UNITS ns ns ns ns ns 50 ns ns 25 ns ns ns ns NOTES
BUS TIMING FOR WRITE CYCLE TO HOST I/F REGISTERS Figure 14-9
tCYC KBCS, PMCS
A0 tCIO IOW tIOL tIOCH tIWDS tIWDH SD7-SD0 (INPUT) tIOH
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DS80CH10
BUS TIMING FOR READ CYCLE TO HOST I/F REGISTERS Figure 14-10
tCYC KBCS, PMCS
A0 tCIO IOR tIOL tIOCH tIRD tIRDH SD7-SD0 (OUTPUT) tIRDZ tIOH
OUTPUT LOAD Figure 14-11
VCC = +5.0V
1.8K DEVICE UNDER TEST 50 pF
1K
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DS80CH10
14.6 2-WIRE AC TIMING CHARACTERISTICS
PARAMETER START Condition Hold Time SCL Low Time SCL High Time SCL, SDA Rise Time SCL, SDA Fall Time Data Setup Time Data Hold Time Repeated START Setup Time Repeated STOP Setup Time Bus Free Time SYMBOL tSTAH tSCL tSCH tSR tSF t2DS t2DH tRSTA tRSTO t2BF INPUT > 14 tCLK (4) > 16 tCLK (4) > 14 tCLK (4) < 300 ns(1) < 300 ns(3) > 100 ns > 0 ns > 14 tCLK (4) > 14 tCLK (4) > 14 tCLK (4)
(0C to 70C; VCC=5.0 10%)
OUTPUT > 1.0 s(1) > 1.3 s(1) > 0.6 s(1) - (2) < 300 ns > 250 ns(1) > 8 tCLK - tSF (4) > 600 ns(1) > 600 ns(1) > 1.3 s(1)
NOTES:
1. At 400Kbps. For other bit rates this value is multiplied by 400 / f2W. 2. Determined by the external bus line capacitance and the external bus line pull-up resistor; this must be < 300 ns @ 400Kbps. 3. Spikes on the SDA and SCL lines with a duration of less than 50 ns will be filtered out. Maximum capacitance on either SDA and SCL = 400 pF. 4. Where tCLK is the period of the XTAL oscillator and the instruction cycle rate is set to 4 clocks (default). The frequency of the XTAL oscillator should be greater than 5 MHz for 400Kbps operation.
2-WIRE SERIAL I/O TIMING Figure 14-12
tSF tSR tRSTO
SDA tSTAH tSR SCL t2DS tSCL tSCH t2DS tSF t2DH tRSTA t2BF t2DS
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DS80CH10
14.7 MOUSE/DETACHED KEYBOARD SERIAL TIMING CHARACTERISTICS
PARAMETER "x"DIO, CLK Rise, Fall Time "x"CLK Low Time "x"CLK High Time "x"DIO Input Data Setup Time to Falling Clock "x"DIO Input Data Hold Time From Falling Clock "x"DIO Output Data Delay From Rising Clock SYMBOL tXR, tXF tXCL tXCH tXDS tXDH tXDD 50 50 2tCLCL 0 MIN TYP
(0C to 70C; VCC=5.0 10%)
MAX TBD UNITS ns ns ns ns ns 2tCLCL ns NOTES
NOTE: X = MS for mouse and DK for detached keyboard.
MOUSE/DETACHED KEYBOARD I/F TIMING Figure 14-13
DATA INPUT
tXF
tXR
xDIO tXDS tXF xCLK tXR
START BIT tXDH tXDS
DO tXDH
PARITY
STOP
tXCL
tXCH
DATA OUTPUT tXF tXR
xDIO
START BIT
DO tXDD
PARITY
STOP
tXR xCLK
tXF
tXCL
tXCH
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DS80CH10
14.8
A/D CONVERTER SPECIFICATIONS
14.8.1 ABSOLUTE MAXIMUM RATINGS
PARAMETER Analog Supply Voltage SYMBOL AVCC AGND Analog Inputs (Referred to VCC, GND) VREF+, VREF-, AIN.7- AIN.0 VREF+, VREF-, AIN.7- AIN.0 MIN VCC -0.2V GND-0.2 TYP MAX VCC +0.2 GND +0.2 UNITS V V NOTES
GND-0.2
VCC +0.2
V
Analog Inputs (Referred to AVCC, AGND)
AGND -0.2
AVCC+0.2
V
14.8.2 A/D ELECTRICAL CHARACTERISTICS
PARAMETER Analog Supply Current Analog Power Down Mode Current Analog Input Voltage Ladder Resistance Analog Input Capacitance Sampling Time Conversion Time Stabilization Time Transfer Characteristics: Resolution Differential non-linearity Integral non-linearity I l li i O Offset Error Gain Error Crosstalk between A/D input pins
(0C to 70C; VCC=AVCC =5.0 10% AGND = GND = 0V)
SYMBOL AICC AICCPD VAIN RREF CIN tADS tADC tAD 8 EDL EIL EOS EG ECT 10 + 0.3 + 0.2 + 0.25 + 0.25 + 0.75 + 1.0 + 1.0 + 1.0 -60 5 16 VRL 11 19 10 MIN TYP 600 150 VRH 27 15 MAX UNITS A A V K pF s s s Bits LSB LSB LSB % dB 1 1, 2 4 NOTES
NOTES:
1. ACLK = 1 s. 2. A complete conversion cycle requires 16 ACLK periods, including five input sampling periods. 3. Relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. 4. Stabilization time is defined as the time required for the A/D circuitry to stabilize after ADON is set to A logic "1".
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DS80CH10
128-PIN TQFP
PKG DIM A A1 A2 B C D D1 E E1 e L
128-PIN MIN - 0.05 1.35 0.17 0.09 21.80 MAX 1.60 - 1.45 0.27 0.20 22.20
20.00 BSC 15.80 16.20
14.00 BSC 0.50 BSC 0.45 0.75
56-G4011-000
020299 94/94

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