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| Memory ICs 8k x 8 Bit SRAM BR6265BF-N10SL The BR6265BF-N10SL is an 8192 word x 8 bit CMOS static RAM. It runs on a 5V single power supply, and input can be directed coupled with TTL. Current dissipation in the non-selected state is extremely low at 20A (max.), and memory information can be retained even at a low voltage of 2V, making this product ideal for battery backup operations. Both the access and cycle timing are 100ns, facilitating timing design. *Applications General-purpose *Featureswith an 8192 x 8 bit configuration. 1) SRAM 2) 5V single power supply voltage with 10% fluctuation tolerance. 3) High speed access time of 100ns. 4) TTL compatible input / output. 5) Input and output use the same pin, and there are 3 output states. 6) No clock is necessary (asynchronous static circuit). 7) Input and output data are in the same phase. 8) Low power dissipation. *Block diagram A8 A5 A6 A7 A12 A9 A11 I / O0 INPUT DATA CONTROL I / O7 ROW ROW ADDRESS DECORDER BUFFER 65536BIT (128 x 512) MEMORY CELL ARRAY COLUMN SWITCH COLUMN DECODER OUTPUT DATA CONTROL COLUMN ADDRESS BUFFER A0 A1 A2 A3 A4 A10 CE1 CE2 OE WE CONTROL BUFFER 1 Memory ICs BR6265BF-N10SL *Absolute maximum ratings (Ta = 25C) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature I / O voltage Symbol VCC Pd Topr Tstg VI Limits - 0.51 ~ + 7.0 8502 0 ~ 70 - 55 ~ + 125 - 0.5 ~ VCC + 0.5 Unit V mW C C V 1 At pulse width of 50 ns : - 3.0V (min.) 2 Reduced by 8.5mW for each increase in Ta of 1C over 25C. *Recommended operating conditions (Ta = 25C) Parameter Power supply voltage Input high level voltage Input low level voltage Ambient temperature Symbol VCC VIH VIL Ta Min. 4.5 2.2 - 0.3 0 Typ. 5.0 -- -- -- Max. 5.5 VCC + 0.5 0.8 70 Unit V V V C *Pin descriptions Pin No. 1 2 ~ 10, 21, 23 ~ 25 11 ~ 13, 15 ~ 19 20 26 22 27 28 14 Pin name NC A0 ~ A12 I / O0 ~ I / O7 CE1 CE2 OE WE VCC VSS Internal chip and not connected 8192-byte memory address input 8-bit data I / O Chip enable control input Chip enable control input Output enable control input Write enable control input 5V 10%power supply Reference voltage for all input / output, 0V Function 2 Memory ICs BR6265BF-N10SL *Electrical characteristics (unless otherwise noted, Ta = 0 to 70C, VCC = 5V 10%) Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Symbol VIL VIH VOL VOH ILI ILO ICCA1 Average operating current ICCA2 ISB Standby current ISB1 ISB2 -- -- -- -- -- -- -- -- 10 3 20 20 mA mA A A Min. - 0.31 2.2 0 2.4 VCC x 0.8 -- -- -- Typ. -- -- -- -- -- -- -- -- Max. 0.8 VCC + 0.5 0.4 VCC VCC 1 1 40 Unit V V V V V A A mA IOL = 2.1mA IOH = - 1.0mA IOH = - 0.1mA VIN = 0 ~ VCC VOUT = 0 ~ VCC CE1 = VIL, CE2 = VIH, I / O: OPEN Minimum cycle time CE1 = VIL, CE2 = VIH, I / O: OPEN f = 1MHz CE1 = VIH or CE2 = VIL CE1 CE2 CE2 VCC - 0.2V, VCC - 0.2V or CE2 0.2V 0.2V Conditions -- -- Measurement circuit -- -- Fig.1 Fig.2 -- Fig.3 Fig.4 Fig.5 Fig.5 -- Fig.6 -- 1 At input voltage pulse width of 50 ns or less : - 3.0V 3 Memory ICs BR6265BF-N10SL *Measurement circuits VCC VCC VCC VCC I / O0 ~ I / O7 VSS VSS V VOL V VOH 2.1mA I / O0 ~ I / O7 1.0mA Data sets all output to LOW (Data 00) Data sets all output to HIGH (Data FF) Fig. 1 Output low level voltage measurement circuit Fig. 2 Output high level voltage measurement circuit VCC VCC VCC IL1 A VCC A0 ~ A12 CE1, CE2 VSS VCC OE I / O0 ~ I / O7 VSS ILO A VIN = 0 ~ VCC VOUT = 0 ~ VCC Fig. 3 Input leakage measurement circuit Fig. 4 Output leakage current measurement circuit VCC VCC VIH A ICCA1, ICCA2 VIH A ISB, 1 WE CE2 CE1 OE VCC I / O0 ~ I / O7 SW OPEN q VCC VIL or VIH (Min. cycle) CE1 CE2 I / O0 ~ I / O7 A0 ~ A12 VSS OPEN VCC or GND A0 ~ A12 VSS w VIL or VIH (1MHz cycle) VIL q : Average operating current ICCA1 w : Average operating current ICCA2 Fig. 5 Current dissipation measurement circuit Fig. 6 Standby current measurement circuit 4 Memory ICs BR6265BF-N10SL *Operating modes Control pin OE X X H L X CE1 H X L L L CE2 X L H H H WE X X H H L Mode Wait state Wait state Output disabled Read Write I/O High impedance High impedance High impedance Data output Data output Power dissipation Standby state Standby state Operating state Operating state Operating state X : Either VIL or VIH to *AC test conditions: (Ta = 02.4V70C, VCC = 5V 10%) Input pulse level 0.8 to Input rise / fall time : 5ns I / O timing level : 1.5V Output load : 1 TTL gate and CL = 100pF *Read cycle Parameter Read cycle time Address access time CE1 access time CE2 access time OE access time Output hold time CE1 output set time CE2 output set time OE output reset time CE1 deselect output floating CE2 deselect output floating OE disable output floating Symbol tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ Min. 100 -- -- -- -- 10 10 10 5 -- -- -- Max. -- 100 100 100 40 -- -- -- -- 35 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns 5 Memory ICs BR6265BF-N10SL *Read cycle timing chart 1 (CE1 = OE = VIL, CE2 = WE = VIH) tRC Address tAA tOH Dout Previous Valid Data Valid Data *Read cycle timing chart 2 (WE = VIH) Address Fig.7 tRC tAA CE1 tCO1 tHZ1 tLZ1 CE2 tCO2 tHZ2 tLZ2 OE tOHZ tOE tOLZ Dout High Impedance Valid Data Fgi.8 6 Memory ICs BR6265BF-N10SL *Write cycle Parameter Write cycle time Chip select time Address valid time Address setup time Write pulse width WE output delay time CE1, CE2 output delay time WE * output floating time Input data set time Input data hold time WE * output set time Symbol tWC tCW tAW tAS tWP tWR tWR1 tWHZ tDW tDH tOW Min. 100 80 80 0 60 0 0 -- 40 0 5 Max. -- -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns *Write cycle timing chart 1 (WE control) tWC Address tAW tWR OE CE1 tCW CE2 tCW tAS tWP WE tDW DIN tWHZ DOUT Valid Data tDH tOW High Impedance Fig.9 7 Memory ICs BR6265BF-N10SL *Write cycle timing chart 2 (CE1 control) tWC Address tAW OE tAS tCW CE1 tWR1 CE2 tWP WE tDW tDH DIN tWHZ tLZ1 Valid Data DOUT Fig.10 8 Memory ICs BR6265BF-N10SL *Write cycle timing chart 3 (CE2 control) tWC Address tAW OE CE1 tAS tCW tWR1 CE2 tWP WE tDW tDH DIN Valid Data tWHZ tLZ2 DOUT Fig.11 While the I / O pin is in output state, input signals should not be applled which are in The contents noted in this document may fall under the jurisdiction of services reverse phase to the output. pertaining to overseas exchange rates and overseas control regulations (services pertaining to design, construction, specifications), and may requlre special handiing. 9 Memory ICs BR6265BF-N10SL *Data retention characteristics at low power supply voltage (Ta = 0 to 70C): SL version products Parameter Data retention power supply voltage Data retention current CS data retention time Operating recovery time Symbol VDR ICCDR tCDR tR Min. 2.0 -- 0 5 Typ. -- -- -- -- Max. 5.5 10 -- -- Unit V A ns ms Conditions CE1 VCC - 0.2V, CE2 or CE2 0.2V VCC - 0.2V CE1 VCC - 0.2V, CE2 VCC - 0.2V or CE2 0.2V, VCC = 3.0V -- -- 1A (Max.), when Ta = 0 ~ 40C *Data retention waveform at low power supply voltage Data Retention Mode VCC 4.5V VDR tCDR tR 4.5V CE1 CE1 2.2V VDR - 0.2V 2.2V Data Retention Mode VCC 4.5V VDR 4.5V tCDR tR 0.4V CE2 CE2 0.2V 0.4V Fig.12 10 Memory ICs BR6265BF-N10SL *External dimensions (Units: mm) 18.0 0.2 28 11.8 0.3 8.4 0.2 15 2.55 0.10 1 0.20 14 1.27 0.40 0.10 0.5Min. 0.15 0.1 0.10 SOP-N28 11 |
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