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CDB4392 Evaluation Board for CS4392
Features
l Demonstrates
Description
The CDB4392 evaluation board is an excellent means for quickly evaluating the CS4392 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4392 (for control port mode only) and a power supply. Analog line level outputs are provided via RCA phono jacks. The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4392 Evaluation Board
recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 compatible digital audio l Digital and analog patch areas l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system
I/O for Clocks and Data
Control Port Channel A Output and Mute
CS8414 Digital Audio Interface
CS4392 Channel B Output and Mute
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
MAY `01 DS459DB1 1
CDB4392
TABLE OF CONTENTS
1. CDB4392 SYSTEM OVERVIEW .............................................................................................. 3 2. CS4392 DIGITAL TO ANALOG CONVERTER ........................................................................ 3 3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3 4. CS8414 DATA FORMAT .......................................................................................................... 3 5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 4 6. POWER SUPPLY CIRCUITRY ................................................................................................. 4 7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4 8. CONTROL PORT SOFTWARE ................................................................................................ 4 9. DSD OPERATION .................................................................................................................... 4 10. ANALOG OUTPUT FILTER .................................................................................................. 5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 8 Figure 2. CS4392 and Level Shifters .............................................................................................. 9 Figure 3. Channel A Selectable Instrumentation Amplifier............................................................ 10 Figure 4. Channel B Selectable Instrumentation Amplifier............................................................ 11 Figure 5. Channel A Audio Output and Mute Circuit ..................................................................... 12 Figure 6. Channel B Audio Output and Mute Circuit .................................................................... 13 Figure 7. CS8414 Digital Audio Receiver...................................................................................... 14 Figure 8. I/O for Clocks and Data.................................................................................................. 15 Figure 9. Control Port Interface ..................................................................................................... 16 Figure 10. Power Supply and Reset Circuitry ............................................................................... 17 Figure 11. Silkscreen Top ............................................................................................................. 18 Figure 12. Top Side....................................................................................................................... 19 Figure 13. Bottom Side.................................................................................................................. 20
LIST OF TABLES
Table 1. CS8414 Supported Formats.............................................................................................. 3 Table 2. System Connections ......................................................................................................... 5 Table 3. CDB4392 Jumper and Switch settings - STAND-ALONE MODE ..................................... 6 Table 4. CDB4392 Jumper and Switch settings - CONTOL PORT MODE..................................... 7
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS459DB1
CDB4392
1. CDB4392 SYSTEM OVERVIEW
The CDB4392 evaluation board is an excellent means of quickly evaluating the CS4392. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4392 schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. LED's can be decoded by consulting the CS8414 datasheet. It is likely that the de-emphasis control for the CS4392 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4392 is in the standalone mode with the de-emphasis jumper selected. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, see Figure 6. However, both inputs cannot be driven simultaneously.
2. CS4392 DIGITAL TO ANALOG CONVERTER
A description of the CS4392 is included in the CS4392 datasheet.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches M0, M1, M2, and M3, as described in the CS8414 datasheet. The format selected must be compatible with the data format of the CS4392, as shown in the CS4392 datasheet. Please note that the CS8414 does not support all the possible modes of the CS4392 and the Left-Justified Format for the CS8414 and the CS4392 have incompatible serial clocks, see Table 1. The default settings for M0-M3 on the evaluation board are given in Tables 3-4.
CS4392 CP Mode Format 0 1 2 3 4 5 CS4392 SA Mode Format 0 1 2 3 CS8414 Format Unsupported 2 5 Unsupported Unsupported 6
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 datasheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4392 de-emphasis filter, when the CS4392 is in stand-alone mode. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency information mode. The information displayed by the
Table 1. CS8414 Supported Formats
DS459DB1
3
CDB4392
5. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 8. The 74HC243 transceiver functions as an I/O buffer where HRD1 through HRD6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with HRD1 through HDR6 in the EXT_CLK position. MCLK, LRCK, SDATA and SCLK on J9 become inputs.
7. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4392 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The decoupling capacitors are located as close to the CS4392 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
8. CONTROL PORT SOFTWARE
The CDB4392 is shipped with Windows based software for interfacing with the CS4392 control port via the DB25 connector, P1. The software can be used to communicate with the CS4392 in either SPI or Two Wire mode; however, in SPI mode the CS4392 registers are write-only.
Note: The Two Wire control port mode is compatible with the I2C protocol.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by five binding posts (GND, +5V, VL, +12V and -12V), see Figure 10. The +5V input supplies power to the +5 volt digital circuitry (VA+5, VD+5, VDPC+5) and to VA on the CS4392, while the VL input supplies power to the Voltage Level Converters and the CS4392 VL pin. +12V and -12V supply power to the op-amp and can be +/-5 to +/-12 volts. WARNING: Refer to the CS4392 datasheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device.
Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT.
9. DSD OPERATION
The CDB4392 supports Direct Stream Digital (DSD) operation through the header for external clocks and data, J9. The CS4392 must be placed into the DSD mode and the jumpers HDR1 through HDR6 must be placed into the external clock positions.
4
DS459DB1
CDB4392
10. ANALOG OUTPUT FILTER
The analog output filter on the CDB4392 has been designed to add flexibility when evaluating the CS4392. The output filter was designed in an optional two stage format, with the first optional stage being an instrumentation amplifier design and the second is a 2-pole butterworth filter. The 2-pole filter is designed to have the in-band impedance matched between the positive and negative legs. It also provides a balanced to single ended conversion for standard un-balanced outputs. The instrumentation amplifier is optionally inserted by changing the FILT jumpers (HDR13 and HDR15 for channel A, left, and HDR16 and
CONNECTOR +5V +3/+5V ** VL VEE VCC GND Coax Input Optical Input J9 Parallel Port HDR9 AOUTA AOUTB INPUT/OUTPUT Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output + 5 Volt power + 5 Volt **ONLY** power for the CS4392 + 1.8 to +5.5 digital interface voltage (Note that VL should not exceed the voltage applied to the+3/+5V terminal) -12 to -5V negative supply for the op-amp +5 to +12V positive supply for the op-amp Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical I/O for master, serial, left/right clocks and serial data Parallel connection to PC for SPI / Two Wire control port signals I/O for SPI / Two Wire control port signals Channel A line level analog output Channel B line level analog output Table 2. System Connections
HDR17 for channel B, right) to position 2. This instrumentation amplifier incorporates a 3x gain (+9.5dB) which effectively lowers the noise contribution of the 2-pole filter which improves the overall dynamic range of the system. Resistors R16 and R21 can be adjusted to change the gain of the Instrumentation amp, and R2(R23) must equal R3(R22). The gain of this stage is determined from the following equation where R= R16(R21) and R2= R2(R23)=R3(R22):
2(R ) 1 + ----------R2
SIGNAL PRESENT
DS459DB1
5
CDB4392
JUMPER / SWITCH SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port CS4392 Mode Selection CS4392 Mode Selection CS4392 Mode Selection
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF ENABLE *DISABLE *HI LO HI *LO GND HI *DEM HI *LO *8414 EXT 1 *2
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Invalid for Stand-Alone Mode Disables parallel port See CS4392 datasheet for details See CS4392 datasheet for details See CS4392 datasheet for details Allows the CS8414 to control de-emphasis See CS4392 datasheet for details Selects CS8414 as source Digital I/O header becomes source Bypassed Active
M3 HDR1 to HDR6 HDR13,15 and HDR16,17
CS4392 Mode Selection Selects source of clocks and audio data Selects whether the optional instrumentation amplifier is used or bypassed
Table 3. CDB4392 Jumper and Switch settings - STAND-ALONE MODE *Settings for Stand-Alone mode Notes: The CDB4392 evaluation board is shipped from the factory configured for Control Port mode.
6
DS459DB1
CDB4392
JUMPER SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port AD0/CS SDA/CDIN Pull-Up SCL/CCLK Pull-Up
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF *ENABLE DISABLE *HI LO *HI LO GND *HI DEM HI *LO *8414 EXT 1 *2
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Enables parallel port Invalid for Control Port mode "Don't Care" for Control Port mode SDA/CDIN pulled high Invalid for Control Port mode Invalid for Control Port mode SCL/CCLK pulled high Invalid for Control Port mode Must be low for Control Port mode Selects CS8414 as source Digital I/O header becomes source Bypassed Active
M3 HDR1 to HDR6 HDR13,15 and HDR16,17
Not Functional Selects source of clocks and audio data Selects whether the optional instrumentation amplifier is used or bypassed
Table 4. CDB4392 Jumper and Switch settings - CONTOL PORT MODE *Settings for Control Port mode Notes: The CDB4392 evaluation board is shipped from the factory configured for Control Port mode.
DS459DB1
7
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CDB4392
DS459DB1
Figure 1. System Block Diagram and Signal Flow
DS459DB1
C54 .1UF X7R
VL GND
14
U9 SDATA SCLK LRCK MCLK M3 M2
M2/SCL/CCLK
VL
VCC U7
sdata sclk
11
FERRITE_BEAD L1
VA+5
C59
lrck mclk
SDATA
O0
3
C17 .1UF X7R
AOUTB+ AOUTBBMUTEC
C40 1UF
SCLK
O1
6
.1UF
8
AMUTEC AOUTAAOUTA+
LRCK
GND
M3
1 2 4 5 13 12 10 9
/A0 B0 /A1 B1 /A2 B2 /A3 B3 R10 499 R13 499 R14 499 R41 49.9
GND
1 2 3 4 5 6 7 8 9 10 \RST VL SDATA/DSD_A SCLK/DSD_B LRCK/DSDMODE MCLK (DSD_CLK)M3 (SCL/CCLK)M2 (SDA/CDIN)M1 (AD0/\CS\)M0 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ 20 19 18 17 16 15 14 13 12 11 7
O2
O3
GND CS4392
GND
74VHC125M M1
M1/SDA/CDIN
GND
C34 C20 10UF .1UF X7R
C21 1UF
M0
M0/AD0/CS
LOW ENABLE
GND
U6
14
VCC
MCLK
O0
3
VL
11
RST DEM
O1
6
8414_DEM
8 7
C61
1 2 4 5 13 12 10 9
/A0 B0 /A1 B1 /A2 B2 /A3 B3
O2
O3
.1UF
GND
GND
74VHC125M
GND
GND
CDB4392
Figure 2. CS4392 and Level Shifters
9
2200PF
2.21K
R16
AOUTA+
C55
V+
2
8
.1UF U12 1
GND
.1UF
VEE
CDB4392
DS459DB1
Figure 3. Channel A Selectable Instrumentation Amplifier
GND
10
MC33078P
2 FILT 1
7 HDR15 HDR3X1
R40 300 +
5
6
U12 R2 2.21K 390PF COG
AOUTAAOUTA+
AOUTAC2
AOUTA-
AOUTA+ COG C3 390PF COG 2.21K
VCC
R3
C42
HDR13 HDR3X1
R39 300
3
2
+ V4
MC33078P
1
FILT
C41
2200PF
2.21K
AOUTB+
C56
AOUTB+ COG C15 390PF COG 2.21K
VCC
R21
V+
2
8
.1UF U13
1
GND
.1UF
VEE
CDB4392
Figure 4. Channel B Selectable Instrumentation Amplifier
GND
DS459DB1
MC33078P
2 FILT 1
7 HDR17 HDR3X1
R43 300 +
5
6
U13 2.21K
R23 C39 390PF COG
AOUTB-
AOUTB-
AOUTBAOUTB+
R22
C44
R42 300
3
HDR16 HDR3X1
2
+ V4
MC33078P C43
FILT 1
11
6800PF COG C48
VEE GND GND
2
1500PF COG C53
GND
HDR1X2 HDR8 1 2
12
R28 4.99K C7 2200PF COG
VCC GND
C6 470PF COG
C49 .1UF V+ U11 GND
1 8
R24 4.42K 22UF
3
R17 2.32K C51 R20 715 + MC33078P
4 2
AOUTA-
J3 CON_RCA_RA 560 R5 47K
1 2 3 4 NC
R26 1.33K C14 R15 1.5K VC5
R18
AOUTA+
AOUTA
GND
.1UF
GND
GND
22UF
VA+5
1
MMUN2111LT1 Q3
3
Q1 2SC2878 R25 2K
3
2
3
AMUTEC
AMUTEC
1
Q4 MMUN2211LT1
2
R37 10K
1
VEE GND
GND
CDB4392
DS459DB1
Figure 5. Channel A Audio Output and Mute Circuit
VA+5 GND
2
1
MMUN2111LT1 Q6
3
Q5 2SC2878 R36 2K
3
HDR1X2 HDR7 1 2
DS459DB1
R35 4.99K C4 2200PF COG C18 470PF COG
OUTPUT FILTERS
GND
U11 2.32K 7 6
AOUTB-
R34 4.42K C50 22UF R19 560 1.33K + MC33078P C22 1500PF COG C52
GND GND
R29 R32 715
5
J4 CON_RCA_RA
1 2 3 4 NC
R33 C28 R31 1.5K 6800PF COG
AOUTB+
AOUTB
R4 47K
GND
22UF
GND
2
3
BMUTEC
1
BMUTEC
Q2 MMUN2211LT1 R27 10K
2
1
GND VEE GND
CDB4392
Figure 6. Channel B Audio Output and Mute Circuit
13
D1 LED_RECT 2 1
SN74HC04N
4 3
VA
CS8414_M2
5 4 3 2 1
D3 LED_RECT
RXP RXN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VERF C CD/F1 CE/F2 CC/F0 SDATA CB/E2 ERF CA/E1 M1 /C0/E0 M0 VD+ VA+ DGND AGND RXP FILT RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL CS8414
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R9 470
C33
.068UF X7R GND
SW_DIP_5
OPEN
14
DIGITAL INPUT
J5
CON_RCA_RA
3 NC 4 2 1
C11 .01UF
RXN
R30 75
OPTICAL INPUT
GND
1 2 3
OPT1
MCLK
8414 EXTERNAL CLK SOURCE HDR1X3 HDR5
6
1
C10 .01UF
RXP
HDR1X3 HDR4 1 2 3
2
C9
VA+5
3
.01UF 47UH
1 2 3
L4
VA
HDR1X3 HDR3
4
VD+5
GND SCLK
HDR1X3 HDR2 1 2 3
C1 10UF
5
TORX173
GND LRCK GND
VD1
RN4 47K
R11
VD1
1 2 3
10
SDATA
HDR1X3 HDR1
C26 .1UF X7R U2 1UF C16
VD+5
C27
.1UF X7R
CS8414_M0
.1UF C31
SW1
VD+5
14
RN3 560
CS8414_M1
VCC
GND
U8
1UF C32
GND
6
5
D5 LED_RECT
CSLR/FCK
8414_DEM
8 9
D6 LED_RECT
SW_B3W_1100 S4
11
D4 10 LED_RECT
R7 47.5K
ERROR & FREQ
13
D2 12 LED_RECT
VD1
7
GND
GND
CDB4392
DS459DB1
Figure 7. CS8414 Digital Audio Receiver
GND
VCC GND SN74HC243N
14 7
VD+5
C35 .1UF R1
GND
CDB4392
Figure 8. I/O for Clocks and Data
0
DS459DB1
U4
1 13
G1 G2 A1 A2 A3 A4 B1 B2 B3 B4
SDATA LRCK SCLK MCLK VD+5
11 10 9 8 14 7
SDATA LRCK SCLK MCLK
(DSD_CLK)M3
HDR5X2 J9 2 1 4 3 6 5 8 7 10 9 3 4 5 6
VCC GND C24 .1UF U10
1 13
GND
SN74HC243N
DIGITAL I/O
RN5 47K
VD+5
8414 EXTERNAL CLK SOURCE
G1 G2
GND
11 10 9 8
HDR1X3 HDR6 3 4 5 6
1 2 3
HDR1X3 HDR14 1 2 3
VD+5
A1 A2 A3 A4 B1 B2 B3 B4
M3 M3
GND
15
16
VDPC+5 VD+5
C63 .1UF
VDPC+5 PC PORT
C46 .1UF
RN2 4.7K
11 2 3
GND VL GND ENCTRL GND
VCC U15 SN74HCT125D GND C45 .1UF
VDPC+5 DISABLE ENABLE GND
HDR10 HDR1X3 1 2 3 71
14
HDR4X2 HDR9 1 2 3 4 5 6 7 8
6
U5 VCC O0 O1 O2 O3 GND 74VHC125M R6 2K
7 8 11 6 3 14
GND
RN2 4.7K
16 5 6 1
U15
GND
SN74HCT125D
4
M1/SDA/CDIN M0/AD0/CS M2/SCL/CCLK
VDPC+5
RN1 1K
U1
GND
EN_SCL/CCLK
1 2 4 5 13 12 10 9
/A0 B0 /A1 B1 /A2 B2 /A3 B3
RN2 4.7K
15 2
1 11
/OE CLK
RN2 4.7K
14 3
R8 2K
R12 2K
DB25M_RA P1
2 3 4 5 6 7 8 9
1D 2D 3D 4D 5D 6D 7D 8D
GND
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q VCC GND
VDPC+5
20 10 HDR1X3 HDR11 1 2 3
19 18 17 16 15 14 13 12
VL
HDR1X3 HDR12 1 2 3
RN2 4.7K
13 9 8 4
U15
EN_SCL/CCLK
SN74HCT125D
10
SN74HC574DW .1UF
C47
M0/AD0/CS
M2/SCL/CCLK
M1/SDA/CDIN
RN2 4.7K
GND GND
12 5
GND GND VDPC+5
HDR23 1 2 HDR22 1 2
VL
U15
VDPC+5
12 11
M1/SDA/CDIN
VCC
13
14
C62 SN74HCT125D .1UF SN74HCT125D GND
GND GND
71 2 3
U16
HDR21 1 2
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
DEM
GND
GND
GND
U16 U16 R38 4.7K
9 8 D7 BAT85 5 6
RST
4
SN74HCT125D
SN74HCT125D
10
GND
GND
U16
11 12
RST
SN74HCT125D
13
GND
CDB4392
DS459DB1
Figure 9. Control Port Interface
GND
CDB4392
Figure 10. Power Supply and Reset Circuitry
S1 SW_B3W_1100
DS459DB1
+5V
CON_BANANA CON_BANANA CON_BANANA CON_BANANA
GND
VL/1.8 - 5V
VCC/+12
VEE/-12
CON_BANANA
J6 Z1 P6KE13 P6KE6V8P Z3 Z4
J7
J11
J8 P6KE13
J10
P6KE6V8P
Z5
C12 47UF
GND VL
C29 47UF C30 47UF
C36 47UF
C25 .1UF C57 .1UF C37 L3 FB
GND
VA+5
.1UF
C38
.1UF
C8 U3 DS1233-10
1
L2 FB
C13 47UF
VCC GND
VEE
.1UF
GND
GND RST
3 Vcc
VD+5
GND GND RST
10UF C19
VD+5
VDPC+5
2
1
RST
C23 100PF
GND
17
CDB4392
Figure 11. Silkscreen Top
18
DS459DB1
CDB4392
Figure 12. Top Side
DS459DB1
19
CDB4392
Figure 13. Bottom Side
20
DS459DB1
* Notes *

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