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| E2G1057-29-41 Semiconductor MD56V62320 Semiconductor This version: Apr. 1999 MD56V62320 Pr el im in ar y 4-Bank 524,288-Word 32-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MD56V62320 is a 4-bank 524,288-word 32-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES * * * * * * * Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-bank 524,288-word 32-bit configuration 3.3 V power supply, 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode - CAS latency (2, 3) - Burst length (2, 4, 8) - Data scramble (sequential, interleave) * CBR auto-refresh, Self-refresh capability * Package: 86-pin 400 mil plastic TSOP (Type II) (TSOPII86-P-400-0.50-K) (Product : MD56V62320-xxTA) xx indicates speed rank. PRODUCT FAMILY Family MD56V62320-10 Max. Frequency 100 MHz Access Time (Max.) tAC2 9 ns tAC3 9 ns 1/29 Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ1 VCCQ DQ2 DQ3 VSSQ DQ4 DQ5 VCCQ DQ6 DQ7 VSSQ DQ8 NC VCC DQM0 WE CAS RAS CS NC BA0 BA1 A10 A0 A1 A2 DQM2 VCC NC DQ17 VSSQ DQ18 DQ19 VCCQ DQ20 DQ21 VSSQ DQ22 DQ23 VCCQ DQ24 VCC 1 2 3 4 5 6 7 8 9 MD56V62320 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 VSS 85 DQ16 84 VSSQ 83 DQ15 82 DQ14 81 VCCQ 80 DQ13 79 DQ12 78 VSSQ 77 DQ11 76 DQ10 75 VCCQ 74 DQ9 73 NC 72 VSS 71 DQM1 70 NC 69 NC 68 CLK 67 CKE 66 A9 65 A8 64 A7 63 A6 62 A5 61 A4 60 A3 59 DQM3 58 VSS 57 NC 56 DQ32 55 VCCQ 54 DQ31 53 DQ30 52 VSSQ 51 DQ29 50 DQ28 49 VCCQ 48 DQ27 47 DQ26 46 VSSQ 45 DQ25 44 VSS 86-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0 - A10 BA0, BA1 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name DQM0 - 3 DQi VCC VSS VCCQ VSSQ NC Function Data Input/Output Mask Data Input/Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/29 Semiconductor MD56V62320 PIN DESCRIPTION CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0 - 3. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA10 Column address: CA0 - CA7 BA0, BA1 RAS CAS WE DQM0 - 3 DQi DQM0 controls DQ1 - 8. DQM1 controls DQ9 - 16. DQM2 controls DQ17 - 24. DQM3 controls DQ25 - 32. Data inputs/outputs are multiplexed on the same pin. Functionality depends on the combination. For details, see the function truth table. Bank Access pins. These pins are dedicated to select one of 4 banks. 3/29 Semiconductor BLOCK DIAGRAM MD56V62320 CLK CKE CLOCK BUFFER Command Decoding Logic Command Buffers Control Logic A0 - A10 BA0, BA1 Address Buffers Mode Register Latency & Burst controller Column Address Latches & Counter Column Decoders Sense Amplifiers CS RAS CAS WE DQM0 - DQM3 Row Address Latches & Refresh Counter Row Decoders Word Drivers Memory Cells BANK A BANK B BANK C BANK D Input Buffers Input Data Register DQ1 - DQ32 Output Data Register Output Buffers 4/29 Semiconductor MD56V62320 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr Rating -0.5 to VCC + 0.5 -0.5 to 4.6 -55 to 150 1 50 0 to 70 (Voltages referenced to VSS) Unit V V C W mA C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- (Voltages referenced to VSS = 0 V) Max. 3.6 VCC + 0.3 0.8 Unit V V V Capacitance (VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (ADDR) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, DQM0 - 3) Input/Output Capacitance (DQ1 - DQ32) Symbol CIN1 CIN2 COUT Min. 2 2 2 Max. 5 5 7 Unit pF pF pF 5/29 Semiconductor DC Characteristics Condition Parameter Symbol CKE -- -- -- -- CKE VIH Others IOH = -2 mA IOL = 2 mA -- -- tCC = min tRC = min No Burst tCC = min CS VIH tCC = min -- CKE VIH tCC = min CS VIH tCC = min tCC = min tRC = min tCC = min -- ICC7 CKE VIL tCC = min -- 2 2 6 Min. 2.4 -- -10 -10 -- -- Version -10 MD56V62320 Unit Note Max. -- 0.4 10 10 170 40 V V mA mA mA 1, 2 mA 3 Output High Voltage VOH Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Stand by) VOL ILI ILO ICC1 ICC2 CKE VIH CKE VIL Average Power ICC3S Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC3 mA 2 -- 100 mA 3 ICC4 ICC5 CKE VIH CKE VIH -- 290 mA 1, 2 -- 190 mA 2 ICC6 CKE VIL mA mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/29 Semiconductor MD56V62320 Mode Set Address Keys CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 2 4 8 BT = 1 2 4 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Note: A7, A8, A9, A10, BA1 and BA0 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/29 Semiconductor AC Characteristics Parameter Clock Cycles Time Access Time from Clock Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time Write Command Input Time from Output RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from DQM Data Input Mask Time from DQM Data Input Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Set Command Input (Min.) CL = 3 CL = 2 CL = 3 CL = 2 Symbol tCC tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR lOWD tRRD tREF tPDE tT lCCD lCKE lDOZ lDOD lDWD lROH lMRD MD56V62320-10 Min. 10 15 -- -- 3 3 3 1 3 -- 3 90 30 60 30 15 2 20 -- tSI + 1 CLK -- 1 1 2 0 0 2 3 Max. -- -- 9 9 -- -- -- -- -- 8 -- -- -- 105 -- -- -- -- 64 -- 3 MD56V62320 Note 1, 2 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycle ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle 3 3, 4 3, 4 8/29 Semiconductor Notes : 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W Output 50 pF 50 W MD56V62320 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/29 Semiconductor TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 , , ,, , MD56V62320 15 16 17 18 19 tRC tRP tRCD Ra Ca0 Rb Cb0 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/29 Semiconductor MD56V62320 Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK ,,, ,, tCC tCL CKE CS High tHI tSI RAS tSI tHI lCCD CAS tSI tSI tSI ADDR Ra Ca Cb Cc tHI tHI BA0 BA1 A10 DQ Ra tAC tHI Qa Db Qc tOLZ tSI tOH tHI tOHZ lOWD WE tSI DQM0 - 3 Row Active Write Command Precharge Command Read Command Read Command 11/29 Semiconductor *Notes: MD56V62320 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, DQM0 - 3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA0 and BA1. BA1 0 0 1 1 BA0 0 1 0 1 Active, read or write Bank A Bank B Bank C Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 0 1 0 1 BA1 0 0 0 0 1 1 1 1 BA0 0 0 1 1 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. After the end of burst, bank C holds the idle status. After the end of burst, bank C is precharged automatically. After the end of burst, bank D holds the idle status. After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10, BA1 and BA0 inputs. A10 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Operation Bank A is precharged. Bank B is precharged. Bank C is precharged. Bank D is precharged. All banks are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM0 - 3 entry. 12/29 Semiconductor Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MD56V62320 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 *Notes: , , , ,, , ,, , , , , , 17 18 19 High Bank A Active lCCD Ca0 Cb0 Cc0 Cd0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 lOWD tWR *Note2 *Note1 Read Command Read Command Write Command Write Command Precharge Command 1. To write data before a burst read ends, DQM0 - 3 should be asserted three cycles prior to the write command, to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/29 ,,,, , , , Semiconductor MD56V62320 Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS tRRD CAS ADDR RAa RDb CAa CDb BA0 BA1 A10 WE RAa RDb CAS Latency = 2 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start DQM0 - 3 CAS Latency = 3 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start tWR DQM0 - 3 Row Active (A-Bank) A Bank Read with Auto Precharge D Bank Write with Auto Precharge D Bank Precharge Start Point Row Active (D-Bank) 14/29 Semiconductor Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 , , ,, , ,, MD56V62320 18 19 High tRC tRRD RAa CAa RCb CCb RAc CAc RAa RCb RAc QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Read Command (C-Bank) Read Command (A-Bank) Row Active (C-Bank) Precharge Command (A-Bank) Precharge Command (C-Bank) Row Active (A-Bank) 15/29 Semiconductor MD56V62320 , , ,, , , ,, , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA0 BA1 A10 DQ RAa RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM0 - 3 Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/29 Semiconductor Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 *Note: , ,,, , , MD56V62320 15 16 17 18 19 High *Note1 RAa CAa RCb CCb CAc CCd CAe RAa RCa QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1 lROH Row Active (A-Bank) Row Active (C-Bank) Read Command (C-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (C-Bank) Read Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/29 ,,, ,,, , , ,, Semiconductor MD56V62320 Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RBa CBa RDb CDb CBc CDd BA0 BA1 A10 DQ RBa RDb DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0 WE DQM0 - 3 Row Active (B-Bank) Row Active (D-Bank) Write Command (D-Bank) Write Command (B-Bank) Write Command (D-Bank) Write Command (B-Bank) Precharge Command (All Banks) 18/29 Semiconductor MD56V62320 ,,, , , Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RCb CCb RAc CAc BA0 BA1 A10 DQ RAa RCb RAc QAa0 QAa1 QAa2 QAa3 DCb0 DCb1 DCb2 DCb3 QAc0 QAc1 QAc2 QAc3 WE DQM0 - 3 Row Active (A-Bank) Row Active (C-Bank) Write Command (C-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 19/29 Semiconductor Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MD56V62320 17 18 19 CLK High CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 ,, ,,,, , CAa0 CDb0 CAc0 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (D-Bank) Read Command (A-Bank) 20/29 Semiconductor MD56V62320 Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note1 *Note1 CKE CS RAS CAS ADDR Ra Ca Cb Cc BA0 BA1 A10 Ra *Note4 DQ1 - 8 Qa1 Qa2 Qa3 Qb0 Qb1 Dc1 Dc2 CLK DQ9 - 16 DQ17 - 24 DQ25 - 32 WE *Note4 DQM0 DQM1 DQM2 DQM3 *Notes: ,, ,, ,, , , , , , , Dc3 *Note3 Qa0 Qa2 Qa3 Qb0 Qb1 Dc0 Dc2 Dc3 tOHZ Qa0 Qa1 Qa3 Qb0 Qb1 Dc0 Dc1 Dc3 *Note2 Qa2 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dc2 Read DQM Row Active Read DQM Read Command CLOCK Suspension Read Command Write DQM Write CLOCK Command Suspension 1. 2. 3. 4. When CKE is deactivated, the next clock will be ignored. When DQM0 - 3 are asserted, the read data after two clock cycles will be masked. When DQM0 - 3 are asserted, the write data in the same clock cycles will be masked. When DQM0 is set High, the input/output data of DQ1 - DQ8 will be masked. When DQM1 is set High, the input/output data of DQ9 - DQ16 will be masked. When DQM2 is set High, the input/output data of DQ17 - DQ24 will be masked. When DQM3 is set High, the input/output data of DQ25 - DQ32 will be masked. 21/29 Semiconductor Read Interruption by Precharge Command @ Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 MD56V62320 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 WE CAS Latency = 2 DQ DQM0 - 3 CAS Latency = 3 DQ DQM0 - 3 *Note: 1. If row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. ,, ,,,, , ,, , 13 14 15 16 17 18 19 High Ra Ca Ra *Note1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note1 Qa0 Qa1 Qa2 Qa3 Qa4 Row Active Read Command Precharge Command 22/29 , , , ,, Semiconductor MD56V62320 Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI CKE CS tSI RAS CAS ADDR Ra Ca BA0 BA1 A10 DQ Ra Qa0 Qa1 Qa2 WE DQM0 - 3 Row Active Power-down Entry Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command *Notes: 1. When all banks are in precharge state, and if CKE is set low, then the MD56V62320 enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1 CLK). 23/29 Semiconductor Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR BA0 BA1 A10 DQ WE DQM0 - 3 , ,,, ,, ,, MD56V62320 tRC tSI Ra BS BS Ra Hi - Z Hi - Z Self Refresh Entry Self Refresh Exit Row Active 24/29 Semiconductor Mode Register Set Cycle 0 1 2 3 4 5 6 MD56V62320 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK CKE CS RAS CAS ADDR DQ WE DQM0 - 3 ,, ,,, , High High lMRD tRC key Ra Hi - Z Hi - Z MRS New Command Auto Refresh Auto Refresh 25/29 Semiconductor MD56V62320 FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle H L L L L L L L Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L L L L X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Reserved Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Reserved (Term Burst) --> Row Active Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Action 26/29 Semiconductor MD56V62320 FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge H L L L L L L Write Recovery H L L L L L L Row Active H L L L L L L Refresh H L L L L Mode Register Access H L L L L ABBREVIATIONS RA = Row Address CA = Column Address Notes: X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Action BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 27/29 Semiconductor MD56V62320 FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh H L L L L L L Power Down H L L L L L L All Banks Idle (ABI) 6 CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS RAS CAS WE X H L L L L X X H L L L L X X H L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Action Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension H H H H H H H H L Any State Other than Listed Above H H L L Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 28/29 Semiconductor MD56V62320 PACKAGE DIMENSIONS (Unit : mm) TSOPII86-P-400-0.50-K Preliminary Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 29/29 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation. 2. 3. 4. 5. 6. 7. 8. 9. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan |
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