 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Advanced Information XV750C NTSC/PAL/SECAM Digital Video Decoder Data Sheet Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC. XV750C Data Sheet Table of Contents 1. 2. 3. General Description............................................................................................................. 1 Features ................................................................................................................................ 1 Pins........................................................................................................................................ 3 3.1. 3.2. Pin Layout................................................................................................................................... 3 List of Pins.................................................................................................................................. 4 4. Functions .............................................................................................................................. 6 4.1. 4.1.1. 4.1.2. 4.1.3. Operating Clock ......................................................................................................................... 6 Free Running Operation .............................................................................................................................. 6 VCXO Operation.......................................................................................................................................... 7 VCXO Control.............................................................................................................................................. 7 4.2. 4.2.1. 4.2.2. 4.2.3. 4.2.4. Input Video Interface.................................................................................................................. 8 Conforming Video Standards (Video Systems) ........................................................................................... 8 Analog Front-end......................................................................................................................................... 9 Connecting Video Signals ......................................................................................................................... 11 Video Signal Levels ................................................................................................................................... 15 4.3. 4.4. 4.4.1. 4.4.2. 4.4.3. 4.4.4. Decimation Filter ...................................................................................................................... 16 Y/C Separation.......................................................................................................................... 17 Adaptive 3-line Comb Filter (NTSC-Jpn,M) ............................................................................................... 17 Adaptive 5-line Comb Filter (PAL-B,D,G,H,I,N,M,cN) ................................................................................ 17 Adaptive 3-line hybrid filter (PAL-B,D,G,H,I,N,M,cN) ................................................................................. 17 Trap Filter and Band-pass Filters .............................................................................................................. 17 4.5. 4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5. Chrominance Signal Processing ............................................................................................ 21 ACC ........................................................................................................................................................... 21 Chrominance Decoding Circuit.................................................................................................................. 21 Color Density Adjustment .......................................................................................................................... 23 Hue Trimming ............................................................................................................................................ 23 Detection of Color Field Sequence............................................................................................................ 23 4.6. 4.6.1. Luminance Signal Processing ................................................................................................ 23 AGC........................................................................................................................................................... 23 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information i 4.6.2. 4.6.3. 4.6.4. 4.6.5. Pedestal clamp.......................................................................................................................................... 24 Brightness and Contrast Adjustment ......................................................................................................... 24 Horizontal Aperture Correction .................................................................................................................. 25 Vertical Aperture Correction ...................................................................................................................... 26 4.7. 4.8. 4.8.1. 4.8.2. 4.8.3. PJC ............................................................................................................................................27 TBC............................................................................................................................................27 TBC Mode 0 .............................................................................................................................................. 29 TBC Mode 1 .............................................................................................................................................. 30 Fh Control.................................................................................................................................................. 31 4.9. 4.9.1. 4.9.2. 4.9.3. 4.9.4. Programmable Filter ................................................................................................................32 Filter Coefficients (b1 to b24) .................................................................................................................... 34 Output Coefficient (scl).............................................................................................................................. 34 Setting Filtering ON/OFF........................................................................................................................... 34 Delay quantity of Luminance and Chroma ................................................................................................ 34 4.10. Scaling Engine..........................................................................................................................35 Vertical Scaling ..................................................................................................................................... 35 Horizontal Scaling................................................................................................................................. 36 Conversion between Interlaced and Non-interlaced Images................................................................ 37 Adjusting the Re-sampling Start Position ............................................................................................. 38 Setting the Number of Output Pixels .................................................................................................... 39 Re-sampling Position............................................................................................................................ 40 4.10.1. 4.10.2. 4.10.3. 4.10.4. 4.10.5. 4.10.6. 4.11. 4.12. 4.13. Cropping ...................................................................................................................................41 Color Space Conversion..........................................................................................................41 Video Output.............................................................................................................................42 Output Format ...................................................................................................................................... 42 Video Port Interface.............................................................................................................................. 45 FIFO for DV Port................................................................................................................................... 45 ITU-R BT.656 Output ............................................................................................................................ 45 DV output with EAV and SAV code....................................................................................................... 47 4.13.1. 4.13.2. 4.13.3. 4.13.4. 4.13.5. 4.14. Sync Separation Circuit ...........................................................................................................48 Self-running Sync ................................................................................................................................. 48 4.14.1. 4.15. Timing Generation Circuit .......................................................................................................49 Timing Output Pins ............................................................................................................................... 49 4.15.1. ii Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.15.2. 4.15.3. 4.15.4. 4.15.5. Vertical Timing ...................................................................................................................................... 49 SV Port Horizontal Timing..................................................................................................................... 52 SV Port Control Signal Timing .............................................................................................................. 59 DV port Horizontal Timing..................................................................................................................... 61 4.16. Color Killer Feature.................................................................................................................. 68 Color Killer Factors ............................................................................................................................... 68 Color Killing........................................................................................................................................... 68 4.16.1. 4.16.2. 4.17. Video Standard Detection/Automatic Switching Circuit ....................................................... 68 Video Standard Automatic Switching Mode .......................................................................................... 68 4.17.1. 4.18. 4.19. VBI Path-through Data Output ................................................................................................ 70 VBI Data Extraction Circuit...................................................................................................... 70 Read-out Using VBI FIFO..................................................................................................................... 70 4.19.1. 4.20. Interrupt .................................................................................................................................... 71 Interrupt Events..................................................................................................................................... 71 Interrupt Masks ..................................................................................................................................... 71 Interrupt Signal Timing.......................................................................................................................... 72 4.20.1. 4.20.2. 4.20.3. 4.21. GPIO Port.................................................................................................................................. 73 Register IO Mode.................................................................................................................................. 73 Status Output Mode .............................................................................................................................. 73 DGP2, 3 Signal Output ......................................................................................................................... 74 CFR/CFS (Color Field Reset/Strobe) Signal Output............................................................................. 74 4.21.1. 4.21.2. 4.21.3. 4.21.4. 4.22. 4.23. 4.24. 4.25. I C Interface .............................................................................................................................. 74 Anti-Copy Protection ............................................................................................................... 77 JTAG.......................................................................................................................................... 77 Test Pattern Generator ............................................................................................................ 77 2 5. Interface Registers............................................................................................................. 78 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.4. List of Registers ....................................................................................................................... 78 Register Details ........................................................................................................................ 84 Flag and Status.......................................................................................................................................... 85 Picture Tuning.......................................................................................................................................... 101 Configuration ........................................................................................................................................... 108 Scaler Settings ........................................................................................................................................ 141 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information iii 5.2.5. System Configurations ............................................................................................................................ 145 5.3. Default Values for Register Settings.....................................................................................176 6. 7. Sample Circuit ..................................................................................................................177 Electrical Characteristics ................................................................................................179 7.1. 7.2. 7.3. 7.3.1. 7.3.2. 7.3.3. Absolute Maximum Ratings ..................................................................................................179 Recommended Operating Conditions ..................................................................................179 DC, AC Characteristics ..........................................................................................................180 Analog Characteristics ............................................................................................................................ 180 DC Characteristics (Digital) ..................................................................................................................... 181 AC Characteristics (Digital) ..................................................................................................................... 181 8. Packaging .........................................................................................................................184 iv Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet List of Figures and Tables Figure 2.1. Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 4.17 Figure 4.18 Figure 4.19 Figure 4.20 Figure 4.21 Figure 4.22 Figure 4.23 Figure 4.24 Figure 4.25 Figure 4.26 Figure 4.27 Figure 4.28 Figure 4.29 Figure 4.30 Figure 4.31 Functional block diagram ............................................................................................................................... 2 Pin layout......................................................................................................................................................... 3 Clock connection (free-running) ...................................................................................................................... 6 Clock connection (VCXO) ............................................................................................................................... 7 Analog Front-end Block Diagram .................................................................................................................... 9 Analog pin Terminations .................................................................................................................................. 9 Analog Video Signal Connection Example (1) .............................................................................................. 13 Analog Video Signal Connection Example (2) .............................................................................................. 13 Analog Video Signal Connection Example (3) .............................................................................................. 14 Analog Video Signal connection Example (4) ............................................................................................... 14 Signal levels .................................................................................................................................................. 15 Characteristic of decimation filter ................................................................................................................ 16 Characteristics of band-pass filter (3.58MHz) .............................................................................................. 18 Characteristics of band-pass filter (4.43MHz) ............................................................................................. 18 Characteristics of trap filter (3.58MHz)........................................................................................................ 19 Characteristics of trap filter (4.43MHz)........................................................................................................ 19 Characteristics of trap filter (SECAM) ......................................................................................................... 20 Characteristic of SECAM BELL filter ........................................................................................................... 22 Characteristic of SECAM De-Emphasis filter .............................................................................................. 22 Input video signal level versus PGA gain .................................................................................................... 24 Characteristics of horizontal aperture correction filter ................................................................................. 25 Coring characteristics.................................................................................................................................. 26 Characteristics of vertical aperture enhancement filter ............................................................................... 26 PJC Filter Characteristics............................................................................................................................ 27 TBC Mode 0 ................................................................................................................................................ 29 TBC mode 1 ................................................................................................................................................ 30 Programmable filter configuration ............................................................................................................... 32 Pixel positions between input and output images. ...................................................................................... 41 BT.656 output (TBC mode 0)....................................................................................................................... 46 BT.656 output (TBC mode 1)....................................................................................................................... 46 DV output with EAV and SAV ...................................................................................................................... 47 60Hz Vertical timing..................................................................................................................................... 50 50Hz Vertical timing..................................................................................................................................... 51 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information v Figure 4.32 Figure 4.33 Figure 4.34 Figure 4.35 Figure 4.36 Figure 4.37 Figure 4.38 Figure 4.39 Figure 4.40 Figure 4.41 Figure 4.42 Figure 4.43 Figure 4.44 Figure 4.45 Figure 4.46 Figure 4.47 Figure 4.48 Figure 4.49 Figure 4.50 Figure 4.51 Figure 4.52 Figure 4.53 Figure 4.54 Figure 4.55 Figure 4.56 Figure 5.1 Figure 6.1 Figure 6.2 Figure 7.1 SV port Horizontal timing (SVTDEF_R656:1 /VPDEF_MODE:0 or1) ......................................................... 52 SV port Horizontal timing (SVTDEF_R656:0 /VPDEF_MODE:0 or1) ......................................................... 52 SV port SAV timing (VPDEF_MODE:0 or 1) ............................................................................................... 53 SV port EAV timing (VPDEF_MODE:0 or1) ................................................................................................ 53 SV port SAV timing (VPDEF_MODE2) ....................................................................................................... 54 SV port EAV timing (VPDEF_MODE:2) ...................................................................................................... 54 SV port SAV timing (VPDEF_MODE:4, SVVDEF_SOLV:0)........................................................................ 55 SV port EAV timing (VPDEF_MODE:4, SVVDEF_SOLV:0)........................................................................ 56 SV port SAV timing (VPDEF_MODE:4, SVVDEF_SOLV:2)........................................................................ 57 SV port EAV timing (VPDEF_MODE:4, SVVDEF_SOLV:2)........................................................................ 58 SV port H-V timing ...................................................................................................................................... 59 SV port SCBF/SFLD pin timing ................................................................................................................... 60 DV port Horizontal timing (DVTDEF_R656:1 /VPDEF_MODE:0) ............................................................... 61 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:0) ............................................................... 62 DV port Horizontal timing (DVTDEF_R656:1 /VPDEF_MODE:1) ............................................................... 63 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:1) ............................................................... 64 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:3 /DVVDEF_DOLV:0)................................ 65 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:3 /DVVDEF_DOLV:2)................................ 66 DV port Target Ready signal ....................................................................................................................... 67 Interrupt signal timing (1) ............................................................................................................................ 72 Interrupt signal timing (2) ............................................................................................................................ 72 I C Bus write sequence ............................................................................................................................... 75 I C Bus read sequence ............................................................................................................................... 75 I C Bus write sequence (continuous access).............................................................................................. 76 I C Bus read sequence (continuous access) .............................................................................................. 76 Functional diagram for gain control..............................................................................................................119 Anti Aliasing Filter Sample .......................................................................................................................... 177 Sample circuit.............................................................................................................................................. 178 AC Characteristics (Digital) ......................................................................................................................... 183 2 2 2 2 Table 3.1 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Pin description .................................................................................................................................................. 4 Selection of VCXO Control Modes ................................................................................................................... 8 Conforming video standards............................................................................................................................. 8 Analog video signal input pins .........................................................................................................................11 VAFE channels ................................................................................................................................................11 vi Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Table 4.5 Table 4.6 Table 4.7 Table 4.8 Table 4.9 Table 4.10 Table 4.11 Filter for Y/C separation circuit........................................................................................................................ 17 Table of Registers for Programmable Filter .................................................................................................... 33 SV Line output format ..................................................................................................................................... 42 DV Line output format ..................................................................................................................................... 43 Output signal names ....................................................................................................................................... 43 Output format and output signal name ......................................................................................................... 44 Video port modes .......................................................................................................................................... 45 Timing output pins (1) ................................................................................................................................ 49 Settings for video mode automatic switching................................................................................................ 69 The reference standards for VBI data extraction .......................................................................................... 70 Registers usable for GPIO Output ................................................................................................................ 73 I C slave addresses ...................................................................................................................................... 74 Color Level (8bits digital range) .................................................................................................................... 77 List of interface registers................................................................................................................................. 78 VBI FIFO register interface ............................................................................................................................. 94 Blue-back self-running mode ........................................................................................................................ 125 VBI Pass-through line number correspondence ........................................................................................... 128 VBI data extraction line number correspondence ......................................................................................... 132 Test Patterns ................................................................................................................................................. 172 Absolute Maximum Ratings .......................................................................................................................... 179 Recommended Operating Conditions........................................................................................................... 179 Analog Characteristics .................................................................................................................................. 180 DC Characteristics (Digital)........................................................................................................................... 181 AC Characteristics (Digital)........................................................................................................................... 181 2 Table 4.12-1 Table 4.13 Table 4.14 Table 4.15 Table 4.16 Table 4.17 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information vii XV750C Data Sheet 1. General Description The XV750C is a high quality video decoder capable of converting NTSC, PAL and SECAM video signals or analog component video signals into digital video signals. Its built-in scaling function makes it possible to independently set the horizontal and vertical scaling ratios, enabling, for example, of giving output images at the aspect ratio of square pixels. Two kinds of video output ports namely SV port for streaming output (image data synchronized with input video sync) and DV port for scaling data output, can simultaneously provide image data. The functional block diagram is shown in Figure 2.1. 2. Features Built-in three (3) channel 10-bit ADCs Analog composite (CVBS) and S-video inputs Supports analog component signal input Four (4) line inputs (CVBS, S-video or component is selectable for each line input) Supports NTSC-M, NTSC-(Jpn), NTSC-4.43, PAL-B, D, G, H, I, PAL-N, PAL-M, PAL-CombinationN, PAL-60, and SECAM Detects Video systems and automatically switches over Built-in high image quality Y/C separation circuit (adaptive comb filter1) Built-in Holizontal/Vertical aperture correction circuit Built-in automatic-gain control AGC/ACC circuit Built-in programmable filter (24 taps) Built-in scaler (Horizontal: 1/8 to 2 times, Vertical: 1/8 to 1 time) Supports ITU-R BT.601 and 656 output formats (only for SV line output) Selectable YCbCr/ RGB color spaces MacroVision Detection Function VBI (Closed Caption/CGMS/WSS) data extraction and raw data 10-bit GPIO pins (availing various status outputs) Generating interrupt Single 27 MHz clock Selection among free-running clock/burst-lock VCXO/line-lock VCXO 2 1 Applicable only to NTSC-(Jpn),M, PAL-B,D,G,H,I,N, PAL-M, PAL-CombinationN. Adaptive 3-line comb filter for NTSC, adaptive 5-line comb filter or adaptive 3-line hybrid filter for PAL. 2 External components are required to form a VCXO circuit for VCXO operation. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 1 2 TSCE_N TRST_N TAFE_N DTRDY RST_N DVO15 DVO14 PWDN DGHP VCXO DGVP AIN23 DGP1 DGP0 XTLO CKX1 CKX2 DVAL TMS TDO XTLI DCK TCK TDI OE AIN22 AIN21 VBYP AIN20 AIN13 AIN12 Y/C Separator (YCS) Chrominance Signal Process (CHR) DVO13 DVO12 DVO11 DVO10 DVO09 Luminance Signal Process (LUM) Figure 2.1. VBYN AIN11 IBIAS AIN10 AIN00 AIN01 VCM AIN02 VBG AIN03 VREFN VREFP Analog Front End Control (AFEC) Video System Detector (SYSDET) Input Channel CrossOver (ICHX) Decimation (DCF) Video AFE (VAFE) DVO08 DVO07 DVO06 DVO05 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Functional block diagram Timing Generator (TIMGEN) Time Base Corrector (TBC) Scaling Engine (SCE) DVO04 SCK DVO03 DVO02 DVO01 DVO00 Programmable Filter (PFIL) Sync Separator (SSEP) Color Space Converter (CSC) SHS SVS SHB Host Interface Registers(HIFR) I2C IF Output Formatter (OFORM) TEST_N GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 IRQ_N SVO0 SVO1 SVO2 SVO3 SVO4 SVO5 SVO6 SVO7 SVO8 SVO9 SCBF SFLD IOAS SDA SVB SCL XV750C Data Sheet 3. Pins 3.1. Pin Layout 128pin QFP (XV750CQ1) DVO13 DVO12 DVO11 DVO10 DVO09 DVO08 DVO07 DVO06 DVO05 DVO04 DVO03 DVO02 DVO01 DVO00 VDDI VSSI VDD VDD SCK SHS SHB 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS VSS VSS SVS 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DVO14 DVO15 DTRDY VDD DCK VSS DVAL DGHP DGVP DGP0 DGP1 VSS CKX2 VDD CKX1 VSS XTLO XTLI VDD VCXO VSS PWDN TSCE_N VDDI OE RST_N TDO VSSI TDI TMS TCK TRST_N TAFE_N VSS AVDD AGND AGND AIN23 65 66 67 68 69 70 71 72 73 74 75 76 77 78 SVB SCBF SFLD VSS SVO9 SVO8 SVO7 SVO6 VSS VDD SVO5 SVO4 SVO3 SVO2 VSS SVO1 SVO0 SDA SCL VDDI IRQ_N GPIO9 GPIO8 VSSI VDD GPIO7 GPIO6 GPIO5 GPIO4 VSS GPIO3 GPIO2 GPIO1 GPIO0 VSS VDD IOAS TEST_N 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 XV750CQ1-01 79 24 23 22 QFP128 (TOP VIEW) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 114 115 116 117 118 119 120 121 122 123 124 125 126 127 VREFP VBYP IBIAS AIN22 AIN21 AIN20 AIN13 AIN12 AIN11 AIN10 AIN00 AIN01 VCM AIN02 AGND AGND AGND AIN03 VBYN VREFN Figure 3.1 Pin layout AGND AVDD AVDD AVDD AVDD VBG 128 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 3 3.2. List of Pins Table 3.1 Pin description Pin# 1 2 5-8, 10-13, 16-17 18 20 21 22-23, 25-28, 31-34 Pin Name TEST_N IOAS GPIO[9:0] IRQ_N SCL SDA SVO[9:0] I/O I I I/O O I I/O O Buffer Type Pull Up Pull Up Pull Up Open Drain --Open Drain Tri State Description Test pin: Normally open or pulled-up I2C Slave address setting (L:1000100x, H:1000101x) General purpose port: Register IO mode, Status output, etc. Interrupt request I2C Bus clock I2C Bus data SV port - Video out For details, please refer to "0 Video Port Interface" on page 45. SV port - Field display SV port - Cb display SV port - Vertical blanking signal SV port - Horizontal blanking signal SV port - Vertical sync signal SV port - Horizontal sync signal /CSYNC DV port - Video out For details, please refer to "0 Video Port Interface" on page 45. 36 37 38 39 40 41 43-46, 51-52, 54-55, 57-60, 63-66, 49 67 69 71 72 73 74 75 77 79 81 82 84 86 SFLD SCBF SVB SHB SVS SHS DVO[15:00] O O O O O O O Tri State Tri State Tri State Tri State Tri State Tri State Tri State SCK DTRDY DCK DVAL DGHP DGVP DGP0 DGP1 CKX2 CKX1 XTLO XTLI VCXO PWDN O I I/O O O O O O O O O I O I --Pull Up --Tri State Tri State Tri State Tri State Tri State --------Tri State --- SV port - Clock DV port - Target ready signal DV port - Clock DV port - Data enable/Gated clock DV port - Horizontal general purpose signal DV port - Vertical general purpose signal DV port - General purpose signal 0 DV port - General purpose signal 1 Clock output (double the pixel clock frequency) Clock output (pixel clock frequency) Crystal output Crystal input PWM output for VCXO control voltage Power down: When "H" is applied, power down mode (releasable by register setting) When "L" is applied, normal mode Test pin: Normally open or pulled-up 87 TSCE_N I Pull Up 4 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Pin# 89 Pin Name OE I/O I Buffer Type --Description Output port enable: When "H" is applied, output ports (SVO, DVO) are enabled. (Only the used pins will be enabled. For example, when in SV port 8-bit output mode, unused lower 2 bits will be "Hi-Z") When "L" is applied, the SVO and DVO ports will be forced to "Hi-Z" 90 91 93 94 95 96 97 102 104 106 107 108 110 112 113 114 115 116 118 120 121 122 123 124 126 127 3, 14, 29, 47, 61, 68, 78, 83, 4, 9, 24, 30, 35, 42, 50, 56, 62, 70, 76, 80,85, 98, 15, 48, 92, 19, 53, 88, 99, 103, 111, 117, 125, 100, 101, 105, 109, 119, 128 RST_N TDO TDI TMS TCK TRST_N TAFE_N AIN23 AIN22 AIN21 VBYP AIN20 AIN13 AIN12 VBYN AIN11 IBIAS AIN10 AIN00 AIN01 VCM AIN02 VBG AIN03 VREFN VREFP VDD I O I I I I I I I I I I I I I I I I I I O I O I O O --- Pull Up Tri State Pull Up Pull Up Pull Up Pull Up Pull Up Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog --- Reset signal. JTAG JTAG JTAG JTAG JTAG Reset by "L" input. VAFE test pin: Normally open or pulled-up Analog video input, CH2 - 3(SV-C/D1-Pb/D1-Pr) Analog video input, CH2 - 2(SV-C/D1-Pb/D1-Pr) Analog video input, CH2 - 1(SV-C/D1-Pb/D1-Pr) Analog chroma - Clamp voltage-in: usually connected with VCM Analog video input, CH2 - 0(SV-C/D1-Pb/D1-Pr) Analog video input, CH1 - 3(SV-C/D1-Pb/D1-Pr) Analog video input, CH1 - 2(SV-C/D1-Pb/D1-Pr) Analog chroma - Clamp voltage-input: usually connected to VCM Analog video input, CH1 - 1(SV-C/D1-Pb/D1-Pr) Analog test pin: Usually connected with analog GND Analog video input, CH1 - 0(SV-C/D1-Pb/D1-Pr) Analog video input, CH0 - 0(CVBS/SV-Y/D1-Y) Analog video input, CH0 - 1(CVBS/SV-Y/D1-Y) Analog common voltage Analog video input, CH0 - 2(CVBS/SV-Y/D1-Y) Analog band-gap voltage Analog video input, CH0-3 (CVBS/SV-Y/D1-Y) Analog reference voltage (negative) Analog reference voltage (positive) Digital VDD (+3.3V for buffer) VSS --- --- Digital GND VSSI VDDI AVDD ------- ------- Digital GND Digital VDD (+2.5V) Analog VDD (+2.5V) AGND --- --- Analog GND Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 5 4. Functions 4.1. Operating Clock The XV750C uses a 27MHz clock for digitally sampling the video signals. As to the clock signals fed to XV750C, two kinds of solutions are readily available, namely free-running operation and VCXO operation. 4.1.1. Free Running Operation Free-running is a mode of operation where video signal is decoded using a clock-oscillating module or a clock within the system not synchronized with the input video signal. Sample connection diagrams are shown in Figure 4.1. The dotted lines are connected as required. Crystal VCXO C1 XTLI SCK DCK XTAL C2 R1 1M XV750C CKX1 XTLO CKX2 User System XTAL:27MHz(Fundamental) OSC. Module VCXO SCK XTLI DCK XV750C CKX1 +3.3V XTLO CKX2 User System 1 4 OSC 2 3 OSC:27MHz +/-50ppm Figure 4.1 Clock connection (free-running) 6 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.1.2. VCXO Operation VCXO is a mode of operation where the video signal is decoded using the clock, synchronized with the input video signal, generated by an external VCXO circuit. Sample connection diagrams are shown in Figure 4.2. The dotted lines are connected as required. Crystal 1K 1K VCXO SCK 10uF C1 XTLI DCK XV750C CKX1 User System D1 C2 XTAL R1 1M XTLO CKX2 XTAL:27MHz(Fundamental) VCXO Module 1K 1K VCXO SCK 10uF DCK XTLI XV750C CKX1 User System +3.3V XTLO CKX2 1 4 VCXO 2 3 OSC:27MHz +/-50ppm Figure 4.2 Clock connection (VCXO) 4.1.3. VCXO Control The XV750C is furnished with an external VCXO controlling circuit to generate a sampling clock by way of burst-lock or H-lock (line-lock.), giving controlling voltage output in PWM for the external VCXO circuit. VCXO control works in the following four (4) different modes selected by register VCXODEF_MOD: Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 7 Table 4.1 Selection of VCXO Control Modes VCXODEF _MOD 0 1 2 3 Operation Component Off (Fixed voltage output) Off (Fixed voltage output) H-lock (Line lock) Automatic CVBS/S-Video Off (Fixed voltage output) Burst lock3 H-lock (Line lock) Automatic No Sync. Off (Fixed voltage output) Freeze Freeze Freeze Conditions that H-lock is selected when Automatic; Logical OR below: 1: NTSC-4.43 2: PAL-60 3: SECAM 4: Color killer detected 5: Non-standard signal detected 6: Non-interlaced 7:Component Conditions that Burst lock is selected when Automatic: 1: When the above conditions are all False. 4.2. Input Video Interface 4.2.1. Conforming Video Standards (Video Systems) For composite video (CVBS) and S-video inputs, the XV750C can decode the video signals in NTSC-M, NTSC-(Jpn), NTSC-4.43, PALB, D, G, H, I, PAL-N, PAL-M, PAL-CombinationN, PAL-60, and SECAM standard. It also accepts component signals, where 7:3 Video/Sync Ratio or 10:4 Video/Sync ratio is selectable. Table 4.2 Conforming video standards Video System NTSC-(Japan) NTSC-M NTSC-4.43 PAL-B,D,G,H,I PAL-N PAL-M PAL-CombiN PAL-60 SECAM Line / Frame 525Lines 525Lines 525Lines 625Lines 625Lines 525Lines 625Lines 525Lines 625Lines Fh 15.734264KHz 15.734264KHz 15.734264KHz 15.625KHz 15.625KHz 15.734264KHz 15.625KHz 15.734264KHz 15.625KHz Fv 59.94Hz 59.94Hz 59.94Hz 50Hz 50Hz 59.94Hz 50Hz 59.94Hz 50Hz Blanking Setup 0IRE 7.5IRE 0IRE 0IRE 7.5IRE 7.5IRE 0IRE 0IRE 0IRE Fsc 3.579545MHz 3.579545MHz 4.43361875MHz 4.43361875MHz 4.43361875MHz 3.57561149MHz 3.58205625MHz 4.43361875MHz --- For each video standards' register settings, please refer to "4.17 Video Standard Detection/Automatic Switching Circuit " on page 68. 3 Unstable with signal without color burst. 8 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.2.2. Analog Front-end The XV750C has built-in analog front-end (VAFE) that consists of 27MHz sampling 10-bit video-ADCs, variable-gain video amplifiers, clamp circuits and 4-to-1 multiplexers (Figure 4.3.) Video AFE (VAFE) AIN00 AIN01 AIN02 AIN03 Analog MUX Channel #0 PGA & Clamp 10bit ADC AIN10 AIN11 AIN12 AIN13 Analog MUX Channel #1 PGA & Clamp 10bit ADC AIN20 AIN21 AIN22 AIN23 Analog MUX Channel #2 PGA & Clamp 10bit ADC VREFN VREFP VBYN VBYP Figure 4.3 Analog Front-end Block Diagram Please refer to Figure 4.4 for the handling of analog pins. XV750C VREFN VREFP VBYN VBYP IBIAS 115 AGND VCM VBG 121 123 127 126 107 IBIAS VCM VBG Control Signal 10uF 10uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF Figure 4.4 Analog pin Terminations 113 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 9 Using host interface register settings, the following controls can be done to the VAFE. Auto/Manual Gain control (for each channel) Please refer to Figure 4.9 for the 8 steps of PGA gain setting. Power down control (for each channel) Please refer to register LPWCS_ Analog multiplexer control (common to all channels) 4-to-1 selection. Please refer to the register AIMS_. 10 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.2.3. Connecting Video Signals Pin description N and M in the analog video input pin naming of AlNnm, stands for the VAFE channel number and the input line number respectively. Table 4.3 Analog video signal input pins VAFE Channel #1 AIN10 AIN11 AIN12 AIN13 System 0 1 2 3 #0 AIN00 AIN01 AIN02 AIN03 #2 AIN20 AIN21 AIN22 AIN23 The VAFE channel number 0 (pins AIN00, AIN01, AIN02 and AIN03) is dedicated for the composite signal, S-video or component's luminance signal and Sync on Green signal. Since the channel number 1 and 2 are interchangeable by way of register settings, please refer to Table 4.4. The registers ICHX_DYCH, ICHX_DCCH and ICHX_DPCH are used to set the relation between the physical channel numbers (#0, #1, and #2) and the logical channel names (Ych, Cch, and Pch) of the VAFE. The logical channel names are Ych (Y channel) to give CVBS or Y input, Cch (C channel) to give C of S-Video or Cb of Component input and Pch (P channel) to give Cr input of Component signal. Table 4.4 VAFE channels Register ICHX_DCCH d.c. 1 2 1 2 VAFE Channel #1 #2 n.c. n.c. C n.c. n.c. C Cb Cr Cr Cb d.c: Don't Care n.c.: No Connection Input CVBS S_Video S_Video Component Component ICHX_DYCH 0 0 0 0 0 ICHX_DPCH d.c. 2 1 2 1 #0 CVBS Y Y Y Y Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 11 Connection Examples Connection examples show the cases where analog video signals are fed to the XV750C: Example 1 Figure 4.5: Example 2 Figure 4.6: Example 3 Figure 4.7: Example 4 Figure 4.8: CVBS on Line 0, S-Video on Line 1, component on Line 2, CVBS on Line 3 CVBS on Line 0 to 3 Component on Line 0 to 3 The case where the VAFE channels #1 and #2 are interchanged in example 1, by changing settings in the registers ICHX_DCCH and ICHX_DPCH. By setting input video signal mode for each line (CVBS, S-Video or Component) in the register AINDEF_SELm (m means input line number) in advance, input lines change can be simply done by the register AIMS_SELP. 12 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet AINDEF_SEL0=0 CVBS Video-1 AINDEF_SEL1=1 AINDEF_SEL2=2or3 AINDEF_SEL3=0 AIN00 0 1 2 3 Analog Ch-0* VAFE XV750C Digital Video Decoder S-Video(Y) Component(Y) CVBS Video-2 AIN01 AIN02 AIN03 0 Y-Ch ICHX_DYCH=0 AIN10 S-Video(C) Component(Pb) AIN11 AIN12 AIN13 1 2 3 ICHX_DCCH=1 AIN20 AIN21 Component(Pr) AIN22 AIN23 1 2 3 ICHX_DPCH=2 AIMS_SELP=0,1,2or3 Analog Ch-2 2 0 1 P-Ch Analog Ch-1 2 0 1 C-Ch Figure 4.5 Analog Video Signal Connection Example (1) AINDEF_SEL0=0 CVBS Video-1 AINDEF_SEL1=0 AINDEF_SEL2=0 AINDEF_SEL3=0 AIN00 0 1 2 3 Analog Ch-0* VAFE XV750C Digital Video Decoder CVBS Video-2 CVBS Video-3 CVBS Video-4 AIN01 AIN02 AIN03 0 Y-Ch ICHX_DYCH=0 AIN10 AIN11 AIN12 AIN13 1 2 3 ICHX_DCCH=1 AIN20 AIN21 AIN22 AIN23 1 2 3 ICHX_DPCH=2 AIMS_SELP=0,1,2or3 Analog Ch-2 0 1 P-Ch 2 Analog Ch-1 0 1 C-Ch 2 Figure 4.6 Analog Video Signal Connection Example (2) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 13 AINDEF_SEL0=2or3 Component-1(Y) AINDEF_SEL1=2or3 AINDEF_SEL2=2or3 AINDEF_SEL3=2or3 AIN00 0 1 2 3 Analog Ch-0* VAFE XV750C Digital Video Decoder Component-2(Y) Component-3(Y) Component-4(Y) AIN01 AIN02 AIN03 0 Y-Ch ICHX_DYCH=0 Component-1(Pb) Component-2(Pb) Component-3(Pb) Component-4(Pb) AIN10 AIN11 AIN12 AIN13 1 2 3 ICHX_DCCH=1 Component-1(Pr) Component-2(Pr) Component-3(Pr) Component-4(Pr) AIN20 AIN21 AIN22 AIN23 1 2 3 ICHX_DPCH=2 AIMS_SELP=0,1,2or3 Analog Ch-2 2 0 1 P-Ch Analog Ch-1 2 0 1 C-Ch Figure 4.7 Analog Video Signal Connection Example (3) AINDEF_SEL0=0 CVBS Video-1 AINDEF_SEL1=1 AINDEF_SEL2=2or3 AINDEF_SEL3=0 AIN00 0 1 2 VAFE XV750C Digital Video Decoder AINDEF_SEL0=0 CVBS Video-1 AINDEF_SEL1=1 S-Video(Y) AINDEF_SEL2=2or3 Component(Y) AINDEF_SEL3=0 AIN01 AIN02 AIN00 0 3 VAFE Analog Ch-0* XV750B 0 Y-Ch Digital Video Decoder S-Video(Y) Component(Y) CVBS Video-2 AIN03 AIN01 1 AIN02 AIN10 CVBS Video-2 AIN03 AIN11 AIN12 AIN10 AIN13 AIN11 20 13 2 Analog Ch-0* 0 ICHX_DYCH=0 Y-Ch 1 Analog Ch-1 2 C-Ch ICHX_DYCH=0 Component(Pr) S-Video(C) Component(Pb) S-Video(C) Component(Pb) 1 0 3 1 Analog Ch-1 2 1 Analog Ch-2 2 AIN12 AIN20 AIN13 AIN21 AIN22 AIN20 AIN23 AIN21 20 13 2 ICHX_DCCH=2 C-Ch ICHX_DCCH=1 P-Ch 0 3 1 2 3 Component(Pr) AIN22 AIN23 Analog Ch-2 1 ICHX_DPCH=1 P-Ch AIMS_SELP=0,1,2or3 2 ICHX_DPCH=2 AIMS_SELP=0,1,2or3 Figure 4.8 Analog Video Signal connection Example (4) 14 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.2.4. Video Signal Levels Figure 4.9 shows the signal levels within VAFE when 75% color bar signal is applied at 1Vp-p. Please note that the voltage levels and the gain values below are approximate numbers (voltage levels shown: for NTSC/PAL.) PGA Gain 0: -2.0dB 1: +4.1dB 2: +7.6dB 3: +10dB 4: +12dB 5: +14dB Channel #0 AIN00 AIN01 AIN02 AIN03 Gain 0dB 6: +15dB 7: +16dB MUX 4to1 PGA & Clamp ADC 10bit VRT: 2V 714.3/700mV 714.3/700mV 1143/1120mV 285.7/300mV 285.7/300mV 457/480mV VCL: 25mV*}10 mV VRB: 0V 75%Color Bar PGA Gain 0: -2.0dB 1: +4.1dB 2: +7.6dB 3: +10dB 4: +12dB 5: +14dB Channel #n (n=1,2) AINn0 AINn1 AINn2 AINn3 Gain 0dB 6: +15dB 7: +16dB MUX 4to1 PGA & Clamp ADC 10bit VRT: 2V 626.4/664mV 626.4/664mV 1002/1062mV VCL: 1V*} 25mV 75%Color Bar VRB: 0V Figure 4.9 Signal levels Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 15 4.3. Decimation Filter The XV750C has a built-in decimation filter in order to degrade the video signals that have been originally sampled at 27MHz sampling rate at the analog front end down to 13.5MHz sampling rate. Figure 4.10 shows the frequency characteristic of the decimation filter. Gain (dB) Frequency (MHz) Figure 4.10 Characteristic of decimation filter 16 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.4. Y/C Separation The Y/C separation circuit automatically selects the optimal filter based on the video system used. Please refer to Table 4.5 for the register settings. Note. The case where comb filter is selected is limited when color sub-carriers on adjacent lines bear 180-degree (90-degree in the case of PAL) phase difference. Even in the case of such video system, if once the color sub-carriers move away from the above mentioned standard phase difference, the filter will automatically be switched over to trap and band pass filter. Table 4.5 Filter for Y/C separation circuit Register COMBDEF COMS PAFS 0 d.c. 1 d.c. d.c. d.c. 0 0 0 1 1 0 1 1 d.c. d.c. d.c. d.c. Video System NTSC-Jan,M NTSC-4.43 PAL-B,D,G,H,I,N,M,cN PAL-60 SECAM Y/C Separation Filter Adaptive 3-line comb filter Fixed 3-line comb filter Trap and band pass filter Adaptive 5-line comb filter Adaptive 3-line hybrid filter Fixed 5-line comb filter Fixed 3-line comb filter Trap and band pass filter Trap and band pass filter d.c. *F Don't care 4.4.1. Adaptive 3-line Comb Filter (NTSC-Jpn,M) The adaptive 3-line comb filter utilize three (3) lines; the decoding line (LN0) together with its previous line and the next line (LN-1 and LN+1.). The pixel correlative judgment between the lines, switches between 3-line comb filter (LN-1, LN0 and LN+1) and 2-line comb filter [LN-1 and LN0] or [LN0 and LN+1]. 4.4.2. Adaptive 5-line Comb Filter (PAL-B,D,G,H,I,N,M,cN) The adaptive 5-line comb filter is identical to adaptive 3-line comb filter in its comb filter operation except the numbers of line used. It uses three (3) lines; decoding line (LN0) together with LN-2 and LN+2 lines, skipping the directly adjacent lines. Setting the register, this can be switched to 3-line adaptive hybrid filter. The adaptive 5-line comb filter produces the video signal with less cross-color in comparison with the 3-line adaptive hybrid filter. 4.4.3. Adaptive 3-line hybrid filter (PAL-B,D,G,H,I,N,M,cN) The 3-line adaptive hybrid filter automatically switches and uses comb filter using LN-1 and LN+1 or band-pass filter using LN0, resulting of adaptability judgment. It gives better color reproducibility for horizontal-stripe color in comparison with the case using 5-line adaptive comb filter. 4.4.4. Trap Filter and Band-pass Filters Y/C separation is performed using band-pass and trap filters. There are two band-pass filters; for 3.58MHz and for 4.43MHz. Three types of trap filters are available; for 3.58MHz, for 4.43MHz and for SECAM. The characteristics of those filters are shown in Figure4.11 and Figure 4.15. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 17 10 BPFCHR_CHRS=4 BPFCHR_CHRS=5 BPFCHR_CHRS=6 0 BPFCHR_CHRS=7 -10 Gain (dB) -20 -30 BPFCHR_CHRS=3 BPFCHR_CHRS=2 BPFCHR_CHRS=1 BPFCHR_CHRS=0 -40 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure4.11 Characteristics of band-pass filter (3.58MHz) 10 BPFCHR_CHRS=4 BPFCHR_CHRS=5 BPFCHR_CHRS=6 0 BPFCHR_CHRS=7 -10 Gain (dB) -20 -30 BPFCHR_CHRS=3 BPFCHR_CHRS=2 BPFCHR_CHRS=1 BPFCHR_CHRS=0 -40 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure 4.12 Characteristics of band-pass filter (4.43MHz) 18 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 10 0 -10 Gain (dB) -20 -30 TRPFCHR_CHRS=0 TRPFCHR_CHRS=1 TRPFCHR_CHRS=2 TRPFCHR_CHRS=3 -40 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure 4.13 Characteristics of trap filter (3.58MHz) 10 0 -10 Gain (dB) -20 -30 TRPFCHR_CHRS=0 TRPFCHR_CHRS=1 TRPFCHR_CHRS=2 TRPFCHR_CHRS=3 -40 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure 4.14 Characteristics of trap filter (4.43MHz) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 19 10 0 -10 Gain (dB) -20 -30 -40 TRPFCHR_CHRS=0 TRPFCHR_CHRS=1 TRPFCHR_CHRS=2 TRPFCHR_CHRS=3 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure 4.15 Characteristics of trap filter (SECAM) 20 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.5. Chrominance Signal Processing In the chrominance signal processing, chrominance signal is decoded out from chrominance signal after Y/C separation. 4.5.1. ACC Except for SECAM video, the XV750C can function ACC on the chrominance signal after Y/C separation. The ACC circuit, monitoring the color burst amplitude of the input video signal, automatically calculates the appropriate gain. Digital multiplier then, will provide adequate chrominance signal, based on the calculated gain. There are three (3) modes of operation in ACC based on the register values; 0 for fixed gain (gain value being set by register), 1 for digital ACC (for C channel and P channel, analog gain can be separately set by register) and 3 for automatic gain control. In automatic gain control mode, the analog gains for C channel and P channel become identical to the one for Y channel. When component input is applied, the digital AGC gain value will be used as digital U/V gain. Alternately it is possible through a register setting, to freeze the gain value to the then current value. The ACC time constant can be adjusted in eight (8) steps by register setting. 4.5.2. Chrominance Decoding Circuit This Chrominance decoding circuit supports various video systems of NTSC, PAL and SECAM, and processes the input chrominance modulated components through high precision arithmetic circuit. For SECAM decoding built-in Bell Filter, De-emphasis Filter and FM Demodulation Circuit are provided with. Figure 4.16 shows the Bell Filter characteristics while Figure 4.17 shows the De-emphasis Filter characteristics respectively. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 21 4 2 0 -2 -4 ain d)B G ( -6 -8 -10 -12 -14 -16 3.6 3.8 4 requency )zHM( F 4.2 4.4 4.6 4.8 5 Figure 4.16 Characteristic of SECAM BELL filter 2 0 -2 Gain (dB) -4 -6 -8 -10 1 10 Frequency (MHz) 10 2 10 3 Figure 4.17 Characteristic of SECAM De-Emphasis filter 22 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.5.3. Color Density Adjustment Color density adjustment (chrominance adjustment) before decoding is available for NTSC and PAL only, and is performed commonly for U and V. Post-decoding color density adjustment (color trimming) is available for U and V independently for all the video standards. For details, please refer to the description of the register CLMK_. 4.5.4. Hue Trimming Hue Trimming is only available for NTSC color modulating mode. For PAL, Hue Trimming in a minimal manner avails. Hue Trimming is provided targeting for the case used during decoding video signal in NTSC color modulating mode (color mode = 0). Generally due to the inherent restrictions, PAL and SECAM color modulation modes will not avail Hue Trimming; the XV750C makes it possible for PAL color modulation mode (color mode = 1) to undergo Hue Trimming in a pseudo-manner. In case of SECAM, however, the register value shall be neglected. 4.5.5. Detection of Color Field Sequence Detecting the color field information, the following pin output will be made available. - CFR: pulse output in the designated color field. For output pin, please refer to 4.15.1 Timing Output Pins. -CFSINF: color field number at the time of the input. For output pin, please refer to 4.21.4 CFR/CFS Signal Output. -CFS: strobe pulse to latch CFSINF. For output pin, please refer to 4.21.2 Status Output Mode. 4.6. Luminance Signal Processing The luminance signal processing extracts brightness signal by eliminating sync signal component from the luminance signal after Y/C separation. 4.6.1. AGC The XV750C provides with AGC function over luminance signal after Y/C separation. The AGC circuit automatically calculates the adequate gain and functions, monitoring the amplitude of the input video sync signal and the peak value of the luminance signal. (It is also possible to cut off the peak control, operating AGC only on the sync.) The total gain, output versus input signal, shall be obtained by the function of the circuits of both analog programmable gain amplifier (PGA) and digital AGC. There are four (4) AGC operation modes: selections are available on the register AGCDEF_MOD namely 0 for fixed gain (fixed for both analog PGA gain, digital gain), 1 for digital AGC operation (with analog PGA gain fixed), and 2 for analog and digital AGC operation (up to input level 120%), and 3 for analog and digital AGC operation (up to input level 200%). The fixed gain value for analog PGA and total gain can be preset respectively on the registers YGFXA_FXGA and LGFXD_FXGD. It is also possible to freeze the gain through the register setting, at the then current value, Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 23 when operating in both of the digital AGC and analog digital AGC. Please refer to the related register: AGCDEF_ for details. When operating in digital AGC and analog & digital AGC, based on the calculated gain for Analog PGA and Digital Multiplier, Programmable Gain Amplifier (PGA) and Digital Multiplier will yield an adequate luminance signal. Figure 4.18 shows Input video signal level versus PGA gain. 12 10 8 PGA Gain [dB] 6 4 2 0 -2 -4 -6 -8 -10 20 30 40 50 60 70 80 90 100 110 120 130 140 input level increased input level decreased Input Video Signal Level [%] Figure 4.18 Input video signal level versus PGA gain 4.6.2. Pedestal clamp The pedestal clamp removes the sync signal from the luminance signal. The setup level of 7.5IRE can be supported using register setting. Setup level setting for NTSC-M or NTSC-Jpn: Setup level setting for PAL-B, D, G, H, I, N: Setup level setting for PAL-M: Register MNVM_MOD[5] Register MNVM_MOD[6] Register MNVM_MOD[7] 4.6.3. Brightness and Contrast Adjustment The brightness and contrast controls are readily available. The adjustment can be done through the register settings; register BRTT_BRTT for brightness adjustment and register CONT_CONT for contrast adjustment. 24 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.6.4. Horizontal Aperture Correction The XV750C is capable of enhancing aperture by detecting the horizontal directional edge of the luminance signal. The frequency bandwidth for the enhancement and the level of enhancement are also adjustable. For details please refer to the description on the related register APCOR_. Figure 4.19 shows the frequency response characteristics. WEIT=7 APBW=3 APBW=2 Gain (dB) APBW=1 Frequency (MHz) Figure 4.19 Characteristics of horizontal aperture correction filter In addition, XV750C is provided with coring function in order to reduce the noisiness caused by the aperture correction. Figure 4.20 shows the coring characteristics. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 25 output output -16 input 16 input APCOR_CORG=0 (VENHANC_CORG=0) APCOR_CORG=1 (VENHANC_CORG=1) output output -32 32 -64 input 64 input APCOR_CORG=2 (VENHANC_CORG=2) APCOR_CORG=3 (VENHANC_CORG=3) Figure 4.20 Coring characteristics 4.6.5. Vertical Aperture Correction The XV750C is capable of enhancing apertures by detecting the vertical directional edge of the luminance signal. The level of enhancement and coring characteristics are also adjustable. the description on the related register VENHANC_. For details please refer to Figure 4.21 shows the frequency response characteristics. The coring characteristics will be same as that of Figure 4.20. 20 15 Gain (dB) 10 5 0 -5 Fh/2 Figure 4.21 Characteristics of vertical aperture enhancement filter 26 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.7. PJC The XV750C has a built-in PJC Filter to correct horizontal sampling jitter in 1/16 pixel unit both in luminance signal channel and in chrominance signal channel. With this filter functioning in order, the output phase difference of the sync signal and data could be maintained at constant. The filter characteristic is shown in the Figure 4.22. When the XV750C being driven under VCXO control, the ON/OFF of the PJC Filter will be switched over automatically. This is to make the frequency characteristics flat, switching PJC Filter off when the input signal being TV signal or the like and VCXO control working effectively. In order not to use the automatic switching, please set the register PJSCSW_AUTO to 0 (Manual). 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 0 1 2 3 4 5 6 Frequency (MHz) Figure 4.22 PJC Filter Characteristics Including these functions, PJC Filter can be enabled or disabled through the register setting; for luminance signal with PJCSW_YPJC and for chrominance signal with PJCSW_CPJC, respectively. 4.8. TBC The XV750C has a built-in Line TBC that generates output horizontal sync signal at a stable constant cycle (in pixel unit.) When the TBC is enabled [TBCDEF_ENB=1], it generates output horizontal sync (SHS) and horizontal blanking signal (SHB) so that the horizontal interval during Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 27 active line (line other than vertical blanking) interval is uniformly maintained. This functions to compensate the digitizing error caused in the output horizontal interval when the XV750C is operated in free-running clock mode, by operating in such manner as to absorb the accumulation of 1 field error caused by the compensation, during vertical blanking interval. (This operation of absorbing the accumulated errors is expressed as "TBC reset".) This means the existence of lines deviating from standard value, in its output horizontal interval during vertical blanking interval. In those cases, however, the active horizontal interval is still kept constant as far as possible . When using at [TBCDEF_ENB=1], please set the PJC on by all means. 4 The deviation of horizontal sync frequency Fh to be absorbed by Line TBC being *} 18Hz(NTSC), if in case it goes beyond the limit within 1 field, TBC becomes overflowed, when the TBC operation suspends. This situation continues till TBC resetting takes places. If the line frequency Fh very much differs from the standard, the TBC overflow occurs. Since the register FHCTLS_TBCT can adjust the pixel cycle per line of the TBC circuit, such control is possible as to avoid the occurrence of overflow. It is also noted that the register [FHCTLS_TBCE=1] being enabled, the above register [FHCTLS_TBCE=1] becomes disabled and the XV750C will automatically select the pixel cycle per line. The lines where TBC reset going to take place are set at each field's beginning of the vertical blanking interval (EOF reset) and ending of the vertical blanking interval (SOF reset). These are adjustable line per line by registers TBCDEF_RLE and TBCDEF_RLS, respectively. In addition, there are two modes of TBC operation differentiated by the manner controlling the TBC reset and deviation in horizontal interval. Those two operation modes can be selected using the register TBCDEF_MOD. It is recommended to use at the default setting of [TBCDEF_MOD=1]. Note:! The TBC capability will work only for SV Line output. 4 If horizontal interval becomes extremely too short to maintain standard horizontal interval, active horizontal interval might be shortened. 28 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.8.1. TBC Mode 0 In TBC mode 0, the TBC reset is going to be performed only twice at the EOF and SOF reset lines. The horizontal interval is kept constant except on the TBC resets. Figure 4.23 explains the operation. Active Video Line SHB SHS 138pixels 720pixels HDLY (138 +/- n0)pixels 720pixels SHB TBCDEF_RLE SHS SHB +3Line V Blanking Line SHB SHS SHS 138pixels 720pixels 138pixels 720pixels -8Line SHB SHS 138pixels 720pixels SHB TBCDEF_RLS SHS (138 +/- n1)pixels 720pixels SHB +7Line Active Video Line SHS 138pixels 720pixels HDLY=122(fv=60Hz), HDLY=132(fv=50Hz) Figure 4.23 TBC Mode 0 The Line TBC is aimed to keep the horizontal interval at the standard value, during active video interval (the actual period showing on the screen). This mode especially tries to maintain the characteristics as much as possible in the whole field inclusive of blanking interval in addition to active video interval. The digitizing error accumulated during the interval, shall be released on the EOF and SOF reset lines. (Because of this, the horizontal interval shall deviate on these lines only.) Both of the reset lines release the errors, at the EOF those accumulated during active video interval while at the SOF those accumulated during blanking interval. In other words, distortions accumulated on the field are going to be released through 2 lines separately. Generally, since the number of lines is greater in the active video interval than in blanking, the accumulated distortion becomes bigger in active video interval, therefore, horizontal interval deviation at the EOF reset line becomes greater comparatively than at the SOF reset line. Because of this reason, the horizontal interval Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 29 from blanking interval to active video interval, can be relatively smoothly connected. 4.8.2. TBC Mode 1 In TBC mode1, TBC reset works effective from EOF reset line to SOF reset line. The accumulated error going to be reset at the EOF reset line first, and thereafter the output horizontal intervals deviate from its standard value every time digitizing error occurs. As the result, the deviation in the horizontal sync to be absorbed at SOF reset is not more than the error that occurs during a line. Figure 4.24 explains this operation. Active Video Line SHB SHS 138pixels 720pixels HDLY (138 +/- n0)pixels 720pixels SHB TBCDEF_RLE SHS SHB +3Line V Blanking Line SHB SHS SHS (138 +/- n1)pixels 720pixels (138 +/- n2)pixels 720pixels -8Line SHB SHS (138 +/- n3)pixels 720pixels SHB TBCDEF_RLS SHS (138 +/- n4)pixels 720pixels SHB +7Line Active Video Line SHS 138pixels 720pixels HDLY=122(fv=60Hz), HDLY=132(fv=50Hz) Figure 4.24 TBC mode 1 Although compared to TBC Mode 0, only the active video interval can maintain the constant horizontal interval, there exist no lines with big line deviation throughout from blanking interval to active video interval. 30 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.8.3. Fh Control In the Line TBC circuit, jitter (in pixel unit) in input data, during active vertical video interval shall be absorbed to FIFO line by line, and the distortion shall be accumulated in TBC FIFO. Because the accumulated distortion, going to be released during vertical blanking interval, the decoded result during active vertical video interval outputs conforming to the ITU-R BT601 and BT.656. The XV750C is so designed as to avoid a case where TBC FIFO capacity goes short against video replayed signal and the like. However, some of the video signals easily generated might see FIFO overflow and/or underflow during its active vertical video interval. Fh Control is to perform absorption and release of jitter distortion through FIFO memory, not only during vertical blanking but also horizontal blanking interval. Setting Fh Control on, even in the cases FIFO capacity becoming short, overflow and/or underflow can be avoided by way of adjusting the horizontal blanking intervals. For example, in the case of NTSC video signal with a standard Fh, sampling clock count during 1 line becomes 858 at the sampling clock frequency of 13.5MHz. Usually the Line TBC of the XV750C controls per line pixel number (clock number) during active vertical video interval in such manner to match with 858 clocks. Suppose Fh of the input video signal being high, the feeding signal is of sampling clock number per line of about 857 clocks. At this time, if Fh control function is enabled, it will control in such manner as to make clock number of output data per line to be 857 automatically. This adjustment is done during horizontal blanking interval. For instance, in case of ITU-R BT.656 output mode, interval length of EAV-SAV being deviated, and out of specifications, still SAV-EAV interval can satisfy the specifications. For more details, please refer to the description on the related register FHCTLS_. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 31 4.9. Programmable Filter The XV750C has a built-in FIR filter of 24 taps with coefficients configurable at random. This filter enables limiting the bandwidth of luminance data. Figure 4.25 shows its filter configuration. There are 24 coefficients (b1 to b24) on this filter. By setting those coefficients, a filter with an aimed frequency response can be realized. An output coefficient (scl) also need to be set in order to keep the range of the data output value, within a certain adequate range. Since every coefficient (b1 to b24) can take any value at random, all filters can be configured such as odd-symmetric filter, even-symmetric filter and asymmetric filter etc. The coefficients b1 to b24 and scl can be set at the registers PROFLT_ADRS and PROFLT_DATA. The addresses to set the filter coefficients are not assigned to ordinary registers. By first storing addresses desired to be set, on the PROFLT_ADRS registers, and then write each coefficient value into the PROFLT_DATA registers, coefficient registers can be written. Table 4.6 shows the correspondence between the PROFLT_ADRS values and the filter coefficients. Y in Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 scl Y out Figure 4.25 Programmable filter configuration 32 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Table 4.6 Table of Registers for Programmable Filter PROFLT_ADRS [7:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 PROFLT_DATA [4] [3] b1[7:0] 0 b2[7:0] 0 b3[7:0] 0 b4[7:0] 0 b5[7:0] 0 b6[7:0] 0 b7[7:0] 0 b8[7:0] 0 b9[7:0] 0 b10[7:0] 0 b11[7:0] 0 b12[7:0] 0 b13[7:0] 0 b14[7:0] 0 b15[7:0] 0 b16[7:0] 0 b17[7:0] 0 b18[7:0] 0 b19[7:0] 0 b20[7:0] 0 b21[7:0] 0 b22[7:0] 0 b23[7:0] 0 b24[7:0] 0 0 0 0 [7] s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 0 0 [6] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [2] [1] [0] b1[11:8] b2[11:8] b3[11:8] b4[11:8] b5[11:8] b6[11:8] b7[11:8] b8[11:8] b9[11:8] b10[11:8] b11[11:8] b12[11:8] b13[11:8] b14[11:8] b15[11:8] b16[11:8] b17[11:8] b18[11:8] b19[11:8] b20[11:8] b21[11:8] b22[11:8] b23[11:8] b24[11:8] scl[3:0] 0 sv_en dv_en Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 33 4.9.1. Filter Coefficients (b1 to b24) bn [11:0] Sn Two addresses are allocated for each filter coefficient bn, where n=1 to 24, as shown in Table 1. indicates the coefficient value. 1/2048 of the value set in the bn[11:0] shall be the actual coefficient value. is a bit used to set the coefficient code, where Sn=0 and Sn=1 represent a positive and a negative value, respectively. For example, to set a value of -1.25 to coefficient b1, write the registers as follows: Write 0x00 in PROFLT_ADRS Write 0x00 in PROFLT_DATA Write 0x01 in PROFLT_ADRS Write 0x8a in PROFLT_ADRS Above steps will set a value of -1.25 to coefficient b1. 4.9.2. Output Coefficient (scl) The relation between output coefficient set value of scl and coefficient value is given below. Coefficient value * 2*O (scl-8) The value of scl can range from zero (0) to 15. 4.9.3. Setting Filtering ON/OFF Filtering can be enabled or disabled for SV port and DV port separately. However, since there is only one set of filter coefficients available, it is not possible to configure different filter coefficients for SV port and DV port. The filter is enabled or disabled by setting sv_ev and dv_en bits. Setting sv_ev to "1" enables filtering on SV port, and setting "0" disable it. While dv_en bit is used for the DV port likewise. 4.9.4. Delay quantity of Luminance and Chroma Although no filtering being applied for chroma data, chroma data need to be agreeing with the data delay quantity of the luminance data. For this reason, chroma data is delayed by 12 samples. When filtering is disabled, both luminance data and chroma data will be delayed by 12 samples. 34 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.10. Scaling Engine The XV750C allows scaling on output image data fed to DV port. The scaling ratio is from 1/8 to two (2) horizontally and from 1/8 to one (1) vertically. The scaling ratio can be independently set horizontally and vertically respectively. For scaling, re-sampling process is adopted using a poly-phase filter. The XV750C can continuously (in 32 steps) vary bandwidth-limiting filter characteristics widely over the scaling range, by employing a uniquely configured bandwidth-limiting filter that prevents aliasing. For this reason, characteristics change in the bandwidth-limiting filter causes almost no changes on the image, enabling a flawless zooming while continuously changing the scaling ratio. Since the re-sampling start-position being able to set at the unit of 1/32 pixel horizontally and 1/32 line vertically, post-scaling image can be adjusted at 1/32 pixel unit. Making use of this feature, smooth zooming become possible towards randomly chosen center point. In addition, with the function automatically shifting the vertical sampling position by 1/2 line based on the ODD/EVEN field of the input image, it is possible to generate non-interlaced image from interlaced image. Vice versa, it is also possible to generate interlaced image from non-interlaced one. 4.10.1. Vertical Scaling 1) Setting Scaling Method There are two ways of vertical scaling. It is necessary to choose an appropriate method based on the scaling ratio required. The scaling method is going to be chosen by setting the value on the register SCALM_VFLTS. 1-1) Linear interpolation (SCALM_VFLTS =0) Post-scaling value is going to be obtained by linear interpolation. This method is effective over all the scaling ratio, however, in order to avoid image degradation due aliasing, recommendation is given to use within the scaling ratio range from 1/2 to one (1.) 1-2) Poly-phase Filter Sampling (SCALM_VFLTS =1) Post-scaling value is going to be obtained using a poly-phase filter. This method can only be used for the scaling ratio less than 1/2 inclusive. The image degradation due aliasing is kept minimal, since appropriate bandwidth-limiting filtering is applied corresponding to the scaling ratio. For the scaling ratio ranging from 1/8 to 1/2, the choice of this method is recommended. 2) Setting the Scaling Ratio Setting the values of two registers VFILT_VFILT and VSCAL_VSCAL sets the scaling ratio. The scaling ratio SV is represented by the following formula: Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 35 SV=VFILT_VFILT/VSCAL_VSCAL*512 2-1) Limitations to the setting values There are certain limitations to the configurable values to the registers VFILT_VFILT and VSCAL_VSCAL, with the limit varying to the value of SCALM_VFLTS. 2-1-1) Limit to VFILT_VFILT When SCALM_VFLTS =0, values 4, 8, 16 or 32 only are configurable. When SCALM_VFLTS =1, values from 8 to 32 only are configurable. 2-1-2) Limit on VSCAL_VSCAL When SCALM_VFLTS =0, following relation need to be satisfied. VSCAL_VSCAL* 0x4000+(0x200*(32-VFILT_VFILT)) When SCALM_VFLTS =1, following relation need to be satisfied VSCAL_VSCAL* 0x8000+(0x200*(32-VFILT_VFILT)) 2-2) Recommended Values to be configured Considering the limitation above and the aliasing effect caused by scaling, description is given below how to calculate the recommended values for SCALM_VFLTS, VFILT_VFILT, and VSCAL_VSCAL based on the desired scaling ratio (SV). 2-2-1) Recommended value for SCALM_VFLTS 0 for the scaling ratio of 0.5* SV*...1 1 for the scaling ratio of SV*...0.5 2-2-2) Recommended value for VFILT_VFILT 32 for the scaling ratio of 0.5* SV*...1: 32 The rounded-up value of 96*SV/(1+SV) for the scaling ratio of SV*...0.5 2-2-3) Recommended value for VSCAL_VSCAL VSCAL_VSCAL is expressed in the following formula. VSCAL_VSCAL =VFILT_VFILT *512/SV 4.10.2. Horizontal Scaling Re-sampling using a poly-phase filter at all times, regardless of the scaling ratio, performs horizontal scaling. The image degradation caused by aliasing is kept minimal, since appropriate bandwidth-limiting filtering is performed corresponding to the scaling ratio. 36 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 1) Setting Scaling Ratio Setting the values to the two registers HFILT_FILT and HSCAL_HSCAL, set the scaling ratio. The scaling ratio SH is expressed by the following formula. SH=HFILT_FILT /HSCAL_HSCAL *1024 1-1) Limitations to the setting values There are certain limitations to the values assignable to the registers HFILT_FILT and HSCAL_HSCAL. 1-1-1) Limitations to HFILT_FILT For the scaling ratio greater than 1, only the value of 32 is assignable. For the scaling ratio less than 1 inclusive, only a value between 4 and 32 is assignable. 1-1-2) Limitation to HSCAL_HSCAL If HFILT = 32, the following relation needs to be satisfied: HSCAL_HSCAL* 0x4000 If HFILT < 32, the following relation needs to be satisfied: HSCAL_HSCAL* 0x8000 1-2) Recommended Values to be configured Considering the limitation above and the aliasing effect caused by scaling, description is given below how to calculate the recommended values for HFILT_FILT and HSCAL_HSCAL based on the scaling ratio (SH) desired. 1-2-1) Setting Value of HFILT_FILT 32 for the scaling ratio of 1*...SH Rounded-up value of 32*SH for the scaling ratio of SV* 1 1-2-2) Setting Value of HSCAL_HSCAL HSCAL_HSCAL =HFILT_FILT *1024/SH 4.10.3. Conversion between Interlaced and Non-interlaced Images The scaler normally outputs odd-field image when odd-field is applied, and vice versa even-field when even-field is applied. Therefore, when non-interlaced image is applied, the scaler output yields non-interlaced image of only odd field or even field. The scaling engine incorporated in the XV750C is capable of generating non-interlaced image from interlaced Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 37 image, and vice versa. These settings can be made by the registers SCALM_INTI and SCALM_INTO. 1) Setting for Interlaced to Non-interlaced Setting SCALM_INTI=1 and SCALM_INTO=0, will make the output image all odd fields. Given odd field input image, normal scaling being performed and odd field image output will be fed. Given even field input image, vertical re-sampling starting position being automatically so adjusted as to position the image same with odd-field. In this manner, odd-field images can be produced from even-field image. In this setting, even if a non-interlaced image is applied, normal operation shall produce non-interlaced image output. 2) Setting for Non-interlaced input and Interlaced output Setting SCALM_INTI=0 andSCALM_INTIO=1, odd-field and even-field are alternately repeated automatically on the output image. In this setting, the odd/even flags in the input image are ignored, and every field is treated as odd. Internally however, odd/even flag is generated and each other field alternates odd, even, odd, even. When the internal flag is even, it automatically adjusts the vertical re-sampling starting position and will produce an even field output image, shifting down a half line from the odd field output image. Please be careful, however, if an interlaced image input being fed in this setting, proper output will not be obtained. 4.10.4. Adjusting the Re-sampling Start Position Adjustments for re-sampling start position can be done in 1/32 pixel unit horizontally and in 1/32 line unit vertically. These adjustments use registers DCROPH_CRPHS, DCROPV_CRPVS, HPHS_OFST, and VPHS_OFST. Adjustments are possible horizontally and vertically each other independently. Please note that the re-sampling start position is set as the position on the input image. Therefore, when the scaling ratio is set at 0.3 and re-sampling start position being moved by 1 pixel, the output image will move 0.3 pixel. This is because the scaling ratio of 0.3 is going to be multiplied. 1) Setting Horizontal Start Position The registers DCROPH_CRPHS and HPHS_OFST can specify the horizontal re-sampling start position. The re-sampling start position (HS) is expressed by the following formula. HS=DCROPH_CRPHS *2+HPHS_OFST /32 (Unit in pixel) For the register HPHS_OFST, any value between zero (0) and 63 is assignable but for DCROPH_CRPHS, only a value between zero (0) and 340. Because of this constraint, the re-sampling start position cannot be set close to the right edge of the input image. 38 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 2) Setting Vertical Start Position The registers DCROPV_CRPVS and VPHS_OFST can specify the vertical re-sampling start position. The re-sampling start position (VS) is expressed by the following formula. VS=DCROPV_CRPVS *2 + VPHS_OFST /32 (Unit: line) For the register VPHS any value between zero (0) and 63 is assignable, but for DCROPV_CRPVS only a value between zero (0) and 230 in case of 60Hz scanning mode, or a value between zero (0) and 280 in case of 50Hz scanning mode. Because of this constraint, the re-sampling start position cannot be set close to the bottom edge of the input image. 4.10.5. Setting the Number of Output Pixels The numbers of both horizontal pixels and vertical lines of output image can be configurable. Making use of this function, it is possible to keep the number of output pixels constant even when the scaling ratio is varied. This will not apply, however, if the specified output pixel number and line number go beyond the effective image area. 1) Setting the Number of Output Horizontal Pixel The register DCROPH_CRPHA defines the number of output horizontal pixel. The number of output pixel (HO) is expressed by the following formula. HO=DCROPH_CRPHA*2 Therefore, even numbers only are configurable for the output pixel number. Furthermore, scaling is only performed in the effective area on input image. Accordingly, the number of output pixel may become less than the value specified by DCROPH_CRPHA, depending the settings in the registers DCROPH_CRPHA,DCROPH_CRPHS and the horizontal scaling ratio. When the following equation establishes, the number of output pixels will be equal to the number set to DCROPH_CRPHA: DCROPH_CRPHS*2+DCROPH_CRPHA*2/SH *... 760 (Where, SH is the horizontal scaling ratio.) 2) Setting the Number of Vertical Output Lines The register DCROPV_CRPVA defines the number of vertical output lines. The number of vertical output lines (VO) is expressed by the following equation. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 39 VO=SCROPV_CRPVA For the output line number, odd numbers also may be specified. However when an odd number being specified, please note that the number of lines will differ in odd-field and even-field. In this case, odd field will have one line more than even field. In addition, scaling is only performed within the effective area of the input image, as in the horizontal scaling. Therefore, the number of output pixels may become less than the value specified by DCROPV_CRPVA, depending the settings in the registers DCROPV_CRPVA,DCROPV_CRPVS and vertical scaling ratio. When the following equation is satisfied, output line number will meet the number set in DCROPV_CRPHV: DCROPV_CRPVS*2+DCROPV_CRPVA/SV *... 496(in 60Hz scanning mode) DCROPV_CRPVS*2+DCROPV_CRPVA/SV *... 600(in 50Hz scanning mode) (Where, SV is vertical scaling ratio) 4.10.6. Re-sampling Position Figure 4.26 shows the relation between the pixel positions in the input image and output image. The codes HS, VS, HO and VO in the figure mean as listed below. HS: Horizontal re-sampling start position VS: Vertical re-sampling start position HO: Number of horizontal output pixels VO: Number of vertical output lines 40 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet HS ODD Input Pixel Point EVEN VS ODD EVEN ODD EVEN ODD ODD VO EVEN ODD EVEN ODD EVEN EVEN ODD EVEN ODD EVEN EVEN Output Pixel Point HO ODD Figure 4.26 Pixel positions between input and output images. 4.11. Cropping Cropping is the function for users to crop image at random range. For SV port output, the following two different modes are available. Cropping mode: where the blanking signal that indicates active video interval varies in accordance with cropping. Masking mode: where only the data is masked in accordance with cropping, while blanking signal depends on the window. For DV port, please refer to "4.10.5*DSetting the Output Pixel Number" on page 39. The cropping area can be specified separately for SV and DV ports using the registers. [Related registers: SCROPDEF_, SCROPH_, SCROPV_, DCROPH_, and DCROPV_] 4.12. Color Space Conversion Color space conversion from Y, U, V to YCbCr and RGB is performed. The level of YCbCr corresponds to ITU-R. BT.601. In case of RGB, gamma correction on/off is configurable. Color space settings can be made independently for SV Line and DV Line. Color space: SV Line: register SVVDEF_SOLV DV Line: register DVVDEF_DOLV On/Off setting of RGB level and gamma correction (A Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC =2.2) Advanced Information 41 SV Line: register SVVDEF_SRGB DV Line: register DVVDEF_DRGB 4.13. Video Output The XV750C provides a SV Line that outputs video signals synchronized to the input video signal timing, and a DV Line for scaling output. DV Line output having a FIFO at the output stage, can be read out at the clock different from the internal clock used for decoding. It also provides output formatting conversion function corresponding to such like ITU-R BT.656 format. Note:! DV Line outputs a data of an active video only. Therefore output of DV Line could not have ITU-R BT.656 format even if DV Line is a SAV/EAV addition mode. 4.13.1. Output Format The SV Line output format is shown in Table 4.7, and the DV Line output format in Table 4.8. If the RGB output is selected as described in "4.12 Color Space Conversion" on page 41, only OUT24 or OUT24ES is effective. Note:! Register VPDEF_MODE setting being common to SV and DV Lines, when both SV and DV Line outputs are simultaneously used, please choose "0" or "1" corresponding to the output format for the DV Line Table 4.7 SV Line output format Register SVVDE F_ S10B 0 1 0 1 0 1 0 1 0 0 Format Name OUT8 OUT10 OUT8ES OUT10ES OUT16 OUT20 OUT16ES OUT20ES OUT24 OUT24ES Sampling Ratio 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 4:4:4 Color Space YCbCr YCbCr YCbCr YCbCr YCbCr YCbCr YCbCr YCbCr YCbCr, RGB YCbCr, RGB Description 8bit Y/CbCr Multiplexed output 10bit Y/CbCr Multiplexed output Format EAV and SAV are added to the 8bit Y/CbCr Multiplexed output (Equivalent to ITU-R BT.656) Format EAV and SAV are added to the 10bit Y/CbCr Multiplexed output (Equivalent to ITU-R BT.656) 8bit Y output and CbCr output 10bit Y output and CbCr output Format EAV and SAV are added to the 8bit Y output and CbCr output Format EAV and SAV are added to the 10bit Y output and CbCr output 8bit Y/G, Cb/B and Cr/R output Format EAV and SAV are added to the 8bit Y/G, Cb/B and Cr/R output VPDEF _ MODE 0,1 0,1 0,1 0,1 2 2 2 2 4 4 SVTDE F_ R656 0 0 1 1 0 0 1 1 0 1 42 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Table 4.8 DV Line output format Register SVDE F_ S10B d.c. d.c. d.c. d.c. d.c. d.c. Format Name OUT8 OUT8ES OUT16 OUT16ES OUT24 OUT24ES Sampling Ratio 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 4:4:4 Color Space YCbCr YCbCr YCbCr YCbCr YCbCr, RGB YCbCr, RGB Description 8bit Y/CbCr Multiplexed output Format SAV and EAV are added to the 8bit Y/CbCr Multiplexed output 8bit Y output and CbCr output Format SAV and EAV are added to the 8bit Y and CbCr output 8bit Y/G, Cb/B and Cr/R output Format SAV and EAV are added to the 8bit Y/G, Cb/B and Cr/R output VPDE F_ MODE 0 0 1 1 3 3 DVTD EF_ R656 0 1 0 1 0 1 For the meaning of output signal names, please refer to Table 4.9. Table 4.10 shows the output signal names and the data streams for each output format. Table 4.9 Output signal names Signal Name SYC SY SC SCb SCr SG SB SR DYC DY DC DCb DCr DG DB DR Output Port System SV SV SV SV SV SV SV SV DV DV DV DV DV DV DV DV Sampling Ratio 4:2:2 4:2:2 or 4:4:4 4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:4:4 4:2:2 4:2:2 or 4:4:4 4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:4:4 Bit Width 10 or 8 10 or 8 10 or 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Description Y/CbCr multiplexed data Y data (8bitonly when 4:4:4) CbCr data Cb data Cr data G data B data R data Y/CbCr multiplexed data Y data CbCr data Cb data Cr data G data B data R data Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 43 Table 4.10 Output format and output signal name 27MHz Timeslot 0 1 2 3 4 5 6 7 2n 2n+1 2n+2 2n+3 OUT8/OUT10 SYC Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb(n) Y(n) Cr(n) Y(n+1) OUT16/OUT20 SY Y0 Y1 Y2 Y3 SC Cb0 Cr0 Cb2 Cr2 SY/SG Y0/G0 Y1/G1 Y2/G2 Y3/G3 OUT24 *(c) Output Format Output Signal Name *(c) SCb/SB Cb0/B0 Cb1/B1 Cb2/B2 Cb3/B3 SCr/SR Cr0/R0 Cr1/R1 Cr2/R2 Cr3/R3 Y(n) Y(n+1) Cb(n) Cr(n) Y(n)/G(n) Y(n+1/G(n+1) Cb(n)/B(n) Cb(n+1)/B(n+1) Cr(n)/R(n) Cr(n+1)/R(n+1) 44 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.13.2. Video Port Interface The video data output in its data output configuration to DVO port and SVO port, differs to the register settings. Table 4.11 indicates the relations among output signal names, SVO pins and DVO pins in each output format. As to the meaning of each output signal name used in the table, please refer to Table 4.9. Please also note that the registers relevant to the modes of video ports are VPDEF_MODE and SVVDEF_S10B, among those concerned with the output format. Table 4.11 Video port modes REGISTER VPDEF_MODE SVVDEF_S10B [2:0] 9 0 0 1 0 1 1 0 2 1 0 3 1 4 0 PORT 8 SVO 76543 SYC[7:0] SYC[9:0] SYC[7:0] SYC[9:0] SY[7:0] SY[9:0] DR/DCr[7:0] DR/DCr[7:0] SG/SY[7:0] SG/SY[7:0] 2 1 0 15 14 13 12 11 10 9 DYC[7:0] DYC[7:0] DY[7:0] DY[7:0] SC[7:0] SC[9:0] DG/DY[7:0] DG/DY[7:0] SB/SCb[7:0] SB/SCb[7:0] DVO 87 6 5 4 3 2 1 0 DC[7:0] DC[7:0] DB/DCb[7:0] DB/DCb[7:0] SR/SCr[7:0] SR/SCr[7:0] 4.13.3. FIFO for DV Port There is a FIFO provided for data output at DV port. It is 32 stages deep and write-side uses mains 27MHz (13.5MHz) line, while read-side is read at the speed corresponding to the clock being used for input/output at the DCK port. (The maximum clock frequency to be supplied to DCK is 54MHz.) At the FIFO read-out, timing signal necessary for the DV port is generated, corresponding to the readout clock and the mode. As to the output timing chart, please refer to "Timing Generation Circuit" on page 49. 4.13.4. ITU-R BT.656 Output The output formats OUT8ES and OUT10ES are equivalent to ITU-R BT.656. However, if the input video signal is non-standard or decoding on free-running clock, such things are thought to happen as the pixel number may deviate from the standard or the line number may fluctuate. In terms of the number of lines, the XV750C will produce output in accordance to the input video signals. In terms of pixel number deviation, the output is given in such manner as the deviation happens during the EAV-SAV period in the vertical blanking-interval. This action may slightly differ by the settings of the TBC mode [register TBCDEF_MOD]. 5 5 Only for SV Line output Refer to 4.13.5 in case of DV Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 45 Figure 4.27 shows the operation in TBC mode 0, and Figure 4.28 shows the operation in TBC mode 1. 138pixels SAV (138+/-X0)pixels SAV 138pixels EAV SAV EAV 138pixels SAV 720pixels 720pixels 720pixels 720pixels ACTIVE VIDEO V BLANK EAV EAV EAV EAV EAV 138pixels 138pixels SAV SAV SAV 720pixels 720pixels 720pixels 720pixels V BLANK SAV (138+/-X1)pixels 138pixels EAV EAV EAV 138pixels 138pixels SAV 720pixels 720pixels 720pixels 720pixels 720pixels ACTIVE VIDEO SAV (138+/-X2)pixels EAV SAV 138pixels EAV SAV EAV 138pixels SAV EAV EAV EAV 138pixels 138pixels SAV SAV 720pixels 720pixels 720pixels V BLANK SAV (138+/-X3)pixels Figure 4.27 BT.656 output (TBC mode 0) EAV (138+/-B0)pixels SAV EAV (138+/-B1)pixels SAV 138pixels EAV SAV EAV 138pixels SAV 720pixels 720pixels 720pixels 720pixels V BLANK ACTIVE VIDEO EAV EAV EAV 138pixels 138pixels SAV SAV 720pixels 720pixels 720pixels 720pixels V BLANK SAV (138+/-X0)pixels EAV (138+/-B2)pixels SAV EAV SAV EAV (138+/-B3)pixels SAV EAV (138+/-B4)pixels SAV EAV (138+/-B5)pixels SAV EAV EAV 138pixels 138pixels SAV SAV 720pixels 720pixels 720pixels 720pixels 720pixels ACTIVE VIDEO EAV EAV EAV 138pixels 138pixels SAV SAV 720pixels 720pixels 720pixels V BLANK SAV (138+/-X1)pixels Figure 4.28 BT.656 output (TBC mode 1) 46 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.13.5. DV output with EAV and SAV code The output formats OUT8ES and OUT10ES of DV output is shown in Figure 4.29. SAV(0,1,0) EAV(0,1,1) SAV(0,0,0) SAV(0,0,0) SAV(0,0,0) Field 1 SAV(0,0,0) SAV(0,0,0) SAV(0,0,0) SAV(1,1,0) EAV(1,1,1) SAV(1,0,0) SAV(1,0,0) SAV(1,0,0) Field 2 SAV(1,0,0) SAV(1,0,0) SAV(1,0,0) SAV(0,1,0) EAV(0,1,1) SAV(0,0,0) SAV(0,0,0) SAV(0,0,0) Field 1 SAV(0,0,0) SAV(0,0,0) SAV(0,0,0) Active Video Active Video EAV(0,0,1) EAV(0,0,1) EAV(0,0,1) (F,V,H) Active Video Active Video Active Video EAV(0,0,1) EAV(0,0,1) EAV(0,0,1) Active Video Active Video EAV(1,0,1) EAV(1,0,1) EAV(1,0,1) Active Video Active Video Active Video EAV(1,0,1) EAV(1,0,1) EAV(1,0,1) Active Video Active Video EAV(0,0,1) EAV(0,0,1) EAV(0,0,1) Active Video Active Video Active Video EAV(0,0,1) EAV(0,0,1) EAV(0,0,1) V BLANK V ACTIVE V BLANK V ACTIVE V BLANK V ACTIVE Figure 4.29 DV output with EAV and SAV Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 47 4.14. Sync Separation Circuit This circuit separating the sync signal from the input video signal, generates various timing signals used internally. 4.14.1. Self-running Sync The XV750C can self-produce output sync signal, synchronizing to the input video signal sync and output in line with the timing corresponding to the image decoded. When however, in such case as unstable input signal suddenly fluctuating sync position, dropping of sync and missing of sync due to noise, the XV750C will complement such sync and output. Later when the signal becomes stable, sync output resumes to synchronize to the input signal. In case when such unstable condition continues, it will switch over to self-running mode. The conditions for switching over to the self-running mode and the video output under self-running can be changed by setting the register BBDEF_MOD. output blue-back when it cannot detect the sync. In the default setting, the XV750C will 48 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.15. Timing Generation Circuit This circuit generates from the separated sync signal, various timing signals for external output use, synchronized to the output image. 4.15.1. Timing Output Pins The outputs are such various timing signals as video sync signals synchronized to SV-line output data, and DV-line output data. Table 4.12 indicates the relation between the timing-signal output pins and the output-timing signals. Each pin name is shown with the register names used to specify corresponding timing signal (As to SCK, SHS, SVS, SHB and SVB registers can not change output timing signal.) For instance, in order to give VBI Path Through data output interval signal (VBI Term) at SFLD port, `1' shall be written into register SVCDEF_SFLDS. Table 4.12-1 Timing output pins (1) PORT SCK SCK Output SHS H Sync SVS V Sync SHB H Blank SVB V Blank Table 4.12-2 Timing output pins (2) PORT REGISTER 0 1 2 3 4 5 6 7 SFLD SVCDEF_SFLDS Field ID VBI Term SHB & SVB SHS & SVS SVS Field ID (Alternated) Color Field Reset Color Field Strobe SCBF SVCDEF_SCBFS CB Flag VBI Term SHB & SVB SHS & SVS SVS Field ID (Alternated) Color Field Reset Color Field Strobe DGHP DVCDEF_DGHP H End (DHEND) H Blank (DHB) DGVP DVCDEF_DGVP V End (DVEND) V Blank (DVB) DGP0 DVCDEF_DGP0 H Blank (DHB) Field ID (DFLD) CB Flag (DCBF) VBI Term (DVBI) DV FIFO not Empty DV FIFO Almost Empty DV FIFO Almost Full DV FIFO Full Table 4.12-3 Timing output pins (3) PORT REGISTER 0 1 2 3 4 5 6 7 DGP1 DVGDEF_DGP1 H Blank (DHB) Field ID (DFLD) CB Flag (DCBF) ANC Term (DANC) DV FIFO not Empty DV FIFO Almost Empty DV FIFO Almost Full DV FIFO Full DPIO8 (DGP2) DVGDEF_DGP2 H Blank (DHB) Field ID (DFLD) CB Flag (DCBF) SAVEAV Term (DS AVEAV) DV FIFO not Empty DV FIFO Almost Empty DV FIFO Almost Full DV FIFO Full DPIO9 (DGP3) DVGDEF_DGP3 H Blank (DHB) Field ID (DFLD) CB Flag (DCBF) ANC Term (DANC) DV FIFO not Empty DV FIFO Almost Empty DV FIFO Almost Full DV FIFO Full DCK DVCDEF_DCKS DCK Output DCK Input DVAL DVCDEF_DVALG Data Valid DCK & Data Valid In addition, the polarity of the following signals can be inverted by register settings. Registers SVPOL_ SCK, SFLD, SCBF, SVB, SHB, SVS and SHS Registers DVPOL_ DCK, DTRDY, DVAL, DGP1, DGP0, DGVP and DGHP 4.15.2. Vertical Timing Figure 4.30 and Figure 4.31 indicate the vertical timing when the vertical frequency is 60Hz and 50Hz, respectively. The input video signal is fed out with approximate 2.5 H delay. output timing might differ according to the scaling ratio. In case of DV Line output, the Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 49 50 2 3 4 5 6 7 8 9 10 11 22 23 24 25 525 4 20 21 22 264 265 266 267 268 269 270 271 272 273 274 285 286 287 263 266 283 284 285 524 525 1 AIN0x (Y) SHB SVB SHS SVS SFLD 262 263 Figure 4.30 60Hz Vertical timing Advanced Information AIN0x (Y) SHB SVB SHS SVS Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC SFLD 621 622 623 624 625 1 2 3 4 5 6 7 8 23 24 25 26 AIN0x 622 623 1 23 24 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC 311 312 313 314 315 316 317 318 319 320 321 336 337 338 339 310 313 336 (Y) SHB SVB SHS SVS SFLD 309 310 Figure 4.31 50Hz Vertical timing Advanced Information AIN0x (Y) SHB SVB SHS SVS XV750C Data Sheet SFLD 51 4.15.3. SV Port Horizontal Timing Figure 4.32 and Figure 4.33 indicate the SV port output video signal interface timings when the video port mode (register VPDEF_MODE) is "0" or "1". neighborhood of SAV and EAV. Note! The figures are for the 8-bit mode ( HSW=60 HDLY=122(fv=60Hz), HDLY=132(fv=50Hz) Figure 4.34 and Figure 4.35 show the details in the XTLI SCK SVO Cbn-2 Yn-2 Crn-2 Yn-1 FF 00 00 EAV undefined FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") SHS HSW*T1 (HDLY-HSDELAY_HST)*T1 T1=1/fCKX1 Figure 4.32 SV port Horizontal timing (SVTDEF_R656:1 /VPDEF_MODE:0 or1) XTLI SCK SVO (SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Yn-2 Crn-2 Yn-1 0x80 0x10 0x80 0x10 0x80,0x10,...... Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SVO (SBMSK_YMSH="0", SBMSK_CMSH="0") Cbn-2 Yn-2 Crn-2 Yn-1 undefined Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SHB SHS HSW*T1 (HDLY-HSDELAY_HST)*T1 T1=1/fCKX1 Figure 4.33 SV port Horizontal timing (SVTDEF_R656:0 /VPDEF_MODE:0 or1) 52 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet XTLI SCK SVO (SVTDEF_R656="0", SBMSK_YMSH="0", SBMSK_CMSH="0") undefined Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 0x80 0x10 0x80 0x10 0x80 0x10 0x80 0x10 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SVO (SVTDEF_R656="1", SBMSK_YMSH="0", SBMSK_CMSH="0") undefined 0xFF 0x00 0x00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 0x80 0x10 0x80 0x10 0xFF 0x00 0x00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.34 SV port SAV timing (VPDEF_MODE:0 or 1) XTLI SCK SVO (SVTDEF_R656="0", SBMSK_YMSH="0", SBMSK_CMSH="0") Cbn-2 Yn-2 Crn-2 Yn-1 undefined SVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Yn-2 Crn-2 Yn-1 0x80 0x10 0x80 0x10 0x80 0x10 0x80 0x10 0x80 0x10 0x80 0x10 SVO (SVTDEF_R656="1", SBMSK_YMSH="0", SBMSK_CMSH="0") Cbn-2 Yn-2 Crn-2 Yn-1 0xFF 0x00 0x00 EAV undefined SVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Yn-2 Crn-2 Yn-1 0xFF 0x00 0x00 EAV 0x80 0x10 0x80 0x10 0x80 0x10 0x80 0x10 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.35 SV port EAV timing (VPDEF_MODE:0 or1) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 53 The SV port output video signal interface timing of SAV in Figure 4.36 and of EAV in Figure 4.37 are shown respectively, when the video port mode (register VPDEF_MODE) is "2". XTLI SCK SVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 Y0 Y1 Y2 Y3 DVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 Cb0 Cr0 Cb2 Cr2 SVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 0x00 SAV Y0 Y1 Y2 Y3 DVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 0xFF 0x00 Cb0 Cr0 Cb2 Cr2 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.36 SV port SAV timing (VPDEF_MODE2) XTLI SCK SVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Yn-2 Yn-1 0x10 DVO (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Crn-2 0x80 SVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Yn-2 Yn-1 0x00 EAV 0x10 DVO (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Crn-2 0xFF 0x00 0x80 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.37 SV port EAV timing (VPDEF_MODE:2) 54 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Figure 4.38 and Figure 4.39 indicate the interface timing of SV port Y/Cb/Cr output video signal SAV and EAV, respectively, when the video port mode (register VPDEF_MODE) is " 4". XTLI SCK SVO[9:2] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 Y0 Y1 Y2 Y3 DVO[15:8] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 Cb0 Cb1 Cb2 Cb3 DVO[7:0] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 Cr0 Cr1 Cr2 Cr3 SVO[9:2] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x10 0x00 SAV Y0 Y1 Y2 Y3 DVO[15:8] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 0xFF 0x00 Cb0 Cb1 Cb2 Cb3 DVO[7:0] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x80 Cr0 Cr1 Cr2 Cr3 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.38 SV port SAV timing (VPDEF_MODE:4, SVVDEF_SOLV:0) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 55 XTLI SCK SVO[9:2] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Yn-2 Yn-1 0x10 DVO[15:8] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Cbn-1 0x80 DVO[7:0] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Crn-2 Crn-1 0x80 SVO[9:2] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Yn-2 Yn-1 0x00 EAV 0x10 DVO[15:8] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Cbn-2 Cbn-1 0xFF 0x00 0x80 DVO[7:0] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Crn-2 Crn-1 0xFF 0x00 0x80 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.39 SV port EAV timing (VPDEF_MODE:4, SVVDEF_SOLV:0) 56 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Figure 4.40 and Figure 4.41 indicate the SV port RGB output image-signal interface timing SAV and EAV, respectively, when the video port mode (register VPDEF_MODE) is " 4" XTLI SCK SVO[9:2] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x00 G0 G1 G2 G3 DVO[15:8] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x00 B0 B1 B2 B3 DVO[7:0] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x00 R0 R1 R2 R3 SVO[9:2] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x01 0x00 SAV G0 G1 G2 G3 DVO[15:8] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x01 0xFF 0x00 B0 B1 B2 B3 DVO[7:0] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") 0x01 R0 R1 R2 R3 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.40 SV port SAV timing (VPDEF_MODE:4, SVVDEF_SOLV:2) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 57 XTLI SCK SVO[9:2] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Gn-2 Gn-1 0x00 DVO[15:8] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Bn-2 Bn-1 0x00 DVO[7:0] (SVTDEF_R656="0", SBMSK_YMSH="1", SBMSK_CMSH="1") Rn-2 Rn-1 0x00 SVO[9:2] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Gn-2 Gn-1 0x00 EAV 0x01 DVO[15:8] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Bn-2 Bn-1 0xFF 0x00 0x01 DVO[7:0] (SVTDEF_R656="1", SBMSK_YMSH="1", SBMSK_CMSH="1") Rn-2 Rn-1 0x01 SHB (SVTDEF_HBE="0") SHB (SVTDEF_HBE="1") Figure 4.41 SV port EAV timing (VPDEF_MODE:4, SVVDEF_SOLV:2) 58 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.15.4. SV Port Control Signal Timing Figure 4.42 indicates the timing relation among Hsync (SHS port), Vsync (SVS port) and the Field ID (SFLD port), and the timing between the Hblank (SHB port) and Vblank (SVB port), on the SV port. The fixed delay from the first Hsync of odd field to the Vsync: HVDLYO=0 The fixed delay from the first Hsync of even field to the Vsync: HVDLYE=429(fv=60Hz), HVDLYE=432(fv=50Hz) SHB SVB End of V Blanking SVB Start of V Blanking SHS (HSDELAY_HST="0") SVS Start of Odd Field (HVDLYO-VSDELAY_VST)*T1 SVS Start of Even Field (HVDLYE-VSDELAY_VST)*T1 SFLD (SVCDEF_SFLDS="0") T1=1/fCKX1 Figure 4.42 SV port H-V timing Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 59 In addition, Figure 4.43 shows the timing of the SCBF/SFLD ports. SHS SVS SHB SVB (SVTDEF_VBE="0") SVB (SVTDEF_VBE="1") VBI Path Through Enabled Line(s) SCBF (SVCDEF_SCBFS="1") SCBF (SVCDEF_SCBFS="2", SVTDEF_VBE="0") SCBF (SVCDEF_SCBFS="3") Figure 4.43 SV port SCBF/SFLD pin timing 60 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.15.5. DV port Horizontal Timing The DV port output video signal interface timings shown in Figure 4.44 and Figure 4.45 for the case with video port mode (register VPDEF_MODE) set to "0", in Figure 4.46 and Figure 4.47 for the case with "1", and in Figure 4.48 and Figure 4.49 for the case with "3". Figure 4.50 shows the timing of the Target Ready signal on the DV port. Note:! DV Line outputs a data of an active video only. XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DCK (DVCDEF_DCKS="0", DVPOL_DCK="1") DTRDY (="1") DVO[15:8] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="1") Yn-2 Cbn-2 Yn-1 Crn-2 FF 00 00 EAV 8'h10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 DVAL (DVTDEF_R656="1", DVCDEF_DVALG="0") DVAL (DVTDEF_R656="1", DVCDEF_DVALG="1") DGHP (DVCDEF_DGHP="1") DGHP (DVCDEF_DGHP="0") DGVP (DVCDEF_DGVP="1") DGVP (DVCDEF_DGVP="0") Figure 4.44 DV port Horizontal timing (DVTDEF_R656:1 /VPDEF_MODE:0) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 61 XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DCK (DVCDEF_DCKS="0", DVPOL_DCK="1") DTRDY (="1") DVO[15:8] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="0") Yn-2 Cbn-2 Yn-1 Crn-2 8'h10 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 DVAL (DVTDEF_R656="0", DVCDEF_DVALG="0") DVAL (DVTDEF_R656="0", DVCDEF_DVALG="1") DGHP (DVCDEF_DGHP="1") DGHP (DVCDEF_DGHP="0") DGVP (DVCDEF_DGVP="1") DGVP (DVCDEF_DGVP="0") Figure 4.45 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:0) 62 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DTRDY (="1") DVO[15:8] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="1") Yn-4 Yn-3 8'h10 Yn-2 Yn-1 SAV2 SAV4 8'h10 EAV2 EAV4 8'h10 Y0 Y1 8'h10 Y2 Y3 8'h10 DVO[7:0] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="1") Cbn-4 Crn-4 8'h80 Cbn-2 Crn-2 SAV1 SAV3 8'h80 EAV1 EAV3 8'h80 Cb0 Cr0 8'h80 Cb2 Cr2 8'h80 DVAL (DVTDEF_R656="1", DVCDEF_DVALG="0") DGHP (DVCDEF_DGHP="0") DGHP (DVCDEF_DGHP="1") DGVP (DVCDEF_DGVP="0") DGVP (DVCDEF_DGVP="1") Figure 4.46 DV port Horizontal timing (DVTDEF_R656:1 /VPDEF_MODE:1) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 63 XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DTRDY (="1") DVO[15:8] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="0") Yn-6 Yn-5 8'h10 Yn-4 Yn-3 Yn-2 Yn-1 8'h10 Y0 Y1 8'h10 Y2 Y3 8'h10 Y4 Y5 8'h10 DVO[7:0] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="0") Cbn-6 Crn-6 8'h80 bn-4 Crn-4 Cbn-2 Crn-2 8'h80 Cb0 Cr0 8'h80 Cb2 Cr2 8'h80 Cb4 Cr4 8'h80 DVAL (DVTDEF_R656="0", DVCDEF_DVALG="0") DGHP (DVCDEF_DGHP="0") DGHP (DVCDEF_DGHP="1") DGVP (DVCDEF_DGVP="0") DGVP (DVCDEF_DGVP="1") Figure 4.47 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:1) 64 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DTRDY (="1") DVO[15:8] (VPDEF_MOD="3", VPDEF_DVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Yn-6 Yn-5 8'h00 Yn-4 Yn-3 Yn-2 Yn-1 8'h00 Y0 Y1 8'h00 Y2 Y3 Y4 Y5 Y6 Y7 8'h00 DVO[7:0] (VPDEF_MOD="3", VPDEF_DVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Cbn-6 Cbn-5 8'h00 Cbn-4 Cbn-3 Cbn-2 Cbn-1 8'h00 Cb0 Cb1 8'h00 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 8'h00 SVO[9:2] (VPDEF_MOD="3", VPDEF_SVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Crn-6 Crn-5 8'h00 Crn-4 Crn-3 Crn-2 Crn-1 8'h00 Cr0 Cr1 8'h00 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 8'h00 DVAL (DVCDEF_DVALG="0") DGHP (DVCDEF_DGHP="0") DGHP (DVCDEF_DGHP="1") DGVP (DVCDEF_DGVP="0") DGVP (DVCDEF_DGVP="1") Figure 4.48 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:3 /DVVDEF_DOLV:0) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 65 XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DTRDY (="1") DVO[15:8] (VPDEF_MOD="3", VPDEF_DVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Gn-6 Gn-5 8'h00 Gn-4 Gn-3 Gn-2 Gn-1 8'h00 G0 G1 8'h00 G2 G3 G4 G5 G6 G7 8'h00 DVO[7:0] (VPDEF_MOD="3", VPDEF_DVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Bn-6 Bn-5 8'h00 Bn-4 Bn-3 Bn-2 Bn-1 8'h00 B0 B1 8'h00 B2 B3 B4 B5 B6 B7 8'h00 SVO[9:2] (VPDEF_MOD="3", VPDEF_SVOE="1", DVVDEF_DOLV="2", DVVDEF_DRGB="0") Rn-6 Rn-5 8'h00 Rn-4 Rn-3 Rn-2 Rn-1 8'h00 R0 R1 8'h00 R2 R3 R4 R5 R6 R7 8'h00 DVAL (DVCDEF_DVALG="0") DGHP (DVCDEF_DGHP="0") DGHP (DVCDEF_DGHP="1") DGVP (DVCDEF_DGVP="0") DGVP (DVCDEF_DGVP="1") Figure 4.49 DV port Horizontal timing (DVTDEF_R656:0 /VPDEF_MODE:3 /DVVDEF_DOLV:2) 66 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet XTLI DCK (DVCDEF_DCKS="0", DVPOL_DCK="0") DTRDY (DVPOL_DTRDY="0") DTRDY (DVPOL_DTRDY="1") DVO[15:8] (VPDEF_MOD="0", VPDEF_DVOE="1", DVTDEF_R656="0") 8'h10 Cb0 8'h10 Y0 8'h10 Cr0 8'h10 Y1 8'h10 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 8'h10 DVAL (DVTDEF_R656="1", DVCDEF_DVALG="0") Figure 4.50 DV port Target Ready signal Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 67 4.16. Color Killer Feature 4.16.1. Color Killer Factors The color killer works under the logical OR condition of the following two factors: 1: BL (Burst Level) Color killer Color killer that works when the color-burst level goes lower than the preset level. (Presetting level using registers CKILLS_ALEV and CKILLS_RLEV) 2: VS (Video Standard) Color killer Color killer that works when input video signal not found among the configured video standards. However, this is not applicable if the automatic video standard automatic switching mode set to "Manual". (For the video standard setting, please refer to the register ATVM_VSTD) 4.16.2. Color Killing Color killer factors taking place, either of the followings works depending on register setting at CKILLS_MOD: - Bypassing YC separation circuit. -Chrominance signal forced off. 4.17. Video Standard Detection/Automatic Switching Circuit The XV750C is able to detect the following input video systems of the input vide signals, and automatically switches over to the detected system. NTSC-Jpn, NTSC-M NTSC-4.43 PAL-B, D, G, H, I, PAL-N PAL-M PAL-CombinationN PAL-60 SECAM Since judgment is not automatic on the setup mode, the distinction between NTSC-M and NTSC-Japan in the above (1), PAL-B, D, G, H, I and PAL-N in the above (3) is determined by specifying whether the setup exists in the register MNVM_MOD [7:5]. For PAL-M in the above (4), setup is usually on, but off also can be configured. The video mode judgment result can be confirmed by the register VMJDG_. 4.17.1. Video Standard Automatic Switching Mode The following 4 operation modes are selectable by the register settings on ATVM_. 68 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Manual: By setting color sub-carrier frequency (Fsc Mode), color modulation (Color Mode) and scan (Scan Mode), on the register MNVM_MOD, video mode can be forcedly configured. Single Auto: A single video mode can be specified. Detecting video mode other than the specified, color killer is going to be activated. In addition, synchronization (scan mode) will follow the detected mode. Group Auto: Multiple video modes can be specified, and switch able among the specified modes. scan (scan mode) will follow the detected mode even in the case not specified. Full Auto: On each mode of color sub-carrier frequency (Fsc Mode), color modulation (Color Mode) and scan (Scan Mode), operates in accordance to the detected result. However, When component signal is applied, only the scan mode (fv: 60Hz/50Hz) can be automatically switched (except manual setting.) For the register setting values, please refer to Table 4.13. Table 4.13 Settings for video mode automatic switching FULL Auto Video System NTSC-(Jpn),M NTSC-4.43 PAL-B,D,G,H,I,N PAL-M PAL-CombiN PAL-60 SECAM GROUP Auto ATVM "0xxx xxx1" "0x1x xxxx" "0xxx xx1x" "0xxx 1xxx" "0xx1 xxxx" "01xx xxxx" "0xxx x1xx" SINGLE Auto ATVM "0000 0001" "0010 0000" "0000 0010" "0000 1000" "0001 0000" "0100 0000" "0000 0100" Manual ATVM "0000 0000" "0000 0000" "0000 0000" "0000 0000" "0000 0000" "0000 0000" "0000 0000" ATVM "1xxx xxxx" "1xxx xxxx" "1xxx xxxx" "1xxx xxxx" "1xxx xxxx" "1xxx xxxx" "1xxx xxxx" MNVM_ MDD "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" MNVM_ MDD "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" MNVM_ MDD "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" "x xxxx" MNVM_ MDD "0 0000" "0 1000" "0 1011" "0 0000" "1 0010" "0 1010" "0 0111" x: Don't care Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 69 4.18. VBI Path-through Data Output Settings on the registers VBPLS0_ and VBPLS1_, avail 27MHz sampling data of the specified line (For specifying the line, please refer to "5 Interface Registers" on page 78) as output at the image data output SV port or DV port. Please refer to the relevant register VBIDEF_. For the output port and register settings of the timing signal "VBI Term" indicate VBI data under output, please refer to "4.15.1 Timing Output Pins" on page.49. In addition, by setting the register SVTDEFVBE, SVB (vertical blanking signal in the SV Line) can be activated during the VBI Path-through output interval. For more detail please see Figure 4.43 Note! Please be careful if VBI Path-through being specified, VBI data extraction shall not avail. 4.19. VBI Data Extraction Circuit With this circuit, data extraction during the vertical blanking-interval (closed caption, CGMS and WSS.) becomes available. The extracted data can be read at register via a VBI FIFO. Table 4.14 indicates the reference standards of the supported systems. Table 4.14 The reference standards for VBI data extraction Expression Closed Caption CGMS(CGMS-A) System 525/60 525/60 Line 21/284 20/283 Org. EIA IEC Doc. NO. EIA-608 IEC61880 Doc. Title EIA Standard / Recommended Practice for Line 21 Data Service International Standard / Video systems (525/60) - Video and accompanied data using the vertical blanking interval - Analogue interface Recommendation ITU-R BT.1119 / Wide - Screen Signaling For Broadcasting WSS 625/50 23 ITU ITU-R BT.1119 Using GPIO status output mode, it is also possible to give receiving CGMS or wide screen information output to the GPIO port. As to the DPIO port, please refer to " 4.21 GPIO port" on page 73. For setting Closed Caption, CGMS and WSS detection, please refer to register VBELS_. Note! In case specifying VBI Path-through, please be careful as VBI data cannot be extracted. 4.19.1. Read-out Using VBI FIFO The XV750C is provided with a FIFO for the VBI extracted data output via host interface registers. The FIFO is 16 stages deep. Using the register VBFDEF_, writing mode etc. into VBI FIFO can be specified. When reading data from VBI FIFO, first read register FSTS_VBNE , "1" there means there are data in the VBI FIFO, please read the concerned data and information by reading the register VBINF_ VBRD_. For the details of the registers, please refer to "5 Interface Registers" on page 78. 70 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.20. Interrupt Detecting Interrupt event, the XV750C produces output interrupt signal at the IRQ_N port. Relevant registers: FIRQ_ (FIFO related interrupt event) MIRQ_ (Other miscellaneous interrupt event) FIMSK_ (FIFO related interrupt masking event) MIMSK_ (Other miscellaneous interrupt masking event) 4.20.1. Interrupt Events Interrupt events are as listed below: FIFO related interrupt: DV port FIFO becoming not empty DV port FIFO becoming almost empty DV port FIFO becoming almost full DV port FIFO becoming overflowed VBI FIFO becoming not empty VBI FIFO becoming almost empty VBI FIFO becoming almost full VBI FIFO becoming overflowed Other miscellaneous interrupt Video Mode being changed Video input sync being detected Video input going out of synchronization Standard signal being detected Non-standard signal being detected Interlaced scanning being detected Non-Interlaced scanning being detected Copy control data being changed 4.20.2. Interrupt Masks Each interrupt event described above can be independently masked. If any interrupt event taking places during interrupt being masked, no interrupt will happen but the situation will be held. In this case, when the interrupt masking released, the interrupt takes place. To allow the interrupt only after masking being removed, clear any interrupt event before releasing the concerned interrupt masking (by writing "1" into the corresponding bit in the register FIRQ_ and MIRQ_) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 71 4.20.3. Interrupt Signal Timing The timing of the interrupt request signal is shown here. Figure 4.51 represents the case where all the interrupt events are reset by the registers FIRQ_ and MIRQ_. Figure 4.52 shows the case where an unmasked interrupt event exists despite interrupt event has been reset by the register MIRQ_. CKX1 tDLY tDLY IRQ_N Interruption Request MIRQ clear Figure 4.51 Interrupt signal timing (1) CKX1 tDLY tDLY tDLY IRQ_N Interruption Request MIRQ clear Figure 4.52 Interrupt signal timing (2) 72 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.21. GPIO Port The XV750C has a 10-bits GPIO port. Register IO mode and Status Output mode can be selected for each of the two groups of upper 2 bits and lower 8 bits in the GPIO 10 bits. The upper two bits can be used also as the DV Line control timing output pins (DGP output mode). GPIO lower 8 bits Register IO mode: Status Output mode: GPIO upper 2 bits Register IO mode: Status Output mode: DGP Output mode: CFR/CFS Output mode: Register GPMD_GPSOH=0 Register GPMD_GPSOH=1 Register GPMD_GPSOH=2 Register GPMD_GPSOH=3 Register GPMD_GPSOL=0 Register GPMD_GPSOL=1 4.21.1. Register IO Mode By setting the register GPDIR_GPDIR, input/output can be specified for each bit. Actual read/write is performed through the register GPIOD_GPIOD. Please refer to "5.2 Register Details" on page.84 for the details. 4.21.2. Status Output Mode Using registers GPMD_GPSSL and GPMD_GPSSH, the address of the internal status can be specified. Please refer to "5.2. Register Details" on page.84 for the details. Table 4.15 shows the registers that can be used for output. In this table, only the lower two bits of addresses from 0x02 to 0x05 can be used for output in the upper two bits of GPIO. Table 4.15 Registers usable for GPIO Output Address 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0xAB WSSTS Wide Screen Status VBINF VBI FIFO Informations VBRD VBI FIFO Read Data CFSINF Color Field Seqence Information Read Write R R R R R R R R MSB 7 CONF VBFL NINT 1 rsv DETE VBERR VBRD 7 rsv LSB 0 SCNM DVNE FSCL VCXO 0 ASPO 0 VBID 0 VBRD 0 CFSQ 0 Default Name VMJDG Video Mode Judgement FSTS FIFO Status MSTS Misc. Status 6 rsv VBAF NINT 0 AGAT 2 DETO rsv VBRD 6 rsv 5 SUPM VBAE NSTD AGAT 1 ASPE 1 VBWN 1 VBRD 5 rsv 4 FSCM 1 VBNE TBCE AGAT 0 ASPE 0 VBWN 0 VBRD 4 rsv 3 FSCM 0 DVFL CKON rsv POS VBFLD VBRD 3 CONF 2 COLM 1 DVAF BBON PJCON FORM rsv VBRD 2 CFSQ 2 1 COLM 0 DVAE SDET VCXO 1 ASPO 1 VBID 1 VBRD 1 CFSQ 1 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 73 4.21.3. DGP2, 3 Signal Output The upper two bits of GPIO can be used as the control timing output pins for the DV Line. Please refer to the registers DVGDEF_DGP2 and DVGDEF_DGP3 for the details. 4.21.4. CFR/CFS (Color Field Reset/Strobe) Signal Output The upper two bits of GPIO can use GPIO lower 8 bits as CFR/CFS signal. This signal can also be fed to pins SCBF and SFLD. 4.22. I2C Interface The XV750C has an I2C bus interface as the external host interface. It supports up to Fast-Mode. Table 4.16 shows the slave addresses. By the setting of the IOAS pin, slave address can select two addresses. Table 4.16 I2C slave addresses IOAS Low High A6 1 1 A5 0 0 A4 0 0 A3 0 0 A2 1 1 A1 0 0 A0 0 1 RW X X Figure 4.53 and Figure 4.54 show the write and read sequence timing respectively. In addition, the write and read timings when accessed continuously are shown in Figure 4.55 and Figure 4.56 respectively. 74 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet I2C Bus Write Sequence Start Sequence Stop Sequence SCL Ack driven by XV750 SDA SLVA (6) SLVA (5) SLVA (1) SLVA (0) SUBA (7) SUBA (6) SUBA (2) SUBA (1) Ack driven by XV750 SUBA (0) DATA (7) DATA (6) DATA (2) DATA (1) Ack driven by XV750 DATA (0) SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" R/W="L" Register's Address(8bit) Write Data(8bit) Figure 4.53 I C Bus write sequence 2 I2C Bus Read Sequence Start Sequence Stop Sequence SCL Ack driven by XV750 SDA SLVA (6) SLVA (5) SLVA (1) SLVA (0) SUBA (7) SUBA (6) SUBA (2) SUBA (1) Ack driven by XV750 SUBA (0) to "A" SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" Start Sequence R/W="L" Register's Address(8bit) Stop Sequence "A" SLVA (6) SLVA (5) SLVA (1) SLVA (0) Ack driven by XV750 DATA (7) DATA (6) DATA (2) DATA (1) not Ack driven by Master DATA (0) SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" R/W="H" Read Data(8bit) Figure 4.54 I C Bus read sequence 2 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 75 I2C Bus Continuous Write Sequence Start Sequence SCL Ack driven by XV750 SDA SLVA (6) SLVA (5) SLVA (1) SLVA (0) SUBA (7) SUBA (6) SUBA (2) SUBA (1) Ack driven by XV750 SUBA (0) DATA0 DATA0 (7) (6) to "A" SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" W="L" Register's Address(8bit) Write Data @SUBA (8bit) Stop Sequence "A" DATA0 (2) Ack driven by XV750 DATA0 DATA0 (1) (0) DATA1 DATA1 (7) (6) Ack driven by XV750 DATA1 DATA1 DATA1 (2) (1) (0) DATA2 DATA2 (7) (6) Ack driven by XV750 DATA2 DATA2 (1) (0) Write Data @(SUBA+1) (8bit) Write Data @(SUBA+2) (8bit) Figure 4.55 I C Bus write sequence (continuous access) 2 I2C Bus Continuous Read Sequence Start Sequence Stop Sequence SCL Ack driven by XV750 SDA SLVA (6) SLVA (5) SLVA (1) SLVA (0) SUBA (7) SUBA (6) SUBA (2) SUBA (1) Ack driven by XV750 SUBA (0) to "A" SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" Start Sequence R/W="L" Register's Address(8bit) "A" SLVA (6) SLVA (5) SLVA (1) SLVA (0) Ack driven by XV750 DATA0 DATA0 (7) (6) Ack driven by XV750 DATA0 DATA0 DATA0 (2) (1) (0) DATA1 DATA1 (7) (6) to "B" SLVA=0x44(7bit): if IOAS="L" SLVA=0x45(7bit): if IOAS="H" R/W="H" Read Data @SUBA (8bit) Read Data @(SUBA+1) (8bit) Stop Sequence "B" Ack driven by XV750 DATA1 DATA1 DATA1 (2) (1) (0) DATA2 DATA2 (7) (6) not Ack driven by Master DATA2 DATA2 DATA2 (2) (1) (0) Read Data @(SUBA+1) (8bit) Read Data @(SUBA+2) (8bit) Figure 4.56 I C Bus read sequence (continuous access) 2 76 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 4.23. Anti-Copy Protection The XV750C is provided with a detection function based on "SPECIFICATION FOR DETECTION OF THE MACROVISION COPY PROTECTION PROCESS As Used On 525/60 and 625/50 DVD, STB and Pre-Recorded VHS Cassette Analog Video Outputs Revision 1.00". Macrovision certification test) For more details, please refer to MacroVison TM. (Passed the 4.24. JTAG The XV750C contains a JTAG circuit. For more details, please contact IIX Inc. 4.25. Test Pattern Generator The XV750C can output color bar pattern, ramp pattern and raster pattern for testing. Each color level of the pattern output is as shown in the Table 4.17. The relative registers are TPGEN_MODE*A TPGEN_PICS*ATPGEN_AMPS White Y Cb Cr Y Cb Cr Y Cb Cr Y Cb Cr 235 128 128 180 128 128 235 128 128 235 128 128 Yellow 210 16 146 162 44 142 210 16 146 162 44 142 Cyan 170 166 16 131 156 44 170 166 16 131 156 44 Magenta Green NTSC 100% 145 106 584 202 34 222 NTSC 75% Red 81 90 240 65 100 212 81 90 240 65 100 212 Blue 41 240 110 35 212 114 41 240 110 35 212 114 Black 16 128 128 16 128 128 16 128 128 16 128 128 112 72 58 PAL 100% 84 184 198 106 202 222 84 184 198 145 54 34 PAL 75% 112 72 58 Table 4.17 Color Level (8bits digital range) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 77 5. Interface Registers The XV750C has various interface registers to configure various flags, image adjustment, mode settings and parameter settings. The interface registers can be configured via the I2C bus interface. 5.1. List of Registers Table 5.1 shows the list of all registers. For the detailed explanation, please refer to "5.2 Register Details" on page.84. Table 5.1 List of interface registers Address Flags and Status 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D WSSTS Wide Screen Status VBINF VBI FIFO Informations VBRD VBI FIFO Read Data DCCD Detected Copy Control Data FIRQ FIFO Interrupt Request MIRQ Misc. Interrupt Request GPIOD General Purpose IO Read Write Data VMJDG Video Mode Judgement FSTS FIFO Status MSTS Misc. Status Read Write R R R R R R R R R R R/W R/W W/R W/R W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) MSB 7 PRDC 7 PRDC 15 CONF VBFL NINT 1 rsv DETE VBERR VBRD 7 CSTYP VBOV DCCD GPIOD 7 rsv LSB 0 PRDC 0 PRDC 8 SCNM DVNE FSCL VCXO 0 ASPO 0 VBID 0 VBRD 0 DCCD 0 DVNE VMCLM GPIOD 0 GPIOD 8 0x00 0x00 0x00 0x00 0x00 0x00 Default Name PRDC Product Code 6 PRDC 6 PRDC 14 rsv VBAF NINT 0 AGAT 2 DETO rsv VBRD 6 CSDET VBAF NINT GPIOD 6 rsv 5 PRDC 5 PRDC 13 SUPM VBAE NSTD AGAT 1 ASPE 1 VBWN 1 VBRD 5 AGCP VBAE INT GPIOD 5 rsv 4 PRDC 4 PRDC 12 FSCM 1 VBNE TBCE AGAT 0 ASPE 0 VBWN 0 VBRD 4 PSDET VBNE NSTD GPIOD 4 rsv 3 PRDC 3 PRDC 11 FSCM 0 DVFL CKON rsv POS VBFLD VBRD 3 rsv DVOV STD GPIOD 3 rsv 2 PRDC 2 PRDC 10 COLM 1 DVAF BBON PJCON FORM rsv VBRD 2 rsv DVAF NSDET GPIOD 2 rsv 1 PRDC 1 PRDC 9 COLM 0 DVAE SDET VCXO 1 ASPO 1 VBID 1 VBRD 1 DCCD 1 DVAE SDET GPIOD 1 GPIOD 9 Picture Tuning 0x10 0x11 0x12 0x13 0x14 0x15 CONT Contrast Trimmer BRTT Brightness Trimmer APCOR Apeature Correction CLMK Color Level Trimmer CONT CONT CONT CONT CONT CONT CONT CONT 7 6 5 4 3 2 1 0 BRTT BRTT BRTT BRTT BRTT BRTT BRTT rsv 6 5 4 3 2 1 0 CORG CORG rsv WEIT WEIT WEIT APBW APBW 1 0 2 1 0 1 0 CHRMK CHRMK CHRMK CHRMK CHRMK CHRMK CHRMK CHRMK 7 6 5 4 3 2 1 0 COLUM COLUM COLUM COLUM COLUM COLUM COLUM COLUM 7 6 5 4 3 2 1 0 COLVM COLVM COLVM COLVM COLVM COLVM COLVM COLVM 7 6 5 4 3 2 1 0 78 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Address 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E TRPFCHR TRAP Filter Characteristics BPFCHR Band Pass Filter Characteristics BELCHR BELL Filter Characteristics DEMPCHR De-Emphasys Filter Characteristics PROFLT Programmable Filter Parameter Setting VENHANC Virtical Enhancer Read Write W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) MSB 7 HUET 1 HUET 9 rsv rsv rsv rsv ADRS 7 DATA 7 CORG 1 LSB 0 UVOF 0 HUET 2 CHRS 0 CHRS 0 SIFT 0 CHRS 0 ADRS 0 DATA 0 ENB Default 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 Name HUET Hue Trimmer 6 HUET 0 HUET 8 rsv rsv rsv rsv ADRS 6 DATA 6 CORG 0 5 rsv HUET 7 rsv rsv SHAP 1 rsv ADRS 5 DATA 5 rsv 4 UVOF 4 HUET 6 rsv rsv SHAP 0 rsv ADRS 4 DATA 4 WEIT 2 3 UVOF 3 HUET 5 rsv rsv rsv rsv ADRS 3 DATA 3 WEIT 1 2 UVOF 2 HUET 4 rsv CHRS 2 rsv rsv ADRS 2 DATA 2 WEIT 0 1 UVOF 1 HUET 3 CHRS 1 CHRS 1 SIFT 1 CHRS 1 ADRS 1 DATA 1 rsv Configuration 0x20 AIMS Analog Input MUX Selection 0x21 ATVM Automatic Video Mode Settings 0x22 MNVM Manual Video Mode Settings COMBDEF 0x23 Comb Filter Definition 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 CGFXA C Ch. Fixed Gain for Analog Amp. PGFXA P Ch. Fixed Gain for Analog Amp. YGFXA Y Ch. Fixed Gain for Analog Amp. LGFXD Luminance Fixed Gain for Digital AGC ACCDEF Automatic Chrominance Gain Control Definitions PAGCC Peak AGC Control Reserved AGCDEF Automatic Gain Control Definitions W/(R) W/(R) W/(R) W/(R) W/(R) rsv W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) rsv FULL MOD 7 Rsv P3HT 3 rsv rsv AGMK 7 rsv rsv PAGM 7 rsv REOFS 3 rsv FXGD 0 FXGD 8 rsv ACMK 5 rsv rsv rsv rsv VSTD 6 MOD 6 rsv P3HT 2 rsv rsv AGMK 6 rsv rsv PAGM 6 rsv REOFS 2 rsv rsv FXGD 7 rsv ACMK 4 rsv rsv rsv rsv VSTD 5 MOD 5 PAFS P3HT 1 rsv LMT AGMK 5 rsv rsv PAGM 5 rsv REOFS 1 rsv rsv FXGD 6 LMT ACMK 3 rsv rsv rsv rsv VSTD 4 MOD 4 PCOMB P3HT 0 rsv FRZ AGMK 4 rsv rsv PAGM 4 rsv REOFS 0 rsv rsv FXGD 5 FRZ ACMK 2 rsv rsv rsv rsv VSTD 3 MOD 3 rsv P3LT 3 rsv rsv AGMK 3 rsv rsv PAGM 3 SETM rsv rsv rsv FXGD 4 rsv ACMK 1 rsv rsv rsv rsv VSTD 2 MOD 2 ACMS P3LT 2 rsv MOD 2 AGMK 2 AGTC 2 rsv PAGM 2 SETC 2 RETC 2 FXGA 2 rsv FXGD 3 rsv ACMK 0 ACTC 2 FXGA 2 FXGA 2 SELP 1 VSTD 1 MOD 1 BPFS P3LT 1 rsv MOD 1 AGMK 1 AGTC 1 HVSL 1 PAGM 1 SETC 1 RETC 1 FXGA 1 rsv FXGD 2 MOD 1 rsv ACTC 1 FXGA 1 FXGA 1 SELP 0 VSTD 0 MOD 0 COMS P3LT 0 rsv MOD 0 AGMK 0 AGTC 0 HVSL 0 PAGM 0 SETC 0 RETC 0 FXGA 0 rsv FXGD 1 MOD 0 rsv ACTC 0 FXGA 0 FXGA 0 0x00 0x7F 0x80 0x14 0xCB 0x22 0x00 0x04 0x02 0x7F 0x04 0x84 0x01 0x00 0x80 0x23 0x00 0x04 0x01 0x01 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 79 Address 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 Name CHGFXD Chrominance Fixed Gain for Digital ACC Read Write W/(R) W/(R) UVGFXD W/(R) U/V Fixed Gain for Digital ACC W/(R) SBMSK SV Port Blanking Mask Settings VBISLC VBI Slice Level Control PJCSW Pixel Jitter Canceller Switch TBCDEF TBC Definitions VCXODEF VCXO Definitions BBDEF Blue-back Definitions VBIDEF VBI Definitions VBPLS0 VBI Path Through Line Selection #0 VBPLS1 VBI Path Through Line Selection #1 VBELS VBI Extractor Line Settings W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) YCDELAY YC Delay HSDELAY HS Delay VSDELAY VS Delay ACTWINS Active Video Window Settings W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) SCROPDEF SV Port Cropping Definitions SCROPH SV Port Cropping H Settings W/(R) W/(R) W/(R) W/(R) MSB 7 FXGD 0 FXGD 8 FXGD 0 FXGD 8 rsv MOD rsv RLS 3 rsv rsv rsv FIDSL 6 rsv FXGD 7 rsv FXGD 7 rsv LEV 6 rsv RLS 2 rsv rsv rsv 5 rsv FXGD 6 rsv FXGD 6 rsv LEV 5 rsv RLS 1 rsv rsv rsv 4 rsv FXGD 5 rsv FXGD 5 rsv LEV 4 rsv RLS 0 HCTLE rsv rsv 3 rsv FXGD 4 rsv FXGD 4 CMSV LEV 3 rsv RLE 1 rsv rsv rsv 2 rsv FXGD 3 rsv FXGD 3 CMSH LEV 2 AUTO RLE 0 rsv MOD 2 rsv 1 rsv FXGD 2 rsv FXGD 2 YMSV LEV 1 CPJC MOD MOD 1 MOD 1 SVPTE LSB 0 rsv FXGD 1 rsv FXGD 1 YMSH LEV 0 YPJC ENB MOD 0 MOD 0 DVPTE Default 0x00 0x80 0x00 0x80 0x0F 0x20 0x07 0x03 0x10 0x01 0x00 0x11 0x11 0x91 0x91 0xBB 0xBB 0xAA 0xAA 0xCC 0xCC 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x12 0x00 0x68 VBPSL VBPSL VBPSL VBPSL VBPSL VBPSL VBPSL 6 5 4 3 2 1 0 FIDEL VBPEL VBPEL VBPEL VBPEL VBPEL VBPEL VBPEL 6 5 4 3 2 1 0 FIDSL VBPSL VBPSL VBPSL VBPSL VBPSL VBPSL VBPSL 6 5 4 3 2 1 0 FIDEL VBPEL VBPEL VBPEL VBPEL VBPEL VBPEL VBPEL 6 5 4 3 2 1 0 CCELO CCELO CCELO CCELO CCSLO CCSLO CCSLO CCSLO 3 2 1 0 3 2 1 0 CCELE CCELE CCELE CCELE CCSLE CCSLE CCSLE CCSLE 3 2 1 0 3 2 1 0 CGELO CGELO CGELO CGELO CGSLO CGSLO CGSLO CGSLO 3 2 1 0 3 2 1 0 CGELE CGELE CGELE CGELE CGSLE CGSLE CGSLE CGSLE 3 2 1 0 3 2 1 0 WSELO WSELO WSELO WSELO WSSLO WSSLO WSSLO WSSLO 3 2 1 0 3 2 1 0 WSELE WSELE WSELE WSELE WSSLE WSSLE WSSLE WSSLE 3 2 1 0 3 2 1 0 ODLC ODLC ODLC rsv ODLY ODLY ODLY rsv 2 1 0 2 1 0 HST HST HST HST HST HST HST HST 7 6 5 4 3 2 1 0 VST VST VST VST VST VST VST VST 7 6 5 4 3 2 1 0 WINL WINL WINL WINL rsv rsv rsv rsv 3 2 1 0 WINR WINR WINR WINR rsv rsv rsv rsv 3 2 1 0 WINT WINT WINT WINT rsv rsv rsv rsv 3 2 1 0 WINB WINB WINB WINB rsv rsv rsv rsv 3 2 1 0 rsv rsv rsv rsv rsv rsv MOD MOD 1 0 CRPHS CRPHS CRPHS CRPHS CRPHS CRPHS CRPHS CRPHS 7 6 5 4 3 2 1 0 rsv rsv rsv rsv rsv rsv rsv CRPHS 8 CRPHA CRPHA CRPHA CRPHA CRPHA CRPHA CRPHA CRPHA 7 6 5 4 3 2 1 0 80 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Address 0x55 Read Write W/(R) MSB 7 rsv LSB 0 CRPHA 8 Default 0x01 Name 6 rsv 5 rsv 4 rsv 3 rsv 2 rsv 1 rsv 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 SCROPV SV Port Cropping V Settings W/(R) W/(R) W/(R) W/(R) CRPVS 7 rsv CRPVA 7 rsv CRPHS 7 rsv CRPHA 7 rsv CRPVS 7 rsv CRPVA 7 rsv CKLE CODE 5 rsv TBCT 6 rsv rsv rsv rsv rsv SCAL 7 SCAL 15 rsv rsv VSCAL 7 VSCAL 15 rsv rsv AFEC 7 SEL3 1 CRPVS 6 rsv CRPVA 6 rsv CRPHS 6 rsv CRPHA 6 rsv CRPVS 6 rsv CRPVA 6 rsv MOD CODE 4 rsv TBCT 5 rsv rsv rsv rsv rsv SCAL 6 SCAL 14 rsv rsv VSCAL 6 VSCAL 14 rsv rsv AFEC 6 SEL3 0 CRPVS 5 rsv CRPVA 5 rsv CRPHS 5 rsv CRPHA 5 rsv CRPVS 5 rsv CRPVA 5 rsv rsv CODE 3 rsv TBCT 4 rsv rsv rsv OFST 5 FILT 5 SCAL 5 SCAL 13 OFST 5 VFILT 5 VSCAL 5 VSCAL 13 rsv rsv AFEC 5 SEL2 1 CRPVS 4 rsv CRPVA 4 rsv CRPHS 4 rsv CRPHA 4 rsv CRPVS 4 rsv CRPVA 4 rsv RLEV 1 CODE 2 rsv TBCT 3 rsv SFTL 4 rsv OFST 4 FILT 4 SCAL 4 SCAL 12 OFST 4 VFILT 4 VSCAL 4 VSCAL 12 rsv rsv AFEC 4 SEL2 0 CRPVS 3 rsv CRPVA 3 rsv CRPHS 3 rsv CRPHA 3 rsv CRPVS 3 rsv CRPVA 3 rsv RLEV 0 CODE 1 rsv TBCT 2 rsv SFTL 3 rsv OFST 3 FILT 3 SCAL 3 SCAL 11 OFST 3 VFILT 3 VSCAL 3 VSCAL 11 rsv rsv AFEC 3 SEL1 1 CRPVS 2 rsv CRPVA 2 rsv CRPHS 2 rsv CRPHA 2 rsv CRPVS 2 rsv CRPVA 2 rsv ALEV 2 CODE 0 rsv TBCT 1 rsv SFTL 2 INTO OFST 2 FILT 2 SCAL 2 SCAL 10 OFST 2 VFILT 2 VSCAL 2 VSCAL 10 rsv rsv AFEC 2 SEL1 0 DCROPH DV Port Cropping H Settings W/(R) W/(R) W/(R) W/(R) CRPVS 1 CRPVS 9 CRPVA 1 CRPVA 9 CRPHS 1 rsv CRPHA 1 CRPHA 9 CRPVS 1 rsv CRPVA 1 CRPVA 9 ALEV 1 TBCE rsv TBCT 0 rsv SFTL 1 INTI OFST 1 FILT 1 SCAL 1 SCAL 9 OFST 1 VFILT 1 VSCAL 1 VSCAL 9 DCROPV DV Port Cropping V Settings W/(R) W/(R) W/(R) W/(R) CKILLS Color Killer Settings FHCTLS FH Control Setting W/(R) W/(R) W/(R) W/(R) CRPVS 0 CRPVS 8 CRPVA 0 CRPVA 8 CRPHS 0 CRPHS 8 CRPHA 0 CRPHA 8 CRPVS 0 CRPVS 8 CRPVA 0 CRPVA 8 ALEV 0 rsv rsv rsv TC SFTL 0 VFLTS OFST 0 FILT 0 SCAL 0 SCAL 8 OFST 0 VFILT 0 VSCAL 0 VSCAL 8 0x06 0x00 0xE6 0x01 0x12 0x00 0x68 0x01 0x0A 0x00 0xE0 0x01 0x81 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x20 0x00 0x80 0x00 0x20 0x00 0x40 0x03 0x00 0x9F 0x00 HSYNC Hsync Setting VSSFT Vsync Shift Setting SCALM Scaller Mode HPHS Horizontal Phase Settings HFILT Horizontal Filter Setting HSCAL Horizontal Scale Settings VPHS Vertical Phase Settings VFILT Vertical Filter Setting VSCAL Vertical Scale Settings W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) Scaller Settings 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 System Configurations 0x80 LPWCS Low Power Consumption 0x81 Control Settings 0x82 0x83 AINDEF Analog Input Definitions AUTO PINE OFPWM OFSCE AFEC AFEC 1 0 SEL0 SEL0 1 0 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 81 Address 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 Name ICHX Input Channel Cross-Over VSMPDEF Video Sampling Definitions ICMPNDEF Input Component Definitions Reserved VPDEF Output Video Port Definitions SVVDEF SV Port Video Definitions DVVDEF DV Port Video Definitions SVTDEF SV Port Timing Definitions DVTDEF DV Port Timing Definitions SVCDEF SV Port Control Signal Definitions DVCDEF DV Port Control Signal Definitions DVGDEF DV Port General Signal Definitions SVPOL SV Port Polarities DVPOL DV Port Polarities GPMD General Purpose IO Mode GPDIR General Purpose IO pin Direction Settings FIMSK FIFO Interrupt Mask MIMSK Misc. Interrupt Mask DVFLV DV Port FIFO Trigger Level VBFLV VBI FIFO Trigger Level VBFDEF VBI FIFO Definitions PWMS PWM Settings VCXOS VCXO Settings CFRDEF Color Field Reset Signal Definitions SYNCDEF Sync Detection Definitions PDLDEF Pedestal Level Detection Definitions Read Write W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) W/(R) MSB 7 rsv rsv rsv rsv SVCOE S10B OECV rsv rsv rsv rsv OECV1 OECV3 SCK DCK GPSSH 1 GPDIR 7 SOUT VBOV DCCD AFL 3 rsv 6 rsv rsv rsv rsv DVCOE rsv rsv rsv rsv SFLDS 2 DGVP DGP1 2 DGP3 2 rsv rsv GPSSH 0 GPDIR 6 SIN VBAF NINT 5 DPCH 1 rsv rsv rsv SVOE SOLM DOLM rsv rsv SFLDS 1 rsv DGP1 1 DGP3 1 SFLD DTRDY GPSSL 2 GPDIR 5 rsv VBAE INT 4 DPCH 0 rsv rsv rsv DVOE SRGB 1 DRGB 1 rsv rsv SFLDS 0 DGHP DGP1 0 DGP3 0 SCBF DVAL GPSSL 1 GPDIR 4 rsv VBNE NSTD 3 DCCH 1 rsv rsv rsv ADEM SRGB 0 DRGB 0 rsv rsv rsv rsv OECV0 OECV2 SVB DGP1 GPSSL 0 GPDIR 3 rsv DVOV STD AEL 3 rsv CCERR TC 3 VXOFS 3 VXTC 3 rsv LINE 0 rsv MOD 2 DCCH 0 rsv rsv rsv MOD 2 rsv rsv VBE rsv SCBFS 2 rsv DGP0 2 DGP2 2 SHB DGP0 1 DYCH 1 SMPC LEV 1 rsv MOD 1 SOLV 1 DOLV 1 HBE rsv SCBFS 1 DVALG DGP0 1 DGP2 1 SVS DGVP LSB 0 DYCH 0 DCFB LEV 0 rsv MOD 0 SOLV 0 DOLV 0 R656 R656 SCBFS 0 DCKS DGP0 0 DGP2 0 SHS DGHP GPSOL GPDIR 0 GPDIR 8 DVNE VMCLM AEL 0 AEL 0 WCC TC 0 VXOFS 0 VXTC 0 FLDN 0 WID SYRT 0 TC 0 Default 0x24 0x00 0x00 0x00 0x80 0x00 0x01 0x01 0x00 0x01 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x88 0x22 0x00 0x80 0x00 0x88 0x73 0x01 0x00 0x1C GPSOH GPSOH 1 0 GPDIR GPDIR 2 1 rsv GPDIR 9 DVAF DVAE NSDET AEL 2 AEL 2 WWSS TC 2 VXOFS 2 VXTC 2 rsv rsv rsv TC 2 SDET AEL 1 AEL 1 WCGMS TC 1 VXOFS 1 VXTC 1 FLDN 1 rsv SYRT 1 TC 1 AFL AFL AFL 2 1 0 AFL AFL AFL 2 1 0 CGCRC CCNULL WSERR CGERR MOD VXOFS 7 VXPOL rsv LINE 4 rsv rsv rsv VXOFS 6 rsv FLDP 2 LINE 3 rsv rsv rsv VXOFS 5 rsv FLDP 1 LINE 2 rsv rsv TC 4 VXOFS 4 rsv FLDP 0 LINE 1 rsv ADPT 82 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Address 0xA2 Read Write W/(R) MSB 7 AMPS 2 LSB 0 MODE 0 Default 0x00 Name TPGENS Test Pattern Generator Settings 6 AMPS 1 5 AMPS 0 4 PICS 2 3 PICS 1 2 PICS 0 1 MODE 1 Information and Data SNRMON 0xA8 Signal Noise Ratio Monitor 0xA9 0xAA 0xAB 0xAC HLJINF H-Lock Judgement Information CFSINF Color Field Seqence Information VTRDET VTR Detection R R R R R SLEV 7 NLEV 7 LCKE 7 rsv rsv SLEV 6 NLEV 6 LCKE 6 rsv rsv SLEV 5 NLEV 5 LCKE 5 rsv rsv SLEV 4 NLEV 4 LCKE 4 rsv rsv SLEV 3 NLEV 3 LCKE 3 CONF rsv SLEV 2 NLEV 2 LCKE 2 CFSQ 2 WEAK SLEV 1 NLEV 1 LCKE 1 CFSQ 1 VTR 1 SLEV 0 NLEV 0 LCKE 0 CFSQ 0 VTR 0 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 83 5.2. Register Details Here gives sample register explanation. (The register EXAMPLE_ is for explanatory purpose only and not existing.) First, please see the list of registers' main ID and bit map. Main ID is a summary of a number of relevant registers, having an underscore "_" at the end of the alphanumerical letter. EXAMPLE_ 0xFF 7 6 Name Example Register Address9 D7 0xFF rsv D6 LEV 2 D5 LEV 1 D4 LEV 0 D3 rsv D2 rsv R/W Write/Read D1 D010 MOD MOD 1 0 8 Next follows the table that describes registers included in the above main ID. Generally, a register representation has a sub-ID after the underscore. Identification11 Bit Width12 EXAMPLE_MOD 2 Description15 This register specifies a mode. 16 16 Value Operation or Status 0 Mode 0 1 Mode 1 Note17 Expression13 Binary Default14 0x0 The next register table follows. In this example, since the sub-IDs included in the main ID of EXAMPLE_ being MOD and LEV, the tables for the registers EXAMPLE_MOD and EXAMPLE_LEV follow. Identification Bit Width Expression Default EXAMPLE_LEV 3 2's Complement 0x1 Description This register sets the level..... Value Operation or Status -4 to +3 The level goes down if the value turns to minus, goes up if it turns to plus, based on zero (0) as its center. Note 7 8 Main ID for the register. Name column of the main ID. 9 Indicates the register's direction of access (read/write) 10 Address of the register. 0x means the representation is in hexadecimal 11 .Denotes each bit's meaning (sub ID) "rsv" represents the bit is reserved. Please note also that the addresses not described in "List of Registers" or "Register Details" are all reserved. 12 Register ID. Sub ID follows main ID. 13 Indicates the bit width of the register. 14 Represents register notation (binary, 2's complement etc.). 15 The default value of the register. 16 The description on the register. 17 The register values and its movement and/or description 17 Other notes or special comments will be described here. 84 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 5.2.1. Flag and Status PRDC_ 0x00 - 0x01 Name Product Code Address D7 PRDC 0x00 7 PRDC 0x01 15 R/W Read D1 PRDC 1 PRDC 9 D6 PRDC 6 PRDC 14 D5 PRDC 5 PRDC 13 D4 PRDC 4 PRDC 12 D3 PRDC 3 PRDC 11 D2 PRDC 2 PRDC 10 D0 PRDC 0 PRDC 8 Identification Bit Width PRDC_PRDC 16 Description Denotes the product code. Value Operation or Status 0xBB84 Product code Expression Binary Default - VMJDG_ 0x02 Name Video Mode Judgment Address D7 0x02 CONF R/W Read D1 COLM 0 Default - D6 rsv D5 SUPM D4 FSCM 1 D3 FSCM 0 D2 COLM 1 D0 SCNM Identification Bit Width Expression VMJDG_SCNM 1 Binary Description Displays the result of video mode judgment. (scan mode) Value Operation or Status 0 60(59.94)Hz, 525Line 1 50Hz, 625Line Note Effective only when the register VMJDG_CONF='1' Identification Bit Width Expression VMJDG_COLM 2 Binary Description Displays the result of video mode judgment. (color modulation) Value Operation or Status 0 NTSC 1 PAL 2 Reserved 3 SECAM Note Effective only when the register VMJDG_CONF='1' Identification VMJDG_ FSCM Description Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Default - Bit Width 2 Expression Binary Default - Advanced Information 85 Indicates the result of video mode judgment. (FSC mode) Value Operation or Status 0 3.579545MHz (NTSC-M, NTSC-Japan) 1 4.43361875MHz (PAL-B,D,G,H,I,N, PAL-60, NTSC-4.43) 2 3.57561149MHz (PAL-M) 3 3.58205625MHz (PAL-CombinationN) Note Effective only when the register VMJDG_CONF='1' Identification Bit Width VMJDG_SUPM 1 Description Indicates the setup mode actually working Value Operation or Status 0 Setup 0 (IRE) 1 Setup 7.5 (IRE) Note Expression Binary Default - Identification Bit Width Expression Default VMJDG_CONF 1 Binary Description Indicates the result of video mode judgement effective and effective or not of the registers VMJDG_SCNM, VMJDG_COLM, VMJDG_FSCM. Value Operation or Status 0 Ineffective 1 Effective Note FSTS_ 0x03 Name FIFO Status Address D7 0x03 VBFL R/W Read D1 DVAE D6 VBAF D5 VBAE D4 VBNE D3 DVFL D2 DVAF D0 DVNE Identification Bit Width Expression Default FSTS_DVNE 1 Binary Description Indicates the status that the DV port FIFO is not empty Value Operation or Status 0 DV port FIFO is empty 1 DV port FIFO is not empty (data exists in one or more stage) Note Identification Bit Width Expression FSTS_DVAE 1 Binary Description Indicates the status that the DV port FIFO is almost empty Value Operation or Status Default - 86 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 1 DV port FIFO is not almost empty DV port FIFO is almost empty Note The criterion is defined by the register DVFLV_AEL Identification Bit Width Expression FSTS_DVAF 1 Binary Description Indicates the status that the DV port FIFO is almost full. Value Operation or Status 0 DV port FIFO is not almost full. 1 DV port FIFO is almost full. Note The criterion is defined by the register DVFLVAFL. Identification Bit Width Expression FSTS_DVFL 1 Binary Description Indicates the status that the DV port FIFO is full. Value Operation or Status 0 DV port FIFO is not full. 1 DV port FIFO is full. Note Default - Default - Identification Bit Width Expression Default FSTS_VBNE 1 Binary Description Indicates the status that the VBI FIFO is not empty Value Operation or Status 0 VBI FIFO is empty. 1 VBI FIFO is not empty (data exists in one or more stage.) Note Identification Bit Width Expression FSTS_VBAE 1 Binary Description Indicates the status that the VBI FIFO is almost empty. Value Operation or Status 0 VBI FIFO is not almost empty. 1 VBI FIFO is almost empty. Note The criterion is defined by the register VBFLV_AEL Identification Bit Width Expression FSTS_VBAF 1 Binary Description Indicates the status that the VBI FIFO is almost full. Value Operation or Status 0 VBI FIFO is not almost full. 1 VBI FIFO is almost full. Note The criterion is defined by the register VBFLV_AFL. Default - Default - Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 87 Identification Bit Width FSTS_VBFL 1 Description Indicates the status that the VBI FIFO is full. Value Operation or Status 0 VBI FIFO is not full. 1 VBI FIFO is full. Note Expression Binary Default - MSTS_ 0x04 - 0x05 Name Misc. Status Address 0x04 0x05 R/W Read D1 SDET VCXO 1 D7 NINT 1 rsv D6 NINT 0 AGAT 2 D5 NSTD AGAT 1 D4 TBCE AGAT 0 D3 CKON rsv D2 BBON PJCON D0 FSCL VCXO 0 Identification Bit Width Expression Default MSTS_FSCL 1 Binary Description Indicates that internally generated color cub-carrier has locked-in with that of the input video signal. Value Operation or Status 0 Not locked-in 1 Locked-in Note Not effective when the video mode is SECAM Identification Bit Width Expression MSTS_SDET 1 Binary Description Indicates sync has detected in the input video signal. Value Operation or Status 0 Sync not detected 1 Sync detected Note Default - Identification Bit Width Expression MSTS_BBON 1 Binary Description Indicates the blue-back is being displayed. Value Operation or Status 0 Blue-back is not being displayed. 1 Blue-back is being displayed. Note Default - 88 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width MSTS_CKON 1 Description Indicates that the color killer circuit is working. Value Operation or Status 0 Color killer is not working. 1 Color killer is working. Note Expression Binary Default - Identification Bit Width Expression Default MSTS_TBCE 1 Binary Description Indicates that TBC error is occurring. (TBC memory overflow occurred) Value Operation or Status 0 TBC error not occurred. 1 TBC error occurred. Note Identification Bit Width Expression Default MSTS_NSTD 1 Binary Description Indicates that the input video signal is a non-standard signal. Value Operation or Status 0 Non-standard signal is not being received. 1 Non-standard signal is being received. Note Here, non-standard means the signal whose number of lines deviates from the standard. Identification Bit Width Expression Default MSTS_NINT 2 Binary Description Indicates that the input video signal is non-interlaced. Value Operation or Status 0 Non-interlaced signal is not received. 1 Non-interlaced signal is not received. 2 Non-interlaced signal is received (continuous odd field.) 3 Non-interlaced signal is received (continuous even field.) Note Identification Bit Width Expression MSTS_VCXO 2 Binary Description Indicates the status of VCXO operation. Value Operation or Status 0 Free run operation 1 Burst lock VCXO operation 2 H-lock (line-lock) VCXO operation 3 Reserved Note Default - Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 89 Identification Bit Width MSTS_PJCON 1 Description Indicates if PJC filter in operation or not. Value Operation or Status 0 PJC filter OFF 1 PJC filter on Note Expression Binary Default - Identification Bit Width MSTS_AGAT 3 Description Indicates analog gain level currently set Value Operation or Status 0-7 Analog gain Note Effective only at the time analog AGC in operation Expression Binary Default - WSSTS_ 0x06 Name Wide Screen Status Address D7 0x06 DETE R/W Read D1 ASPO 1 D6 DETO D5 ASPE 1 D4 ASPE 0 D3 POS D2 FORM D0 ASPO 0 Identification Bit Width Expression Default WSSTS_ASPO 2 Binary Description Indicates the aspect ratio of odd-field. Value Operation or Status 0 4:3 1 14:9 2 16:9 3 >16:9 Note Above value is set when WSS is detected while receiving the PAL signal. While the NTSC signal is applied, the bits are set when CGMS is detected as follows: WSSTS_ASPO[0] : CGMS Word0 bit1 (Odd Field) WSSTS_ASPO[1] : CGMS Word0 bit2 (Odd Field) The values are only valid when the register WSSTS_DETO is '1' while either NTSC or PAL signal is being received. Identification Bit Width WSSTS_FORM 1 Description Indicates the format of WSS. Value Operation or Status 0 Full 1 Letter Box Note Expression Binary Default - 90 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Above value is set when WSS is detected while receiving the PAL signal. Ineffective when receiving the NTSC signal. Effective only when the register WSSTS_DETO is '1'. Identification Bit Width Expression Default WSSTS_POS 1 Binary Description Indicates the position of WSS. Value Operation or Status 0 Center 1 Top Note Above value is set when WSS is detected while receiving the PAL signal. Ineffective when receiving the NTSC signal. Effective only when the register WSSTS_DETO is '1'. Identification Bit Width Expression Default WSSTS_ASPE 2 Binary Description Indicates the aspect ratio of even field Bit Operation or Status 0 CGMS Word0 bit1 (Even Field) 1 CGMS Word0 bit2 (Even Field) Note Above value is set when CGMS is detected while receiving the NTSC signal. Ineffective when receiving the PAL signal. Effective only when the register WSSTS_DETE is '1'. Identification Bit Width Expression Default WSSTS_DETO 1 Binary Description Indicates whether the odd-field information on WSSTS_ is effective or ineffective. Value Operation or Status 0 Ineffective 1 Effective Note Identification Bit Width Expression Default WSSTS_DETE 1 Binary Description Indicates that the even-field information on WSSTS_ is effective or ineffective. Value Operation or Status 0 Ineffective 1 Effective Note VBINF_ 0x07 Name VBI FIFO Information Address D7 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC D6 D5 D4 D3 D2 R/W Read D1 D0 Advanced Information 91 0x07 VBERR VBFNE VBWN 1 VBWN 0 VBFLD rsv VBID 1 Default - VBID 0 Identification Bit Width Expression VBINF_VBID 2 Binary Description Indicates the kinds of the oldest data stored in the VBI FIFO. Value Operation or Status 0 Closed caption 1 CGMS 2 WSS 3 Reserved Note Identification Bit Width Expression VBINF_VBFLD 1 Binary Description Indicates the field of the oldest data stored in the VBI FIFO. Value Operation or Status 0 Odd-field 1 Even-field Note Default - Identification Bit Width Expression Default VBINF_VBWN 2 Binary Description Indicates the word number of the oldest data stored in the VBI FIFO. Value Operation or Status 0 Word number = 0 1 Word number = 1 2 Word number = 2 3 Reserved Note Please refer to Table 5.2 for the detail on the relation between the word number and the data. Identification Bit Width Expression VBINF_VBFNE 1 Binary Description Indicates the existence of data stored in the VBI FIFO. Value Operation or Status 0 No data 1 Some data Note Default - Identification Bit Width Expression Default VBINF_VBERR 1 Binary Description Indicates the existence of error in the oldest data stored in the VBI FIFO. Value Operation or Status 0 No error 1 Some error Note 92 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet VBRD_ 0x08 Name VBI FIFO Read Data Address D7 VBRD 0x08 7 R/W Read D1 VBRD 1 D6 VBRD 6 D5 VBRD 5 D4 VBRD 4 D3 VBRD 3 D2 VBRD 2 D0 VBRD 0 Identification Bit Width Expression Default VBRD_VBRD 8 Binary Description Indicates the oldest data stored in the VBI FIFO. Value Operation or Status 0-255 VBI data (refer to Table 5.2.) Note The data will be de-queued from the VBI FIFO right after having read this register. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 93 Table 5.2 VBI FIFO register interface Data Type Closed Caption, Odd Field, 1st word, No error Closed Caption, Odd Field, 2st word, No error Closed Caption, Even Field, 1st word, No error Closed Caption, Even Field, 2st word, No error Closed Caption, Odd Field, 1st word, With error Closed Caption, Odd Field, 2st word, With error Closed Caption, Even Field, 1st word, With error Closed Caption, Even Field, 2st word, With error CGMS-A, Odd Field, 1st word, No error CGMS-A, Odd Field, 2nd word, No error CGMS-A, Odd Field, 3rd word, No error CGMS-A, Even Field, 1st word, No error CGMS-A, Even Field, 2nd word, No error CGMS-A, Even Field, 3rd word, No error CGMS-A, Odd Field, 1st word, With error CGMS-A, Odd Field, 2nd word, With error CGMS-A, Odd Field, 3rd word, With error CGMS-A, Even Field, 1st word, With error CGMS-A, Even Field, 2nd word, With error CGMS-A, Even Field, 3rd word, With error WSS, Odd Field, 1st word, No error WSS, Odd Field, 2nd word, No error WSS, Even Field, 1st word, No error WSS, Even Field, 2nd word, No error WSS, Odd Field, 1st word, With error WSS, Odd Field, 2nd word, With error WSS, Even Field, 1st word, With error WSS, Even Field, 2nd word, With error 7 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * 5 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 VBINF_ 432 00 10 01 11 00 10 01 11 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 7 6 VBRD_ 5432 Character 1 Character 2 Character 1 Character 2 Character 1 Character 2 Character 1 Character 2 Word2 CRC 1 0 Word1 Word0 Word1 Word2 CRC Word1 Word2 CRC Word1 Word2 CRC Group2 Group4 Group2 Group4 Group2 Group4 Group2 Group4 Word0 Word0 Word0 Group1 Group3 Group1 Group3 Group1 Group3 Group1 Group3 DCCD_ 0x09 Name Detected Copy Control Data Address D7 D6 0x09 CSTYP CSDET D5 AGCP D4 PSDET D3 rsv D2 rsv R/W Read D1 DCCD 1 D0 DCCD 0 Note For details of copy control data, please refer to Macrovision. Identification Bit Width DCCD_DCCD 2 Description Indicates copy control data Value Operation or Status 0 Copy control data=0 Expression Binary Default - 94 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 1 2 3 Note Copy control data=1 Copy control data=2 Copy control data=3 Identification Bit Width Expression DCCD_PSDET 1 Binary Description Individual indication of copy control data Value Operation or Status 0 Without any copy control data event 1 With certain copy control data events Note Default - Identification Bit Width Expression DCCD_AGCP 1 Binary Description Individual indication of copy control data event Value Operation or Status 0 Without any copy control data event 1 With certain copy control data events Note Default - Identification Bit Width Expression DCCD_CSDET 1 Binary Description Individual indication of copy control data event Value Operation or Status 0 Without any copy control data event 1 With certain copy control data events Note Default - Identification Bit Width Expression DCCD_CSTYP 1 Binary Description Individual copy control data event Value Operation or Status 0 Without any copy control data event 1 With certain copy control data events Note Default - FIRQ_ 0x0A Name FIFO Interrupt Request Address D7 D6 R/W Read/Write(reset) D5 D4 D3 D2 D1 D0 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 95 0x0A VBOV VBAF VBAE VBNE DVOV DVAF DVAE DVNE Note This register displays and resets the interrupt requests. To reset any interrupt request in this register, reset it before resetting the MIRQ_ register (Even when there is no need to reset the interrupt request in the MIRQ_ register, it must be effectively reset by writing a data 0x00.) Identification Bit Width Expression Default FIRQ_DVNE 1 Binary Description DV port FIFO non-empty interrupt event. This interrupt event occurs when the status of the DV port FIFO changed from "empty" to "non-empty" (data exists in one or more stage.) Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression Default FIRQ_DVAE 1 Binary Description DV port FIFO almost empty interrupt event. This interrupt event occurs when the status of the DV port FIFO changed from "not almost empty" to "almost-empty" Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. (The criterion on "almost" is specified by the register DVFLV_AEL) Identification Bit Width Expression Default FIRQ_DVAF 1 Binary Description DV port FIFO almost full interrupt event. This interrupt event occurs when the status of the DV port FIFO changed from "not almost full" to "almost full". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. (The criterion on "almost" is specified by the register DVFLV_AFL) Identification Bit Width Expression Default FIRQ_DVOV 1 Binary Description DV port FIFO Overflow interrupt event. This interrupt event occurs when the status of the DV port FIFO changed from "not full" to "full". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. 96 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default FIRQ_VBNE 1 Binary Description VBI FIFO not empty interrupt event. This interrupt event occurs when the status of the VBI FIFO changed from "empty" to "non-empty" (data exists in one or more stage.) Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression Default FIRQ_VBAE 1 Binary Description VBI FIFO almost empty interrupt event. This interrupt event occurs when the status of the VBI FIFO changed from "not almost empty" to "almost empty". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. (The criterion on "almost" is specified by the regisgter VBFLV_AEL.) Identification Bit Width Expression Default FIRQ_VBAF 1 Binary Description VBI FIFO almost full interrupt event. This interrupt event occurs when the status of the VBI FIFO changed from "not almost full" to "almost full". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. (The criterion on "almost" is specified by the register VBFLV_AFL) Identification Bit Width Expression Default FIRQ_VBOV 1 Binary Description VBI FIFO Overflow interrupt event. This interrupt event occurs when the status of the VBI FIFO changed from "not full" to "full". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 97 MIRQ_ 0x0B Name Misc. Interrupt Request Address D7 D6 0x0B DCCD NINT R/W Read/Write(reset) D5 INT D4 NSTD D3 STD D2 NSDET D1 SDET D0 VMCLM Note This register displays and resets the interrupt requests. To reset the interrupt request in this register, reset the interrupt request in the FIRQ_ register first before resetting this register (This rule does not apply if interrupt request in the FIRQ_ register needs not be reset.) Identification Bit Width Expression MIRQ_VMCLM 1 Binary Description Video mode (video system) changed interrupt event. This interrupt event occurs when the video mode changed. Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Default - Identification Bit Width Expression Default MIRQ_SDET 1 Binary Description Sync detection interrupt event. This interrupt event occurs when the status of sync detection changed from "not detected" to "detected". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression Default MIRQ_NSDET 1 Binary Description Out-of-sync interrupt event. This interrupt event occurs when the status of sync detection changed from "detected" to "not detected". Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification MIRQ_STD Description Bit Width 1 Expression Binary Default - 98 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Standard signal detected interrupt event. This interrupt event occurs when the status of standard signal detection changed from "not detected" to "detected" in the input video signal. Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression Default MIRQ_NSTD 1 Binary Description Standard signal not detected interrupt event. This interrupt event occurs when the status of standard signal detection changed from "detected" to "not detected" in the input video signal. Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression Default MIRQ_INT 1 Binary Description Non-interlaced scan not detected interrupt event. This interrupt event occurs when the status of non-interlaced signal changed from "detected" to "not detected" in the input video signal. Value Operation or Status 0 The event has not occurred. 1 The event has occurred. Note Writing "1" into this bit will reset the interrupt request. Identification Bit Width Expression MIRQ_NINT 1 Binary Description Interrupt event due change in copy control data. An interrupt caused by the change in copy control data. Value Operation or Status 0 Such interrupt event not taking place. 1 Such interrupt event took place. Note Writing "1" into this bit will reset the interrupt event. Identification Bit Width Expression MIRQ_DCCD 1 Binary Description Copy control data changed interrupt event This is the Interrupt taken place when copy control data has changed. Value Operation or Status 0 Such interrupt event not taking place. 1 Such interrupt event took place. Note Writing "1" into this bit will reset the interrupt event. Default - Default - Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 99 GPIOD_ 0x0C - 0x0D Name General Purpose IO Read Write Data Address D7 D6 D5 GPIOD GPIOD GPIOD 0x0C 7 6 5 0x0D rsv rsv rsv R/W Write/Read D1 D0 GPIOD GPIOD 1 0 GPIOD GPIOD 9 8 D4 GPIOD 4 rsv D3 GPIOD 3 rsv D2 GPIOD 2 rsv Identification Bit Width Expression Default GPIOD_GPIOD 10 Binary 0x000 Description This register is accessed when GPIO is set to register IO mode. The register GPDIR_GPDIR specifies Read/Write direction for each bit. Data written into the bits specified as Read are ignored. Data read from the bits specified as Write will be the read-back data previously written in. In addition, when the register GPDIR_SIN is "1", read the GPIO's lower 8 bits first before reading the lower 2 bits. Similarly, when the register GPDIR_SOUT is "1", write the GPIO's lower 8 bits first before writing the lower 2 bits. Bit Operation or Status 0 Read or write to GPIO0 pin. 1 Read or write to GPIO1 pin. 2 Read or write to GPIO2 pin. 3 Read or write to GPIO3 pin. 4 Read or write to GPIO4 pin. 5 Read or write to GPIO5 pin. 6 Read or write to GPIO6 pin. 7 Read or write to GPIO7 pin. 8 Read or write to GPIO8 pin. 9 Read or write to GPIO9 pin. Note The register IO mode settings should be as follows: For the lower 8 bits of the GPIO pins: GPMD_GPSOL='0' For the upper 2 bits of the GPIO pins: GPMD_GPSOH='0' 100 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 5.2.2. Picture Tuning CONT_ 0x10 Name Contrast Trimmer Address D7 CONT 0x10 7 R/W Write/Read D1 D0 CONT CONT 1 0 D6 CONT 6 D5 CONT 5 D4 CONT 4 D3 CONT 3 D2 CONT 2 Identification Bit Width Expression Default CONT_CONT 8 2's complement 0x00 Description This register is used to adjust contrast. Value Operation or Status -128 to +127 Enter a larger number for stronger contrast, and a smaller number for weaker contrast, with zero (0) at its center. Note BRTT_ 0x11 Name Brightness Trimmer Address D7 BRTT 0x11 6 R/W Write/Read D1 D0 BRTT rsv 0 D6 BRTT 5 D5 BRTT 4 D4 BRTT 3 D3 BRTT 2 D2 BRTT 1 Identification Bit Width Expression Default BRTT_BRTT 7 2's complement 0x00 Description This register is used to adjust brightness. Value Operation or Status -64 to +63 Enter a larger number for stronger brightness, and a smaller number for weaker brightness, with zero (0) at its center. Note APCOR_ 0x12 Name Aperture Correction Address D7 CORG 0x12 1 Identification Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC D6 CORG 0 D5 rsv D4 WEIT 2 D3 WEIT 1 Expression D2 WEIT 0 R/W Write/Read D1 D0 APBW APBW 1 0 Default Bit Width Advanced Information 101 APCOR_APBW 2 Binary 0x0 Description This register is used to choose the frequency response of aperture correction. As for the frequency characteristics, please refer to Figure 4.19. Value Operation or Status 0 Reserved 1 Refer to the frequency characteristics 2 Refer to the frequency characteristics 3 Refer to the frequency characteristics Note Identification Bit Width Expression Default APCOR_WEIT 3 Binary 0x0 Description This register is used to choose the strength (weight) of enhancement. Value Operation or Status 0 to 7 The larger the setting, the stronger the aperture correction. Note Identification Bit Width Expression Default APCOR_CORG 2 Binary 0x0 Description This register chooses the way the coring works in order to suppress the noisiness caused by aperture correction. For the coring characteristics, please refer to the Figure 4.20. Value Operation or Status 0 Coring is OFF 1 4-bit 2 5-bit 3 6-bit Note Figure 4.20 shows the coring characteristics on the correction components. CLMK_ 0x13 - 0x15 Name Color Level Trimmer Address D7 0x13 0x14 0x15 CHRMK 7 COLUM 7 COLVM 7 D6 CHRMK 6 COLUM 6 COLVM 6 D5 CHRMK 5 COLUM 5 COLVM 5 D4 CHRMK 4 COLUM 4 COLVM 4 D3 CHRMK 3 COLUM 3 COLVM 3 D2 CHRMK 2 COLUM 2 COLVM 2 R/W Write/Read D1 D0 CHRMK 1 COLUM 1 COLVM 1 CHRMK 0 COLUM 0 COLVM 0 Identification Bit Width Expression Default CLMK_CHRMK 8 2's complement 0x00 Description This register is used to adjust the gain of the chroma components in video signal. For the input other than component or SECAM signal, the color density is adjustable, however, use of CLMK_COLUM and CLMK_COLVM is recommended. Value Operation or Status 102 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet -128 to 127 The larger the setting, the stronger the gain, the smaller the setting the weaker the gain, with zero (0) as its center. Note This register should be set to zero (0) when decoding SECAM. When applying component signal, this register becomes disabled. Identification Bit Width Expression Default CLMK_COLUM 8 2's complement 0x00 Description This register is used to adjust U gain after chroma decoding. This register can be used for color density adjustment together with the register CLMK_COLVM. Value Operation or Status -128 to 127 The larger the setting, the stronger the gain, the smaller the setting the weaker the gain, with zero (0) as its center. Note When component signal being applied, the gain center is 64. Identification Bit Width Expression Default CLMK_COLVM 8 2's complement 0x00 Description This register adjusts V gain after chroma decoding. This register can be used for color density adjustment together with the register CLMK_COLUM. Value Operation or Status -128 to 127 The larger the setting, the stronger the gain, the smaller the setting the weaker the gain, with zero (0) as its center. Note When component signal being applied, the gain center is 64. HUET_ 0x16 - 0x17 Name Hue Trimmer Address 0x16 0x17 R/W Write/Read D1 D0 UVOF UVOF 1 0 HUET HUET 3 2 D7 HUET 1 HUET 9 D6 HUET 0 HUET 8 D5 rsv HUET 7 D4 UVOF 4 HUET 6 D3 UVOF 3 HUET 5 D2 UVOF 2 HUET 4 Identification Bit Width Expression Default HUET_UVOF 5 Binary 0x00 Description This register is used to give offset to the phase variance between UV decoding axes (standard 90 degree.) Offset between zero (0) and approx. 31 degree can be specified. Value Operation or Status 0 to 31 Offset amount = HUET_UVOF* approx. 1 degree Note Identification HUET_HUET Description Bit Width 10 Expression 2's complement Default 0x000 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 103 This register gives offset to the color sub-carrier phase and the decoding axes. Hue trimming can be applied between -180 degree and +179.6 degree, with zero (0) at its center. Value Operation or Status -512 to 511 Amount of hue trimming * HUET_HUET*360/1024 degree Note The hue trimming is furnished for use when decoding the video signals of NTSC color modulation (color_mode=0.) Usually, hue trimming is impossible for color modulation based on PAL or SECAM in principle; however, the XV750C can emulate hue trimming when using PAL color modulation (color_mode=1.) In case of SECAM, any value in this register will be neglected. TRPFCHR_ 0x18 Name TRAP Filter Characteristics Address D7 D6 0x18 rsv rsv R/W Write/Read D1 D0 CHRS CHRS 1 0 D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default TRPFCHR_CHRS 2 Binary 0x2 Description This register selects the frequency characteristics of the trap filter used for Y/C separation. Refer to Figure 4.13, Figure 4.14 and Figure 4.15 for the frequency characteristics. Value Operation or Status 0 Refer to the frequency characteristics 1 Refer to the frequency characteristics 2 Refer to the frequency characteristics 3 Refer to the frequency characteristics Note BPFCHR_ 0x19 Name Band Pass Filter Characteristics Address D7 D6 0x19 rsv rsv R/W Write/Read D1 D0 CHRS CHRS 1 0 D5 rsv D4 rsv D3 rsv D2 CHRS 2 Identification Bit Width Expression Default BPFCHR_CHRS 3 Binary 0x0 Description This register chooses the frequency characteristics of the band-pass filter used for Y/C separation. Refer to Figure4.11 and Figure 4.12 for the frequency characteristics. Value Operation or Status 0 Refer to the frequency characteristics 1 Refer to the frequency characteristics 104 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 2 3 4 5 6 7 Note Refer to the frequency characteristics Refer to the frequency characteristics Refer to the frequency characteristics Refer to the frequency characteristics Refer to the frequency characteristics Refer to the frequency characteristics BELCHR_ 0x1A Name BELL Filter Characteristics Address D7 D6 0x1A rsv rsv R/W Write/Read D1 D0 SIFT SIFT 1 0 D5 SHAP 1 D4 SHAP 0 D3 rsv D2 rsv Identification Bit Width Expression Default BELCHR_SIFT 2 Binary 0x0 Description This register chooses the frequency characteristics (shift) of the bell filter used in SECAM decoding circuit. Value Operation or Status 0 Recommended characteristic 1 Reserved 2 Reserved 3 Reserved Note Please use at the default value. Identification Bit Width Expression Default BELCHR_SHAP 2 Binary 0x0 Description This register is used to choose the frequency characteristics (shape) of the bell filter used in SECAM decoding circuit. Value Operation or Status 0 Recommended characteristic 1 Reserved 2 Reserved 3 Reserved Note Please use at the default value. DEMPCHR_ 0x1B Name De-Emphasis Filter Characteristics Address D7 D6 D5 0x1B rsv rsv rsv R/W Write/Read D1 D0 CHRS CHRS 1 0 D4 rsv D3 rsv D2 rsv Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 105 Identification Bit Width Expression Default DEMPCHR_CHRS 2 Binary 0x0 Description This register chooses the frequency characteristics of the de-emphasis filter used in SECAM decoding circuit. Value Operation or Status 0 Recommended characteristic 1 Reserved 2 Reserved 3 Reserved Note Please use at the default value. PROFLT_ 0x1C - 0x1D Name Programmable Filter Parameter Setting Address D7 D6 D5 ADRS ADRS ADRS 0x1C 7 6 5 DATA DATA DATA 0x1D 7 6 5 R/W Write/Read D1 D0 ADRS ADRS 1 0 DATA DATA 1 0 D4 ADRS 4 DATA 4 D3 ADRS 3 DATA 3 D2 ADRS 2 DATA 2 Identification Bit Width Expression Default PROFLT_ADRS 8 Binary 0x00 Description This register specifies the address of the data register for the programmable filter. Value Operation or Status 0 to 255 Register's address for the programmable filter (See Table 4.6) Note Before writing any data into this register, a register's address of the programmable fileter must be specified to the register PROFLT_DATA. Identification Bit Width Expression Default PROFLT_DATA 8 Binary 0x00 Description This register specifies the data for the register of the programmable filter. Value Operation or Status 0 to 255 Programmable filter data. (Please refer to the Table 4.6) Note Before writing any data into this register, a register's address of the programmable fileter must be specified to the register PROFLT_ADRS. VENHANC_ 0x1E Name Virtical Enhancer Address D7 R/W Write/Read D1 D0 D6 D5 D4 D3 D2 106 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet CORG 1 CORG 0 WEIT 2 WEIT 1 WEIT 0 0x12 rsv rsv ENB Identification Bit Width Expression VENHANC_ENB 1 Binary Description This register selects ON/OFF of the vertical aperture correction. Value Operation or Status 0 nee 1 nm Note Default 0x0 Identification Bit Width Expression Default VENHANC_WEIT 3 Binary 0x0 Description This register specifies the degree (weight) of vertical aperture correction. Value Operation or Status 0 to 7 The larger the set number, the stronger the aperture correction applies. Note Identification Bit Width Expression Default VENHANC_CORG 2 Binary 0x0 Description This register selects the coring function to surpress the noise in aperture correction. As for the coring characteristics, please refer to Figure 4.20. Value Operation or Status 0 Coring OFF 1 4 bits 2 5 bits 3 6 bits Note Figure 4.20 shows the coring characteristics for the correction element. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 107 5.2.3. Configuration AIMS_ 0x20 Name Analog Input MUX Selection Address D7 D6 0x20 rsv rsv R/W Write/Read D1 D0 SELP SELP 1 0 D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default AIMS_SELP 2 Binary 0x0 Description This register selects analog input line. The value corresponds to "m" in "AINnm" that denotes the analog video signal input pins. Value Operation or Status 0 Select AINn0 pin 1 Select AINn1 pin 2 Select AINn2 pin 3 Select AINn3 pin Note ATVM_ 0x21 Name Automatic Video Mode Settings Address D7 D6 D5 VSTD VSTD 0x21 FULL 6 5 R/W Write/Read D1 D0 VSTD VSTD 1 0 D4 VSTD 4 D3 VSTD 3 D2 VSTD 2 Identification Bit Width Expression Default ATVM_VSTD 7 Binary 0x7F Description This register specifies the video standard to be switched automatically according to the video standard (video system) of the input video signal. Automatic switching can be specified independently by setting "1" to the bit that corresponds to the video system. For example, to make only PAL-B, D, G, H, I, N and SECAM automatic, set the register ATVM_VSTD to "0x06". Please refer to "4.17 Video Standard Detection/Automatic Switching Circuit " on page 68 for the detail. Bit Operation or Status 0 NTSC-M, NTSC-Japan 1 PAL-B,D,G,H.I,N 2 SECAM 3 PAL-M 4 PAL-CombinationN 5 NTSC-4.43 6 PAL-60 Note To set the video system manually using the register MNVM_MOD[4:0] , please set the registers ATVM_VSTD=0x00, ATVM_FULL='0'. 108 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default ATVM_FULL 1 Binary 0x0 Description This register specifies automatic switching for all the video standards, instead of setting one by one using the register ATVM_VSTD. Value Operation or Status 0 Register ATVM_VSTD is effective. 1 Fully automatic (registers ATVM_VSTD and MNVM_MOD are ineffective) Note MNVM_ 0x22 Name R/W Manual Video Mode Settings Write/Read Address D7 D6 D5 D4 D3 D2 D1 D0 MOD MOD MOD MOD MOD MOD MOD MOD 0x22 7 6 5 4 3 2 1 0 Note The register MNVM_MOD[4:0] is effective only when the registers are set as follow: ATVM_VSTD=0x00 and ATVM_FULL='0'. When the register MNVM_MOD[4:0] is effective, the VS color killer (refer to "4.16.16 Color Killer Event" on page 68) will not function, regardless of the result of video system judgment. Identification Bit Width Expression MNVM_MOD[0] 1 Binary Description This register specifies the scan mode of the video standard manually. Value Operation or Status 0 59.94Hz/525Line 1 50Hz/625Line Note Default 0x0 Identification Bit Width Expression Default MNVM_MOD[2:1] 2 Binary 0x0 Description This register specifies the color mode (color modulation mode) of the video standard manually. Value Operation or Status 0 NTSC 1 PAL 2 Reserved 3 SECAM Note This register is ineffective when component signal is being input. Identification MNVM_MOD[4:3] Description Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 2 Expression Binary Default 0x0 Advanced Information 109 This register specifies the Fsc mode (color sub-carrier frequency) of the video standard manually. Value Operation or Status 0 3.579545MHz 1 4.4361875MHz 2 3.57561149MHz 3 3.58205625MHz Note This register is ineffective when component signal is being input. Identification Bit Width Expression Default MNVM_MOD[5] 1 Binary 0x0 Description This register specifies the set-up mode (for NTSC-M and NTSC-Japan) of the video standard. NTSC-M: 1 NTSC-Japan: 0 Value Operation or Status 0 None 1 7.5IRE Note This register is effective whenever the decoding video system is NTSC-M or NTSC-Japan, regardless of automatic/manual setting of the video standard. Please note that this register becomes ineffective when component signal being fed. Identification Bit Width Expression Default MNVM_MOD[6] 1 Binary 0x0 Description This register specifies the setup mode (for PAL-B, D, G, H, I, N) of the video standard manually. Normally, set as follows: PAL-B, D, G, H, I: 0 PAL-N: 1 Value Operation or Status 0 None 1 7.5% Note This register is effective whenever the decoding video system is PAL-B, D, G, H, I or PAL-N, regardless of automatic/manual setting of the video standard. Please note that this register becomes ineffective when component signal being fed. Identification Bit Width Expression Default MNVM_MOD[7] 1 Binary 0x1 Description This register specifies the setup mode (for PAL-M) of the video standard manually. Usually, please set the register at the default value. Value Operation or Status 0 None 1 7.5% Note This register is effective when the decoding video system is PAL-M. Please note that this register becomes ineffective when component signal being fed. COMBDEF_ 0x23 - 0x24 110 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Name Comb Filter Definition Address D7 0x23 0x24 rsv P3HT 3 R/W Write/Read D1 D0 BPFS P3LT 1 COMS P3LT 0 D6 rsv P3HT 2 D5 PAFS P3HT 1 D4 PCOMB P3HT 0 D3 rsv P3LT 3 D2 ACMS P3LT 2 Identification Bit Width Expression Default COMBDEF_COMS 1 Binary 0x0 Description This register selects the comb filter operation in the Y/C separation circuit. Usually, please use at the default value. Value Operation or Status 0 Adaptive comb filter 1 Fixed comb filter Note Please refer to the Table 4.5. Identification Bit Width Expression Default COMBDEF_BPFS 1 Binary 0x0 Description This register selects the band-pass filter for comb filter operation in the Y/C separation circuit. Usually, please use at the default value. Value Operation or Status 0 BPF dedicated for comb filter operation 1 BPF for chrominance signals Note Identification Bit Width Expression Default COMBDEF_ACMS 1 Binary 0x1 Description This register chooses a Y/C separation filter to use, when a video signal is input that is judged to have no color burst correlation, when the adaptive comb filter is used in Y/C separation circuit. Value Operation or Status 0 Trap band-pass filter 1 Fixed comb filter Note Identification Bit Width Expression Default COMBDEF_PCOMB 1 Binary 0x1 Description This register is to choose the post-comb filter for PAL. Usually, please use at the default value. Value Operation or Status 0 Not to use 1 Use Note This register becomes effective only for the PAL video signal input. Identification Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width Expression Default Advanced Information 111 COMBDEF_PAFS 1 Binary 0x0 Description This register is to choose the type of adaptive filter for PAL Value Operation or Status 0 Adaptive 5-line comb filter 1 Adaptive 3-line hybrid filter Note This register becomes not effective unless in PAL mode. Please refer to Table 4.5. Identification Bit Width COMBDEF_P3LT 4 Description For PAL 3 lines comb (hybrid) filter image adjustment Value Operation or Status 0 to 0xF Higher trimmer Note Expression Binary Default 0xB Identification Bit Width COMBDEF_P3HT 4 Description PAL 3 lines comb (hybrid) filter image adjustment Value Operation or Status 0 to 0xF Lower trimmer Note Expression Binary Default 0xC AGCDEF_ 0x26 - 0x29 Name Automatic Gain Control Definitions Address D7 D6 D5 0x26 0x27 0x28 0x29 rsv AGMK 7 rsv rsv rsv AGMK 6 rsv rsv LMT AGMK 5 rsv rsv R/W Write/Read D1 D0 MOD MOD 1 0 AGMK AGMK 1 0 AGTC AGTC 1 0 HVSL HVSL 1 0 D4 FRZ AGMK 4 rsv rsv D3 rsv AGMK 3 rsv rsv D2 rsv AGMK 2 AGTC 2 rsv Identification Bit Width Expression Default AGCDEF_MOD 2 Binary 0x2 Description This is the register to set the AGC operation mode. Value Operation or Status 0 Fixed gain (gain value set to the register) 1 Digital AGC operation (Analog gain fixed to the value set to the register) 2 Analog and digital AGC operation (max input level 120%) 3 Analog and digital AGC operation (max input level 200%) Note 112 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default AGCDEF_FRZ 1 Binary 0x0 Description This is the register to freeze the AGC operation. Value Operation or Status 0 AGC is active. 1 AGC is freeze. Note This register is ineffective when the AGC operation is in fixed-gain mode (register AGCDEF_MOD='0') Identification Bit Width Expression Default AGCDEF_LMT 1 Binary 0x1 Description This is the register to apply a limiter to AGC operation. Value Operation or Status 0 Limiter OFF 1 Limiter ON Note This register is ineffective when the AGC operation is in fixed-gain mode (register AGCDEF_MOD='0'.) Identification Bit Width Expression Default AGCDEF_AGMK 8 2's complement 0x00 Description This is the register to set the AGC reference level. Usually, use the default value. Value Operation or Status -128 to +127 The reference level goes down if the value turns to minus, goes up if it turns to plus, based on zero (0) as its center. Note This register is ineffective when the AGC operation is in fixed-gain mode (register AGCDEF_MOD='0') Identification Bit Width Expression Default AGCDEF_AGTC 3 Binary 0x5 Description This is the register to set the AGC time constant. Usually, use the default value. Value Operation or Status 0 to 7 The time constant is maximum at zero (0) and minimum at 7. Note This register is ineffective when the AGC operation is in fixed-gain mode (register AGCDEF_MOD='0') Identification Bit Width Expression Default AGCDEF_HVSL 2 Binary 0x2 Description This register is to set the HV reduction mode for AGC. Value Operation or Status 0 Standard 1 HV reduction mode 2,3 Automatic Note This register is ineffective when the AGC operation is in fixed-gain mode (register AGCDEF_MOD='0') Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 113 PAGCC_ 0x2A - 0x2C Name Peak AGC Control Address 0x2A 0x2B 0x2C R/W Write/Read D1 D0 PAGM PAGM 1 0 SETC SETC 1 0 RETC RETC 1 0 D7 PAGM 7 rsv REOFS 3 D6 PAGM 6 rsv REOFS 2 D5 PAGM 5 rsv REOFS 1 D4 PAGM 4 rsv REOFS 0 D3 PAGM 3 SETM rsv D2 PAGM 2 SETC 2 RETC 2 Identification Bit Width Expression Default PAGCC_PAGM 8 2's complement 0x7F Description This register is to specify the threshold level for the peak AGC. Usually, use the default value. Value Operation or Status -128 to 127 If shifting to negative direction, peak AGC threshold level comes down working for better peak AGC efficiency. Vice versa, if shifting to the positive direction, threshold level going up making peak AGC less effective. Note Identification Bit Width Expression Default PAGCC_SETC 3 Binary 0x4 Description This register specifies set-up time constant for the peak AGC. Usually, please use at the default value. Value Operation or Status 0 to 7 0 for the maximum time constant, 7 for the minimum. Note Identification Bit Width Expression Default PAGCC_SETM 1 Binary 0x0 Description This register specifies set-up time constant mode for the peak AGC. Usually, please use at the default value. Value Operation or Status 0 The register PAGCC_SETC becomes effective as Peak AGC set-up time constant. 1 Irrelevant to the value in the register PAGCC_SETC, this register sets the Peak AGC set-up time constant automatically. Note Identification PAGCC_RETC Description Bit Width 3 Expression Binary Default 0x4 114 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet This register is to specify the release time constant for the peak AGC. Usually, use at the default value. Value Operation or Status 0 to 7 0 for the maximum time constant and 7 for the minimum Note Identification Bit Width Expression Default PAGCC_REOFS 4 2's complement 0x8 Description This register is to specify the release level offset for the peak AGC. Usually, use the default value. Value Operation or Status -8 to +7 The release level is given by the following equation: Release Level = PAGCC_PAGM - 16 + (PAGCC_REOFS*2) Note YGFXA_ 0x2D Name Y Ch. Fixed Gain for Analog Amp. Address D7 D6 D5 0x2D rsv rsv rsv R/W Write/Read D1 D0 FXGA FXGA 1 0 D4 rsv D3 rsv D2 FXGA 2 Identification Bit Width Expression Default YGFXA_FXGA 3 Binary 0x1 Description This register is to set the value of the fixed gain for the Y-channel programmable gain amplifier in the analog front end (VAFE.) Value Operation or Status 0 to 7 Gain = 20log((YGFXA_FXGA + 1) * 0.8) [dB] Note This register is effective only when AGCDEF_MOD='0' or `1'. LGFXD_ 0x2E - 0x2F Name Luminance Fixed Gain for Digital AGC Address D7 D6 D5 FXGD 0x2E rsv rsv 0 FXGD FXGD FXGD 0x2F 8 7 6 R/W Write/Read D1 D0 rsv FXGD 2 Default 0x100 rsv FXGD 1 D4 rsv FXGD 5 D3 rsv FXGD 4 D2 rsv FXGD 3 Identification Bit Width Expression LGFXD_FXGD 9 Binary Description This register sets the digital gain value of the AGC circuit. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 115 Value Operation or Status 0 to 511 Gain = 20log( LGFXD_FXGD/128 ) [dB] Note This register is effective only when the register AGCDEF_MOD='0'. ACCDEF_ 0x30 - 0x32 Name Automatic Chrominance Gain Control Definitions Address D7 D6 D5 D4 0x30 0x31 0x32 rsv ACMK 5 rsv rsv ACMK 4 rsv LMT ACMK 3 rsv FRZ ACMK 2 rsv R/W Write/Read D1 D0 MOD MOD 1 0 rsv AGTC 1 rsv AGTC 0 D3 rsv ACMK 1 rsv D2 rsv ACMK 0 AGTC 2 Identification Bit Width Expression Default ACCDEF_MOD 2 Binary 0x3 Description This register sets the ACC operation mode. Value Operation or Status 0 Fixed gain (gain can be set using a register) 1 Digital ACC operation (Analog gain is fixed: gain can be set using a register) 2 Reserved 3 ACC operation for both analog and digital. Note The digital ACC operation includes the U/V gain control when component signal is input. However, since the U/V gain control depends on the AGC control of the luminance side, the AGC operation mode must be in the digital AGC operation as well. Please refer to "Figure 5.1 ". Identification Bit Width Expression Default ACCDEF_FRZ 1 Binary 0x0 Description This is the register to freeze the ACC operation. Value Operation or Status 0 ACC is active. 1 ACC is freeze. Note This register is ineffective when the ACC operation is in the fixed-gain mode (register ACCDEF_MOD=0.) Identification Bit Width Expression Default ACCDEF_LMT 1 Binary 0x1 Description This is the register to apply a limiter for ACC operation. Value Operation or Status 0 Limiter OFF 1 Limiter ON Note This register is ineffective when the ACC operation is in the fixed-gain mode (register ACCDEF_MOD=0.) 116 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default ACCDEF_ACMK 6 2's complement 0x00 Description This is the register to set the ACC reference level. Usually, use the default value. Value Operation or Status -32 to +31 The reference level goes down if the value turns to minus, goes up if it turns to plus, based on zero (0) as its center. Note This register is ineffective when the ACC operation is in the fixed-gain mode (register ACCDEF_MOD=0.) Identification Bit Width Expression Default ACCDEF_ACTC 3 Binary 0x4 Description This is the register to set the ACC time constant. Usually, use the default value. Value Operation or Status 0 to 7 The time constant is maximum at zero (0) and minimum at 7. Note This register is ineffective when the ACC operation is in the fixed-gain mode (register ACCDEF_MOD=0.) CGFXA_ 0x33 Name C Ch. Fixed Gain for Analog Amp. Address D7 D6 D5 0x33 rsv rsv rsv R/W Write/Read D1 D0 FXGA FXGA 1 0 D4 rsv D3 rsv D2 FXGA 2 Identification Bit Width Expression Default CGFXA_FXGA 3 Binary 0x1 Description This is the register to set the fixed-gain value of the C-channel programmable-gain amp in the analog front end (VAFE.) Value Operation or Status 0 to 7 Gain = 20log((CGFXA_FXGA + 1) * 0.8) [dB] Note Effective when the register AGCDEF_MOD='0' or `1'. Please refer to "Figure 5.1 ". PGFXA_ 0x34 Name P Ch. Fixed Gain for Analog Amp. Address D7 D6 0x34 rsv rsv R/W Write/Read D1 D0 FXGA FXGA 1 0 Default 0x1 D5 rsv D4 rsv D3 rsv D2 FXGA 2 Identification PGFXA_FXGA Description Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 3 Expression Binary Advanced Information 117 This is the register to set the fixed-gain value of the P-channel programmable-gain amp in the analog front end (VAFE.) Value Operation or Status 0 to 7 Gain = 20log((CGFXA_FXGA + 1) * 0.8) [dB] Note Effective when the register AGCDEF_MOD='0' or `1'. Please refer to "Figure 5.1 ". CHGFXD_ 0x35 - 0x36 Name Chrominance Gain Fixed for Digital ACC Address D7 D6 D5 FXGD 0x35 rsv rsv 0 FXGD FXGD FXGD 0x36 8 7 6 R/W Write/Read D1 D0 rsv FXGD 2 rsv FXGD 1 D4 rsv FXGD 5 D3 rsv FXGD 4 D2 rsv FXGD 3 Identification Bit Width Expression Default CHGFXD_FXGD 9 Binary 0x100 Description This is the register to set the value of the chrominance fixed-gain in the digital ACC circuit. Value Operation or Status 0 to 511 Gain = 20log( CHGFXD_FXGD/64 )[dB] Note Effective when the register ACCDEF_MOD='0'. UVGFXD_ 0x37 - 0x38 Name U/V Gain Fixed for Digital ACC Address D7 D6 FXGD 0x37 rsv 0 FXGD FXGD 0x38 8 7 R/W Write/Read D1 D0 rsv FXGD 2 rsv FXGD 1 D5 rsv FXGD 6 D4 rsv FXGD 5 D3 rsv FXGD 4 D2 rsv FXGD 3 Identification Bit Width Expression Default UVGFXD_FXGD 9 Binary 0x100 Description This is the register to set the value of the U/V fixed-gain in digital ACC circuit. Value Operation or Status 0 to 511 Gain = 20log( UVGFXD_FXGD/512 )[dB] Note Effective only when the register ACCDEF_MOD='0' and component signal is fed 118 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 3 Register YGFXA_FXGA 0,1 Analog Gain (Ych) 3 Register CGFXA_FXGA 0,1 Analog Gain (Cch) 3 1 1,3 AGC Loop Filter 0 Latch Splitter Register PGFXA_FXGA 0,1 Analog Gain (Pch) Auto Controled Analog Gain Digital Gain (Luminance) Register LGFXD_FXGD 0 Register AGCDEF_FRZ AGCDEF_MOD Register AGCDEF_MOD 1 1,3 2,3 Register UVGFXD_FXGD 0 0 default 0,1 Latch Digital Gain (U/V) Register AINDEF_SEL 1 Latch Auto Controled Digital Gain 1,3 Register CHGFXD_FXGD 0 Digital Gain (Chrominance) Register AIMS_SELP ACC Loop Filter 0 Register ACCDEF_FRZ Register ACCDEF_MOD Figure 5.1 Functional diagram for gain control Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 119 SBMSK_ 0x39 Name SV Port Blanking Mask Settings Address D7 D6 0x39 rsv rsv R/W Write/Read D1 D0 YMSV YMSH D5 rsv D4 rsv D3 CMSV D2 CMSH Identification Bit Width Expression Default SBMSK_YMSH 1 Binary 0x1 Description This is the register to mask the luminance data output during the horizontal blanking-interval in the SV Line. The mask values are as follows: 0x10 ( on 8bit-output) 0x040(on 10bit-output) Value Operation or Status 0 Do not mask 1 Mask Note Identification Bit Width Expression Default SBMSK_YMSV 1 Binary 0x1 Description This is the register to mask the luminance data output during the vertical blanking-interval in the SV Line. The mask values are as follows: 0x10 (on 8bit-output) 0x040(on 10bit-output) Value Operation or Status 0 Do not mask 1 Mask Note Identification Bit Width Expression Default SBMSK_CMSH 1 Binary 0x1 Description This is the register to mask the chrominance data output during the horizontal blanking-interval in the SV Line. The mask values are as follows: 0x80 (on 8bit-output) 0x200(on 10bit-output) Value Operation or Status 0 Do not mask 1 Mask Note Identification Bit Width Expression Default SBMSK_CMSV 1 Binary 0x1 Description This is the register to mask the chrominance data output during the vertical blanking-interval in the SV Line. The mask values are as follows: 0x80 (on 8bit-output) 0x200(on 10bit-output) Value Operation or Status 120 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 1 Note Do not mask Mask VBISLC_ 0x3A Name VBI Slice Level Control Address D7 0x3A MOD R/W Write/Read D1 D0 LEV LEV 1 0 Default 0x20 D6 LEV 6 D5 LEV 5 D4 LEV 4 D3 LEV 3 D2 LEV 2 Identification Bit Width Expression VBISLC_LEV 7 Binary Description This register sets the slice level at the VBI slice level manual mode. Bit Operation or Status 0 to 127 Slice Level = VBISLC_LEV * 200/219 IRE (Pedestal Level = 0 IRE) Note Identification Bit Width Expression VBISLC_LEV 1 Binary Description This register sets the control mode of the VBI slice level. Value Operation or Status 0 Automatic mode 1 Manual mode Note Default 0x0 PJCSW_ 0x3B Name Pixel Jitter Canceller Switch Address D7 D6 0x3B rsv rsv R/W Write/Read D1 D0 CPJC YPJC D5 rsv D4 rsv D3 rsv D2 AUTO Identification Bit Width Expression Default PJCSW_YPJC 1 Binary 0x1 Description This register turns on or off the PJC(Pixel Jitter Canceller) on luminance side. Value Operation or Status 0 Off 1 On Note Ineffective when the register PJCSW_AUTO='1'. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 121 Identification Bit Width Expression Default PJCSW_CPJC 1 Binary 0x1 Description This is the register to turn on/off the Pixel Jitter Canceller (PJC) on chrominance side. Value Operation or Status 0 Off 1 On Note Ineffective when the register PJCSW_AUTO='1'. Identification Bit Width Expression Default PJCSW_AUTO 1 Binary 0x1 Description This register sets either manual or automatic control of the PJC(Pixel Jitter Canceller) on/off control. Value Operation or Status 0 Manual PJC mode 1 Automatic PJC mode Note In the automatic PJC mode, the next conditions will decide either PJC works or not. *Ein case phase locked in VCXO operation*F PJC off *EIn case not pahse locked in VCXO operation*F PJC on *EIn the free-running mode: PJC on TBCDEF_ 0x3C Name TBC Definitions Address 0x3C R/W Write/Read D1 D0 MOD ENB D7 RLS 3 D6 RLS 2 D5 RLS 1 D4 RLS 0 D3 RLE 1 D2 RLE 0 Identification Bit Width Expression TBCDEF_ENB 1 Binary Description Register to specify Line TBC(Time Base Corrector) on/off Value Operation or Status 0 Off 1 On Note Default 0x1 Identification Bit Width Expression TBCDEF_MOD 1 Binary Description Register to set the Line TBC(Time Base Corrector) mode Value Operation or Status 0 Mode 0 1 Mode 1 Note For each mode's explanation, please refer to "4.8 TBC" on page 27. Default 0x1 122 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default TBCDEF_RLE 2 Binary 0x0 Description Register to specify the resetting line (on the ending side of the field) of Line TBC (Time Base Corrector). Value Operation or Status 0 to 3 From +0 to +3 lines of the standard line Note Identification Bit Width Expression Default TBCDEF_RLS 4 2's complement 0x0 Description Register to specify the resetting line (at the starting side of the field) of the Line TBC (Time Base Corrector). Value Operation or Status -8 to +7 From -8 to +7 lines of the standard line Note VCXODEF_ 0x3D Name VCXO Definitions Address D7 0x3D rsv R/W Write/Read D1 D0 MOD MOD 1 0 D6 rsv D5 rsv D4 HCTLE D3 rsv D2 rsv Identification Bit Width Expression Default VCXODEF_MOD 2 Binary 0x0 Description This register to specify the clock mode (free-running/VCXO) and VCXO modes. For details, please refer to "4.1.3 VCXO Control" on page 7. Value Operation or Status 0 Free-running 1 Burst-locked VCXO 2 Line-licked VCXO 3 Automatic selection VCXO Note Identification Bit Width Expression Default VCXODEF_HCTLE 1 Binary 0x1 Description This is the register to turn the feature on/off to locate the horizontal sync sampling at an appropriate position automatically in the burst-locked VCXO mode. Usually, use this feature turned on. Value Operation or Status 0 Off 1 On Note Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 123 BBDEF_ 0x3E Name Blue-back Definitions Address D7 0x3E rsv R/W Write/Read D1 D0 MOD MOD 1 0 D6 rsv D5 rsv D4 rsv D3 rsv D2 MOD 2 Identification Bit Width Expression Default BBDEF_MOD 2 Binary 0x1 Description This register selects the blue-back self-running sync mode of the XV750C. As for the blue-back self-running sync, please refer to "4.14.1 Self-running Sync" on page 48. As to the modes described in "Operation or Status" below, please refer to Table 5.3. Value Operation or Status 0 Blue-back self-running sync off 1 Blue-back self-running sync mode 0 2 Blue-back self-running sync mode 1 3 Forced Blue-back self-running sync 4 to 6 Not to be used since those are not yet specified 7 Forced self-running sync without blue-back output Note Set blue-back self-running sync OFF, the video input goes through at the same sync output with blue-back self-running sync mode `0'. With the forced self-running sync (without blue-back output) ON, the video input goes through at the same sync output with forced blue-back self-running sync. 124 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Table 5.3 Blue-back self-running mode Sync from input video signal undetectable Sync from input video signal detectable Manual Different input v frequency than set to MNVM_MOD *~ *~ *1 *1 *1 *1 (Note 1) Same input v frequency with set to MNVM_MOD * * * *1 * *1 Other than manual - Self-running mode BBDEF_MOD[2:0] Manual (Note 1) - Other than manual - Self-running mode 0 (without blue-back) Self-running mode 0 (with blue-back) Self-running mode 1 (with blue-back) Forced self-running (with blue-back) Automatic mode 1 (without blue-back) Forced self-running (without blue-back) 0,4,5 1 2 3 6 7 * 1 * 1 * 1 * 1 * 1 * 1 * * * * * * 2 2 2 2 2 2 * * * * 3 * * 3 Note1:Manual here means the following settings in the video standard automatic switching registers.0x21: ATVM_FUL=0 and ATVM_VSTD[6:0]=0 Legend * 1 Sync Self-running sync output in the scan mode frequency set in 0x22:MNVN_MOD Video image Video through * 2 * 3 x * * 1 * 2 * 3 Self-running sync output in the scan mode frequency detected proximately Video through (60Hz immediately after resetting) Video through Self-running sync output in the scan mode frequency currently detected Video through Sync output pulling into the scan mode frequency set in 0x22: MNVN_MOD (Note 2) Video through Sync output locked into the input video signal sync blue-back output Self-running sync output in the scan mode frequency set in 0x22:MNVN_MOD Self-running sync output in the scan mode frequency detected proximately blue-back output (60Hz immediately after resetting) blue-back output Self-running sync output in the scan mode frequency currently detected Note2:Sync output in this case, shall be given in imperfect frequency because input sync signal might not be pulled in fully. VBIDEF_ 0x3F Name VBI Definitions Address D7 0x3F rsv R/W Write/Read D1 D0 SVPTE DVPTE D6 rsv D5 rsv D4 rsv D3 rsv D2 rsv Identification VBIDEF_DVPTE Description Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 1 Expression Binary Default 0x0 Advanced Information 125 This is the DV Line. Value 0 1 Note register to turn the VBI Pass-through data output feature on/off in the Operation or Status Off On Identification Bit Width Expression Default VBIDEF_SVPTE 1 Binary 0x0 Description This is the register to turn the VBI Pass-through data output feature on/off in the SV Line. Value Operation or Status 0 Off 1 On Note VBPLS0_ 0x40 - 0x41 Name VBI Path-through Line Selection #0 Address D7 D6 VBPSL 0x40 FIDSL 6 VBPEL 0x41 FIDEL 6 R/W Write/Read D1 D0 VBPSL VBPSL 1 0 VBPEL VBPEL 1 0 D5 VBPSL 5 VBPEL 5 D4 VBPSL 4 VBPEL 4 D3 VBPSL 3 VBPEL 3 D2 VBPSL 2 VBPEL 2 Identification Bit Width Expression Default VBPLS0_VBPSL 7 Binary 0x11 Description This represents the register #0 that indicates the starting line of VBI Pass-through. It indicates the relative line number in the field designated by the register VBPLS0_FIDSL. Table 5.4 shows the correspondence with the absolute line numbers. Value Operation or Status 0 to 127 Relative starting-line number Note Identification Bit Width Expression Default VBPLS0_FIDSL 1 Binary 0x0 Description This register specifies the field ID for the VBI Pass-through starting-line number designated by the register VBPLS0_VBPSL. Value Operation or Status 0 Field 0 (odd field) 1 Field 1 (even field) Note Identification VBPLS0_VBPEL Description Bit Width 7 Expression Binary Default 0x11 126 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet This represents the register #0 that indicates the ending line of VBI Pass-through. It indicates the relative line number in the field designated by VBPLS0_ FIDEL. Table 5.4 shows the correspondence with the absolute line numbers. Value Operation or Status 0 to 127 Relative starting-line number Note Identification Bit Width Expression Default VBPLS0_FIDEL 1 Binary 0x0 Description This register specifies the field ID of the VBI Pass-through ending-line number designated by the register VBPLS0_VBPEL. Value Operation or Status 0 Field 0 (odd field) 1 Field 1 (even field) Note VBPLS1_ 0x42 - 0x43 Name VBI Path-through Line Selection #1 Address D7 D6 VBPSL 0x42 FIDSL 6 VBPEL 0x43 FIDEL 6 R/W Write/Read D1 D0 VBPSL VBPSL 1 0 VBPEL VBPEL 1 0 Default 0x11 Pass-through. It VBPLS0_FIDSL. D5 VBPSL 5 VBPEL 5 D4 VBPSL 4 VBPEL 4 D3 VBPSL 3 VBPEL 3 D2 VBPSL 2 VBPEL 2 Identification Bit Width Expression VBPLS1_VBPSL 7 Binary Description This represents the register #1 that specifies the starting line of VBI indicates the relative line number in the field designated by the register Table 5.4 shows the correspondence with the absolute line numbers. Value Operation or Status 0 to 127 Relative starting-line number Note Identification Bit Width Expression Default VBPLS1_FIDSL 1 Binary 0x1 Description This register specifies the field ID of the VBI Pass-through starting-line number designated by the register VBPLS1_VBPSL. Value Operation or Status 0 Field 0 (odd field) 1 Field 1 (even field) Note Identification VBPLS1_VBPEL Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 7 Expression Binary Default 0x11 Advanced Information 127 Description This represents the register #1 that specifies the ending line of VBI Pass-through. It indicates the relative line number in the field designated by the register VBPLS0_ FIDEL. Table 5.4 shows the correspondence with the absolute line numbers. Value Operation or Status 0 to 127 Relative starting-line number Note Identification Bit Width Expression Default VBPLS1_FIDEL 1 Binary 0x1 Description This register specifies the field ID of the VBI Pass-through ending-line number designated by the register VBPLS1_VBPEL. Value Operation or Status 0 Field 0 (even field) 1 Field 1 (even field) Note Table 5.4 VBI Pass-through line number correspondence Register's Name VBPLS0_VBPSL (VBPLS0_FIDSL="0") VBPLS0_VBPEL (VBPLS0_FIDEL="0") VBPLS1_VBPSL (VBPLS1_FIDSL="0") VBPLS1_VBPEL (VBPLS1_FIDEL="0") VBPLS0_VBPSL (VBPLS0_FIDSL="1") VBPLS0_VBPEL (VBPLS0_FIDEL="1") VBPLS1_VBPSL (VBPLS1_FIDSL="1") VBPLS1_VBPEL (VBPLS1_FIDEL="1") Register Value 0x00 0x01 0x02 Line Number 4 Line (NTSC) / 1 Line (PAL) 5 Line (NTSC) / 2 Line (PAL) 6 Line (NTSC) / 3 Line (PAL) 0x10 0x11 0x12 20 Line (NTSC) / 17 Line (PAL) 21 Line (NTSC) / 18 Line (PAL) 22 Line (NTSC) / 19 Line (PAL) 0x3E 0x3F 0x00 0x01 0x02 66 Line (NTSC) / 63 Line (PAL) 67 Line (NTSC) / 64 Line (PAL) 267 Line (NTSC) / 314 Line (PAL) 268 Line (NTSC) / 315 Line (PAL) 269 Line (NTSC) / 316 Line (PAL) 0x10 0x11 0x12 283 Line (NTSC) / 330 Line (PAL) 284 Line (NTSC) /331Line (PAL) 285 Line (NTSC) / 332 Line (PAL) 0x3E 0x3F 329 Line (NTSC) / 376 Line (PAL) 330 Line (NTSC) / 377Line (PAL) 128 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet VBELS_ 0x44 - 0x49 Name VBI Extractor Line Settings Address D7 0x44 0x45 0x46 0x47 0x48 0x49 CCELO 3 CCELE 3 CGELO 3 CGELE 3 WSELO 3 WSELE 3 D6 CCELO 2 CCELE 2 CGELO 2 CGELE 2 WSELO 2 WSELE 2 D5 CCELO 1 CCELE 1 CGELO 1 CGELE 1 WSELO 1 WSELE 1 D4 CCELO 0 CCELE 0 CGELO 0 CGELE 0 WSELO 0 WSELE 0 D3 CCSLO 3 CCSLE 3 CGSLO 3 CGSLE 3 WSSLO 3 WSSLE 3 D2 CCSLO 2 CCSLE 2 CGSLO 2 CGSLE 2 WSSLO 2 WSSLE 2 R/W Write/Read D1 D0 CCSLO 1 CCSLE 1 CGSLO 1 CGSLE 1 WSSLO 1 WSSLE 1 CCSLO 0 CCSLE 0 CGSLO 0 CGSLE 0 WSSLO 0 WSSLE 0 Identification Bit Width Expression Default VBELS_CCSLO 4 Binary 0xB Description This register specifies the relative starting-line number for extracting the closed caption data in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Bit Width Expression Default VBELS_CCELO 4 Binary 0xB Description This register specifies the relative ending-line number for extracting the closed caption data in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Identification Bit Width Expression Default VBELS_CCSLE 4 Binary 0xB Description This register specifies the relative starting-line number for extracting the closed caption data in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width Expression Default Advanced Information 129 VBELS_CCELE 4 Binary 0xB Description This register specifies the relative ending-line number for extracting the closed caption data in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Identification Bit Width Expression Default VBELS_CGSLO 4 Binary 0xA Description This register specifies the relative starting-line number for extracting CGMS in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Bit Width Expression Default VBELS_CGELO 4 Binary 0xA Description This register specifies the relative ending-line number for extracting CGMS in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Identification Bit Width Expression Default VBELS_CGSLE 4 Binary 0xA Description This register specifies the relative starting-line number for extracting CGMS in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Bit Width Expression Default VBELS_CGELE 4 Binary 0xA Description This register specifies the relative ending-line number for extracting CGMS in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Identification VBELS_WSSLO Bit Width 4 Expression Binary Default 0xC Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC 130 Advanced Information XV750C Data Sheet Description This register specifies the relative starting-line number for extracting WSS in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Bit Width Expression Default VBELS_WSELO 4 Binary 0xC Description This register specifies the relative ending-line number for extracting WSS in the VBI data extraction (odd field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Identification Bit Width Expression Default VBELS_WSSLE 4 Binary 0xC Description This register specifies the relative starting-line number for extracting WSS in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative starting-line number Note Identification Bit Width Expression Default VBELS_WSELE 4 Binary 0xC Description This register specifies the relative ending-line number for extracting WSS in the VBI data extraction (even field.) Table 5.5 shows the correspondence between the relative and absolute line numbers. Value Operation or Status 0 to 15 Relative ending-line number Note Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 131 Table 5.5 VBI data extraction line number correspondence Register's Name Register Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Line Number 10 Line (NTSC) / 11 Line (PAL) 11 Line (NTSC) / 12 Line (PAL) 12 Line (NTSC) / 13 Line (PAL) 13 Line (NTSC) / 14 Line (PAL) 14 Line (NTSC) / 15 Line (PAL) 15 Line (NTSC) / 16 Line (PAL) 16 Line (NTSC) / 17 Line (PAL) 17 Line (NTSC) / 18 Line (PAL) 18 Line (NTSC) / 19 Line (PAL) 19 Line (NTSC) / 20 Line (PAL) 20 Line (NTSC) / 21 Line (PAL) 21 Line (NTSC) / 22 Line (PAL) 22 Line (NTSC) / 23 Line (PAL) 23 Line (NTSC) / 24 Line (PAL) 24 Line (NTSC) / 25 Line (PAL) 25 Line (NTSC) / 26 Line (PAL) 273 Line (NTSC) / 324 Line (PAL) 274 Line (NTSC) / 325 Line (PAL) 275 Line (NTSC) / 326 Line (PAL) 276 Line (NTSC) / 327 Line (PAL) 277 Line (NTSC) / 328 Line (PAL) 278 Line (NTSC) / 329Line (PAL) 279 Line (NTSC) / 330 Line (PAL) 280 Line (NTSC) / 331Line (PAL) 281 Line (NTSC) / 332 Line (PAL) 282 Line (NTSC) / 333 Line (PAL) 283 Line (NTSC) / 334 Line (PAL) 284 Line (NTSC) / 335 Line (PAL) 285 Line (NTSC) / 336 Line (PAL) 286 Line (NTSC) / 337 Line (PAL) 287 Line (NTSC) / 338 Line (PAL) 288 Line (NTSC) / 339 Line (PAL) VBELS_CCSLO VBELS_CGSLO VBELS_WSSLO VBELS_CCELO VBELS_CGELO VBELS_WSELO (Odd Field) VBELS_CCSLE VBELS_CGSLE VBELS_WSSLE VBELS_CCELE VBELS_CGELE VBELS_WSELE (Even Field) YCDELAY_ 0x4A Name YC Delay Address 0x4A R/W Write/Read D1 D0 ODLY Rsv 0 Default 0x0 D7 ODLC 2 D6 ODLC 1 D5 ODLC 0 D4 rsv D3 ODLY 2 D2 ODLY 1 Identification Bit Width Expression YCDELAY_ODLY 3 2's complement Description This register is to adjust the Y data delay against the sync signal. Value Operation or Status -4 to +3 Delay adjustment (in number of pixels) Note 132 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression YCDELAY_ODLC 3 2's complement Description This register is to adjust the C data delay against the sync signal. Value Operation or Status -4 to +3 Delay adjustment (in number of pixels) Note Default 0x0 HSDELAY_ 0x4B Name HS Delay Address 0x4B R/W Write/Read D1 D0 HST HST 1 0 D7 HST 7 D6 HST 6 D5 HST 5 D4 HST 4 D3 HST 3 D2 HST 2 Identification Bit Width Expression Default HSDELAY_HST 8 2's complement 0x00 Description This register makes it possible to adjust the output timing for the horizontal sync signal SHS. Value Operation or Status -128 to +127 Delay adjustment (in number of pixels) Note VSDELAY_ 0x4C Name VS Delay Address 0x4C R/W Write/Read D1 D0 VST VST 1 0 D7 VST 7 D6 VST 6 D5 VST 5 D4 VST 4 D3 VST 3 D2 VST 2 Identification Bit Width Expression Default VSDELAY_VST 8 2's complement 0x00 Description This register makes it possible to adjust the output timing for the vertical sync signal SVS. Value Operation or Status -128 to +127 Delay adjustment (in number of pixels) Note Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 133 ACTWINS_ 0x4D - 0x50 Name Active Video Window Settings Address D7 D6 WINL WINL 0x4D 3 2 WINR WINR 0x4E 3 2 WINT WINT 0x4F 3 2 WINB WINB 0x50 3 2 R/W Write/Read D1 D0 rsv rsv rsv rsv rsv rsv rsv rsv D5 WINL 1 WINR 1 WINT 1 WINB 1 D4 WINL 0 WINR 0 WINT 0 WINB 0 D3 rsv rsv rsv rsv D2 rsv rsv rsv rsv Identification Bit Width Expression Default ACTWINS_WINL 4 2's complement 0x0 Description This register makes it possible to adjust the window (left side) that represents an effective pixel interval. Value Operation or Status -8 to +7 Adjustment of the effective pixels (in number of 2 pixels) Note Use the default value whenever an output in ITU-R BT.656 format is desirable. Identification Bit Width Expression Default ACTWINS_WINR 4 2's complement 0x0 Description This register makes it possible to adjust the window (right side) that represents an effective pixel interval. Value Operation or Status -8 to +7 Adjustment of the effective pixels (in number of 2 pixels) Note Use the default value whenever an output in ITU-R BT.656 format is desirable. Identification Bit Width Expression Default ACTWINS_WINT 4 2's complement 0x0 Description This register makes it possible to adjust the window (upper side) that represents an effective pixel interval. Value Operation or Status -8 to +7 Adjustment of the effective pixels (in number of pixels) Note Use the default value whenever an output in ITU-R BT.656 format is desirable. Identification Bit Width Expression Default ACTWINS_WINB 4 2's complement 0x0 Description This register makes it possible to adjust the window (lower side) that represents an effective pixel interval. Value Operation or Status -8 to +7 Adjustment of the effective pixels (in number of pixels) Note Use the default value whenever an output in ITU-R BT.656 format is desirable. 134 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet SCROPDEF_ 0x51 Name SV Port Cropping Definitions Address D7 D6 0x51 rsv rsv R/W Write/Read D1 D0 MOD MOD 1 0 D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default SCROPDEF_MOD 2 Binary 0x0 Description This is the register to set the cropping feature for the SV Line. For the details on each mode, refer to "4.11Cropping" on page 41. Value Operation or Status 0 Cropping off 1 Cropping mode 2 Masking mode 3 Reserved Note The cropping mode cannot be used when output is in ITU-R BT.656 format. SCROPH_ 0x52 - 0x55 Name SV Port Cropping H Settings Address D7 D6 0x52 0x53 0x54 0x55 CRPHS 7 CRPHS 6 D5 CRPHS 5 D4 CRPHS 4 D3 CRPHS 3 D2 CRPHS 2 R/W Write/Read D1 D0 CRPHS 1 CRPHS 0 CRPHS 8 CRPHA 0 CRPHA 8 rsv CRPHA 7 rsv CRPHA 6 rsv CRPHA 5 rsv CRPHA 4 rsv CRPHA 3 rsv CRPHA 2 rsv CRPHA 1 rsv rsv rsv rsv rsv rsv rsv Identification Bit Width Expression Default SCROPH_CRPHS 9 Binary 0x012 Description This register specifies the horizontal starting-position of the cropping area for the SV Line. Value Operation or Status 0 to 511 Horizontal starting-position (in number of bi-pixels): 0 to 1022 pixel Note Identification Bit Width Expression Default SCROPH_CRPHA 9 Binary 0x168 Description This register specifies the number of effective horizontal pixels in the cropping area for the SV Line. Value Operation or Status 0 to 511 Number of horizontal effective pixels (in number of bi-pixels): 0 to 1022 pixel Note Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 135 SCROPV_ 0x56 - 0x59 Name SV Port Cropping V Settings Address D7 D6 0x56 0x57 0x58 0x59 CRPVS 7 CRPVS 6 D5 CRPVS 5 D4 CRPVS 4 D3 CRPVS 3 D2 CRPVS 2 R/W Write/Read D1 D0 CRPVS 1 CRPVS 9 CRPVA 1 CRPVA 9 CRPVS 0 CRPVS 8 CRPVA 0 CRPVA 8 rsv CRPVA 7 rsv CRPVA 6 rsv CRPVA 5 rsv CRPVA 4 rsv CRPVA 3 rsv CRPVA 2 rsv rsv rsv rsv rsv rsv Identification Bit Width Expression Default SCROPH_CRPV 10 Binary 0x006 S Description This register specifies the vertical starting-position of the cropping area for the SV Line. Value Operation or Status 0 to Vertical starting-position (in number of lines): 0 to 1023 line 1023 Note Identification Bit Width Expression Default SCROPH_CRPVA 10 Binary 0x1E6 Description This register specifies the number of effective vertical lines in the cropping area for the SV Line. Value Operation or Status 0 to Number of vertical effective lines (in number of lines): 0 to 1023 line 1023 Note DCROPH_ 0x5A - 0x5D Name DV Port Cropping H Settings Address D7 D6 0x5A 0x5B 0x5C 0x5D CRPHS 7 CRPHS 6 D5 CRPHS 5 D4 CRPHS 4 D3 CRPHS 3 D2 CRPHS 2 R/W Write/Read D1 D0 CRPHS 1 CRPHS 0 CRPHS 8 CRPHA 0 CRPHA 8 rsv CRPHA 7 rsv CRPHA 6 rsv CRPHA 5 rsv CRPHA 4 rsv CRPHA 3 rsv CRPHA 2 rsv CRPHA 1 CRPHA 9 rsv rsv rsv rsv rsv rsv Identification Bit Width Expression Default Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC 136 Advanced Information XV750C Data Sheet DCROPH_CRPH 9 Binary 0x012 S Description This register specifies the horizontal starting-position of the cropping area for the DV Line. Value Operation or Status 0 to 511 Horizontal starting-position (in number of bi-pixels): 0 to 1022pixel Note There is certain restriction for setting this register. Refer to "4.10.4 Adjusting the Re-sampling Start Position" on page 38, for details. Identification Bit Width Expression Default DCROPH_CRPH 10 Binary 0x168 A Description This register specifies the number of effective horizontal pixels in the cropping area for the DV Line. Value Operation or Status 0 to Number of horizontal effective pixels (in number of bi-pixels): 0 to 2046 1023 pixel Note There is certain restriction for setting this register. Refer to "4.10.5 Setting the Number of Output Pixels" on page 39, for details. DCROPV_ 0x5E - 0x61 Name DV Port Cropping V Settings Address D7 D6 0x5E 0x5F 0x60 0x61 CRPVS 7 CRPVS 6 D5 CRPVS 5 D4 CRPVS 4 D3 CRPVS 3 D2 CRPVS 2 R/W Write/Read D1 D0 CRPVS 1 CRPVS 0 CRPVS 8 CRPVA 0 CRPVA 8 rsv CRPVA 7 Rsv CRPVA 6 rsv CRPVA 5 rsv CRPVA 4 rsv CRPVA 3 rsv CRPVA 2 rsv CRPVA 1 CRPVA 9 rsv Rsv rsv rsv rsv rsv Identification Bit Width Expression Default DCROPH_CRPV 9 Binary 0x00A S Description This register specifies the vertical starting-position of the cropping area for the DV Line. Value Operation or Status 0 to 511 Vertical starting-position (in number of bi-lines): 0 to 1023 line Note There is certain restriction for setting this register. Refer to "4.10.4 Adjusting the Re-sampling Start Position" on page 38, for details. Identification DCROPH_CRPV A Description Bit Width 10 Expression Binary Default 0x1E0 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 137 This register specifies the number of effective vertical lines in the cropping area for the DV Line. Value Operation or Status 0 to Number of vertical effective lines (in number of lines): 0 to 1023 line 1023 Note There is certain restriction for setting this register. Refer to "4.10.5 Setting the Number of Output Pixels" on page 39, for details. CKILLS_ 0x62 Name Color Killer Settings Address D7 0x62 CKLE R/W Write/Read D1 D0 ALEV ALEV 1 0 D6 MOD D5 Rsv D4 RLEV 1 D3 RLEV 0 D2 ALEV 2 Identification Bit Width Expression Default CKILLS_ALEV 3 Binary 0x1 Description This register is to specify the detection level of the BL color killing. The BL color killing works when the color burst level, theXV750C has detected, is lower than the one set in this register. Value Operation or Status 0 Approximately 2% of normal color burst level 1 Approximately 3% of normal color burst level 2 Approximately 4% of normal color burst level 3 Approximately 6% of normal color burst level 4 Approximately 7% of normal color burst level 5 Approximately 9% of normal color burst level 6 Approximately 11% of normal color burst level 7 Approximately 16% of normal color burst level Note Applicable when input luminance signal level is at the standard level. Identification Bit Width Expression Default CKILLS_RLEV 2 Binary 0x0 Description This register is to specify the non-detection level of the BL color killing. The BL color killing turns off when the color burst level, theXV750C has detected, is higher than the one set in this register. Value Operation or Status 0 CKILLS_ALEV+ Approximately 2% 1 CKILLS_ALEV+ Approximately 3% 2 CKILLS_ALEV+ Approximately 4% 3 CKILLS_ALEV+ Approximately 7% Note Identification Bit Width Expression CKILLS_MOD 1 Binary Description This register is to choose the BL color killing modes. Value Operation or Status Default 0x0 138 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 1 Note Bypass YC separation Output chrominance off Identification Bit Width Expression CKILLS_CKLE 1 Binary Description This register is to turn the BL color killing on and off. Value Operation or Status 0 Off 1 On Note Default 0x1 FHCTLS_ 0x63 - 0x65 Name FH Control Setting Address D7 CODE 0x63 5 0x64 rsv TBCT 0x65 6 R/W Write/Read D1 D0 TBCE rsv TBCT 0 rsv rsv rsv D6 CODE 4 rsv TBCT 5 D5 CODE 3 Rsv TBCT 4 D4 CODE 2 rsv TBCT 3 D3 CODE 1 rsv TBCT 2 D2 CODE 0 rsv TBCT 1 Identification Bit Width Expression Default FHCTLS_TBCE 1 Binary 0x0 Description Register to switch on/off Fh automatic control feature in the line TBC circuit Value Operation or Status 0 Off 1 On Note For Fh control function, please refer to "4.8.3 Fh Control" on page 31. Identification Bit Width Expression Default FHCTLS_CODE 6 Binary 0x0 Description Register to set synchronizing characteristics for various non standard signals Value Operation or Status 0 Standard setting 1 - 63 Not yet defined Note Identification Bit Width Expression Default FHCTLS_TBCT 7 2's complement 0x00 Description Register to adjust Fh manually in the line TBC circuit. Value Operation or Status -64 to +63 Number of pixels in 1H** standard value*{ FHCTLS_TBCT Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 139 Note Only effective when the register FHCTLS_TBCE is off = `0'. HSYNC_ 0x66 Name Hsync Setting Address 0x66 R/W Write/Read D1 D0 rsv TC D7 rsv D6 rsv D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default HSYNC_TC 1 Binary 0x00 Description This register sets the synchronizing characteristics of the XV750C for input signal's horizontal sync. Value Operation or Status 0 Normal 1 High speed Note VSSFT_ 0x67 Name Vsync Shift Setting Address D7 0x67 rsv R/W Write/Read D1 D0 SFTL SFTL 1 0 D6 rsv D5 rsv D4 SFTL 4 D3 SFTL 3 D2 SFTL 2 Identification Bit Width Expression Default VSSFT_SFTL 5 Binary 0x00 Description This register is used to shift the timing to output Vsync (SVS) by the line. Value Operation or Status 0 to 31 Output line** standard line*{ VSSFT_SFTL Note 140 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 5.2.4. Scaler Settings For the details of the register settings, please refer to"4.10 Scaling Engine" on page 35. SCALM_ 0x70 Name Scaler Mode Address 0x70 R/W Write/Read D1 D0 INTI VFLTS Default 0x0 D7 rsv D6 rsv D5 rsv D4 rsv D3 rsv Expression Binary D2 INTO Identification Bit Width SCALM_VFLTS 1 Description This register chooses a vertical filter. Value Operation or Status 0 Linear interpolation filter 1 Low-pass filter Note Identification Bit Width Expression Default SCALM_INTI 1 Binary 0x1 Description This register specifies the scan that is input to the scaling engine. Value Operation or Status 0 Non-interlaced scan 1 Interlaced scan Note Refer to "4.10 Scaling Engine" on page 35, for details. Identification Bit Width Expression Default SCALM_INTO 1 Binary 0x1 Description This register specifies the scan that is output from the scaling engine. Value Operation or Status 0 Non-interlaced scan 1 Interlaced scan Note Refer to "4.10 Scaling Engine" on page 35, for details. HPHS_ 0x71 Name Horizontal Phase Settings Address D7 D6 0x71 rsv rsv R/W Write/Read D1 D0 OFST OFST 1 0 D5 OFST 5 D4 OFST 4 D3 OFST 3 D2 OFST 2 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 141 Identification Bit Width Expression HPHS_OFST 6 Binary Description This is the register to set the amount of horizontal phase offset. Value Operation or Status 0 to 63 Horizontal phase offset = HPHS_OFST/32 pixels Note Refer to "4.10 Scaling Engine" on page 35, for details. Default 0x00 HFILT_ 0x72 Name Horizontal Filter Setting Address D7 0x72 rsv R/W Write/Read D1 D0 FILT FILT 1 0 Default 0x20 D6 rsv D5 FILT 5 D4 FILT 4 D3 FILT 3 D2 FILT 2 Identification Bit Width Expression HFILT_FILT 6 Binary Description This is the register to set the horizontal low-pass filter. Value Operation or Status 2 to 32 Assignable values others Non assignable values Note Refer to "4.10 Scaling Engine" on page 35, for details. HSCAL_ 0x73 - 0x74 Name Horizontal Scale Settings Address D7 SCAL 0x73 7 SCAL 0x74 15 R/W Write/Read D1 D0 SCAL SCAL 1 0 SCAL SCAL 9 8 D6 SCAL 6 SCAL 14 D5 SCAL 5 SCAL 13 D4 SCAL 4 SCAL 12 D3 SCAL 3 SCAL 11 D2 SCAL 2 SCAL 10 Identification Bit Width Expression Default HSCAL_SCAL 16 Binary 0x8000 Description This is the register to set the horizontal scaling factor. Value Operation or Status 0 to 65535 Please refer to "4.10.2 Horizontal Scaling" on page 36. Note There is certain restriction for setting this register. Refer to "4.10 Scaling Engine" on page 35, for details. 142 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet VPHS_ 0x75 Name Vertical Phase Settings Address D7 D6 0x75 rsv rsv R/W Write/Read D1 D0 OFST OFST 1 0 Default 0x00 D5 OFST 5 D4 OFST 4 D3 OFST 3 D2 OFST 2 Identification Bit Width Expression VPHS_OFST 6 Binary Description This is the register to set the amount of vertical phase offset. Value Operation or Status 0 to 63 Vertical phase offset = VPHS_OFST/32 lines Note Please refer to "4.10 Scaling Engine" on page 35, for details. VFILT_ 0x76 Name Vertical Filter Setting Address D7 0x76 rsv R/W Write/Read D1 D0 VFILT VFILT 1 0 Default 0x20 D6 rsv D5 VFILT 5 D4 VFILT 4 D3 VFILT 3 D2 VFILT 2 Identification Bit Width Expression VFILT_VFILT 6 Binary Description This is the register to set the vertical low-pass filter. Value Operation or Status 8 to 32 Assignable value (SCALM_VFLTS=1) 4,8,16,3 Assignable value (SCALM_VFLTS=0) 2 others Non assignable value Note Refer to "4.10 Scaling Engine" on page 35, for details. VSCAL_ 0x77 - 0x78 Name Vertical Scale Settings Address D7 0x77 0x78 VSCAL 7 VSCAL 15 D6 VSCAL 6 VSCAL 14 D5 VSCAL 5 VSCAL 13 D4 VSCAL 4 VSCAL 12 D3 VSCAL 3 VSCAL 11 D2 VSCAL 2 VSCAL 10 R/W Write/Read D1 D0 VSCAL 1 VSCAL 9 VSCAL 0 VSCAL 8 Identification VSCAL_VSCAL Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 16 Expression Binary Default 0x4000 Advanced Information 143 Description This is the register to set the horizontal scaling factor. Value Operation or Status 0 to Please refer to "4.10.1 Vertical Scaling" on page 35. 65535 Note There are restrictions for setting this register. Refer to "4.10 Scaling Engine" on page 35, for details. 144 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 5.2.5. System Configurations LPWCS_ 0x80 - 0x82 Name Low Power Consumption Control Settings Address D7 D6 D5 0x80 rsv rsv rsv 0x81 0x82 rsv AFEC 7 rsv AFEC 6 rsv AFEC 5 R/W Write/Read D1 D0 AUTO PINE OF OF PWM SCE AFEC AFEC 1 0 Default 0x1 D4 rsv rsv AFEC 4 D3 rsv rsv AFEC 3 D2 rsv rsv AFEC 2 Identification Bit Width Expression LPWCS_PINE 1 Binary Description This register sets the PWDN pin valid or invalid. Value Operation or Status 0 PWDN pin is invalid. 1 PWDN pin is valid. Note Identification Bit Width Expression Default LPWCS_AUTO 1 Binary 0x1 Description This register sets the auto-power on/off control for the ADCs in VAFE. When the auto-power control is enabled, the unused ADCs are automatically powered down. Value Operation or Status 0 Auto-power control is off (LPWCS_AFEC[2:0] is effective) 1 Auto-power control is on (LPWCS_AFEC[2:0] is ineffective) Note Identification Bit Width Expression Default LPWCS_OFSCE 1 Binary 0x0 Description This register conserves the power consumed by the memory used in the scaling engine. When the DV Line output is not in use, this value may be set to "1". Value Operation or Status 0 Normal mode 1 Low-power mode Note This register should be "0" whenever the DV Line is used. Identification Bit Width Expression Default LPWCS_OFPWM 1 Binary 0x0 Description This register is used to disable the PWM output for the external VCXO. This register may be "1" when the VCXO pin is not in use. Value Operation or Status 0 Normal mode 1 Low-power mode Note Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 145 This register should be "0" whenever the VCXO pin is in use. Identification Bit Width Expression Default LPWCS_AFEC 8 Binary 0x9F Description This is the register to set the power control for VAFE (video analog front end.) Usually, use the default value. Bit Operation or Status 0 On CH#0 1 On CH#1 2 On CH#2 3 On REF 4 On VCM 5 SWIB 6 BYPASS 7 On CLMPY Note AINDEF_ 0x83 Name Analog Input Definitions Address D7 SEL3 0x83 1 R/W Write/Read D1 D0 SEL0 SEL0 1 0 D6 SEL3 0 D5 SEL2 1 D4 SEL2 0 D3 SEL1 1 D2 SEL1 0 Identification Bit Width Expression Default AINDEF_SELm 2 Binary 0x0 Description This register specifies the video signal applied to the analog input line number "m". Value Operation or Status 0 Composite 1 S-video 2 Component (Video signal vs. sync ratio * 7:3) 3 Component (Video signal vs. sync ratio * 10:4) Note ICHX_ 0x84 Name Input Channel Cross-Over Address D7 0x84 Rsv R/W Write/Read D1 D0 DYCH DYCH 1 0 Default 0x0 D6 rsv D5 DPCH 1 D4 DPCH 0 D3 DCCH 1 Expression Binary D2 DCCH 0 Identification ICHX_DYCH Description Bit Width 2 146 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet This register specifies the analog input channel number connected to the digital Y channel. Value Operation or Status 0 Analog channel #0 1 Analog channel #1 (not in use) 2 Analog channel #2 (not in use) 3 Reserved Note ICHX_DYCH should always be "0". Identification Bit Width Expression Default ICHX_DCCH 2 Binary 0x1 Description This register specifies the analog input channel number connected to the digital C channel. Value Operation or Status 0 Analog channel #0 (not in use) 1 Analog channel #1 2 Analog channel #2 3 Reserved Note Never set zero (0) in ICHX_DCCH. Identification Bit Width Expression Default ICHX_DPCH 2 Binary 0x2 Description This register specifies the analog input channel number connected to the digital P channel. Value Operation or Status 0 Analog channel #0 (not in use) 1 Analog channel #1 2 Analog channel #2 3 Reserved Note Never set zero (0) in ICHX_DPCH. VSMPDEF_ 0x85 Name Video Sampling Definitions Address D7 0x85 rsv R/W Write/Read D1 D0 SMPC DCFB D6 rsv D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default VSMPDEF_DCFB 1 Binary 0x0 Description This register determines whether the decimation filter is used for down sampling the 27MHz clock to 13.5MHz or bypassed. Value Operation or Status 0 Decimation filter is used. 1 Decimation filter is bypassed. Note Usually, please use at the default value. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 147 Identification Bit Width Expression VSMPDEF_SMPC 1 Binary Description This register is used to set the sampling clock frequency. Value Operation or Status 0 27MHz 1 13.5MHz Note Usually, please use at the default value. Default 0x0 ICMPNDEF_ 0x86 Name Input Component Definitions Address D7 D6 0x86 rsv rsv R/W Write/Read D1 D0 LEV LEV 1 0 Default 0x0 D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression ICMPNDEF_LEV 2 Binary Description This register defines the signal category in the component input mode. Value Operation or Status 0 YCbCr 1 rsv 2 rsv 3 rsv Note VPDEF_ 0x88 Name Output Video Port Definitions Address D7 D6 0x88 SVCOE DVCOE R/W Write/Read D1 D0 MOD MOD 1 0 Default 0x0 D5 SVOE D4 DVOE D3 rsv D2 MOD 2 Identification Bit Width Expression VPDEF_MOD 3 Binary Description This register specifies the mode of the video output port. For details, refer to "4.13 Video Output " on page 42. Value Operation or Status 0 SYC, DYC 1 SYC, DY, DC 2 SY, SC 3 DG/DY, DB/DCb, DR/DCr 4 SG/SY, SB/SCb, SR/SCr 148 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Note Identification Bit Width Expression Default VPDEF_DVOE 1 Binary 0x0 Description This register enables or disables the OE(Output Enable) pin for the signal output buffer of the video output port in the DV Line Value Operation or Status 0 OE pin is enabled (Hi-Z when OE="L", driven when OE="H") 1 OE pin is disabled (always driven) Note This register controls the buffers for the pins that give the DV Line output signals rather than the DVO pins. For example, if the register VPDEF_MOD is `3', it also controls the buffers for the SVO pins. Identification Bit Width Expression Default VPDEF_SVOE 1 Binary 0x0 Description This register enables or disables the OE(Output Enable) pin for the signal output buffer of the video output port in the SV Line Value Operation or Status 0 OE pin is enabled (Hi-Z when OE="L", driven when OE="H") 1 OE pin is disabled (always driven) Note This register controls the buffers for the pins that give the SV Line output signals rather than the SVO pins. For example, if the register VPDEF_MOD is `4', it also controls the buffers for the DVO pins. Identification Bit Width Expression Default VPDEF_DVCOE 1 Binary 0x0 Description This register specifies OE (Output Enable) control of DV line timing output buffer of the video output port. Value Operation or Status 0 OE pins effective *i giving output with OE="L", Hi-Z and OE="H"*j 1 OE pins ineffective *i always giving output*j Note This register controls terminal buffer to feed DV line timing signal instead of DVO pins. For instance, if the register VPDEF_MOD is '3' it also controls buffers for the SVO pins. Identification Bit Width Expression Default VPDEF_SVCOE 1 Binary 0x0 Description This register specifies OE (Output Enable) control of SV line timing output buffer of the video output port. Value Operation or Status 0 OE pins effective *i giving output with OE="L", Hi-Z and OE="H"*j 1 OE pins ineffective (always giving output) Note This register controls terminal buffer to feed SV line timing signal instead of SVO pins. For instance, if the register VPDEF_MOD is '4' it also controls buffers for the DVO pins. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 149 SVVDEF_ 0x89 Name SV Port Video Definitions Address D7 D6 0x89 S10B rsv R/W Write/Read D1 D0 SOLV SOLV 1 0 D5 SOLM D4 SRGB 1 D3 SRGB 0 D2 rsv Identification Bit Width Expression Default SVVDEF_SOLV 2 Binary 0x0 Description This register specifies the color space for the data output signal of the SV Line. Value Operation or Status 0 YCbCr 1 Reserved 2 RGB 3 Reserved Note Identification Bit Width Expression Default SVVDEF_SRGB 2 Binary 0x0 Description This register specifies the RGB mode for the data output signal of the SV Line. Value Operation or Status 0 0-255 1 0-255 A -1 correction 2 16-235 3 Reserved Note Only effective when the regiser SVVDEF_SOLV= `2'. Identification Bit Width Expression Default SVVDEF_SOLM 1 Binary 0x0 Description This register specifies the limiter for the data output signal of the SV Line. Value Operation or Status 0 Limiter is off 1 Limiter is on (ITU-R BT.601level) Note Only effective when the register SVVDEF_SOLV= `0'. Identification Bit Width Expression Default SVVDEF_S10B 1 Binary 0x1 Description This register specifies the bit width for the data output signal of the SV Line. Value Operation or Status 0 8-bit 1 10-bit Note This register will be disabled (fixed to 8-bit) when the register VPDEF_MOD= `3' or `4'. 150 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet DVVDEF_ 0x8A Name DV Port Video Definitions Address D7 D6 0x8A OECV rsv R/W Write/Read D1 D0 DOLV DOLV 1 0 D5 DOLM D4 DRGB 1 D3 DRGB 0 D2 rsv Identification Bit Width Expression Default DVVDEF_DOLV 2 Binary 0x0 Description This register specifies the color space for the data output signal of the DV Line. Value Operation or Status 0 YCbCr 1 Reserved 2 RGB 3 Reserved Note Identification Bit Width Expression Default DVVDEF_DRGB 2 Binary 0x0 Description This register specifies the RGB mode for the data output signal of the DV Line. Value Operation or Status 0 0-255 1 0-255 A -1 correction 2 16-235 3 Reserved Note Only effective when the register DVVDEF_DOLV= `2'. Identification Bit Width Expression Default DVVDEF_DOLM 1 Binary 0x0 Description This register specifies the limiter for the data output signal of the DV Line. Value Operation or Status 0 Limiter is off 1 Limiter is on (ITU-R BT.601 level) Note Only effective when the regisiter DVVDEF_DOLV= '0'. Identification Bit Width Expression Default DVVDEF_OECV 1 Binary 0x0 Description This register specifies whether the DVAL signal controls the output buffer for the DV Line's data signal. Value Operation or Status 0 Off (Always output mode) 1 On (Output mode while the DVAL signal is asserted, otherwise Hi-Z) Note Only effective while the buffer is driven by the register VPDEF_DVOE. Otherwise, always Hi-Z. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 151 SVTDEF_ 0x8B Name SV Port Timing Definitions Address D7 D6 0x8B rsv rsv R/W Write/Read D1 D0 HBE R656 D5 rsv D4 rsv D3 rsv D2 VBE Identification Bit Width Expression Default SVTDEF_R656 1 Binary 0x1 Description This register specifies the super positioning of the EAV and SAV codes defined in ITU-R BT.656 on the data output signal of the SV Line. Value Operation or Status 0 Off (no superposition) 1 On (superposition) Note Identification Bit Width Expression Default SVTDEF_HBE 1 Binary 0x0 Description This register specifies the output mode for the control signal output, SHB (horizontal blanking signal) for the SV Line. Value Operation or Status 0 Normal mode 1 Extended mode (The EAV and SAV output intervals are not treated as blanking period.) Note Identification Bit Width Expression Default SVTDEF_VBE 1 Binary 0x0 Description This register specifies the output mode for the control signal output, SVB (vertical blanking signal) for the SV Line. Value Operation or Status 0 Normal mode 1 Extended mode (The VBI Path-through data output line is not treated as a blanking line) Note DVTDEF_ 0x8C Name DV Port Timing Definitions Address D7 D6 0x8C rsv rsv R/W Write/Read D1 D0 rsv R656 D5 rsv D4 rsv D3 rsv D2 rsv 152 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default DVTDEF_R656 1 Binary 0x1 Description This register specifies the super positioning of the EAV and SAV codes defined in ITU-R BT.656 on the data output signal of the DV Line. Value Operation or Status 0 Off (no superposition) 1 On (superposition) Note SVCDEF_ 0x8D Name SV Port Control Signal Definitions Address D7 D6 D5 SFLDS SFLDS 0x8D rsv 2 1 R/W Write/Read D1 D0 SCBFS SCBFS 1 0 D4 SFLDS 0 D3 rsv D2 SCBFS 2 Identification Bit Width Expression Default SVCDEF_SCBFS 3 Binary 0x0 Description This register specifies the signals driven to the control signal-out pins in the SV Line. Value Operation or Status 0 Cb flag (Cb flag signal: Cb="H" / Cr="L") 1 VBI driving interval (VBI driving interval ="H") 2 Logical AND of SHB and SVB 3 Logical AND of SHS and SVS 4 SVS 5 Reversing at every V sync 6 CFR 7 CFS Note The polarity can be reversed by the register SVPOL_SCBF. Identification Bit Width Expression Default SVCDEF_SFLDS 3 Binary 0x0 Description This register specifies the signal to output to the control signal-out pin SFLD for the SV Line. Value Operation or Status 0 Field ID (odd field ="L" / even field ="H") 1 VBI driving interval(VBI driving interval="H") 2 Logical AND of SHB and SVB 3 Logical AND of SHS and SVS 4 SVS 5 Reversing at every V sync 6 CFR 7 CFS Note The polarity can be reversed by the register SVPOL_SFLD. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 153 DVCDEF_ 0x8E Name DV Port Control Signal Definitions Address D7 D6 D5 0x8E rsv DGVP rsv R/W Write/Read D1 D0 DVALG D4 DGHP D3 rsv D2 rsv DCKS Identification Bit Width Expression Default DVCDEF_DCKS 1 Binary 0x1 Description This register specifies the direction of the control signal pin DCK for the DV Line. Value Operation or Status 0 DCK out 1 DCK in Note The polarity can be reversed by the register DVPOL_DCK. Identification Bit Width Expression Default DVCDEF_DVALG 1 Binary 0x0 Description This register specifies the signal to output to the control signal-out pin DVAL for the DV Line. Value Operation or Status 0 Data out effective interval for the DV Line (Data Effective)( Data out effective interval ="H") 1 DCK & Data Effective Note The polarity can be reversed by the register DVPOL_DVAL. Identification Bit Width Expression Default DVCDEF_DGHP 1 Binary 0x0 Description This register specifies the signal to output to the control signal-out pin DGHP (horizontal general-purpose signal) for the DV Line. Value Operation or Status 0 Horizontal data ending flag (DHEND) (active Hi) 1 Horizontal blanking (DHB) (Blanking interval = "L") Note The polarity can be reversed by the register DVPOL_DGHP. Identification Bit Width Expression Default DVCDEF_DGVP 1 Binary 0x0 Description This register specifies the signal to output to the control signal-out pin DGVP (vertical general-purpose signal) for the DV Line. Value Operation or Status 0 Vertical data ending flag (DVEND) (active Hi) 1 Vertical blanking (DVB) (Blanking interval = "L") Note The polarity can be reversed by the register DVPOL_DGVP. 154 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet DVGDEF_ 0x8F - 0x90 Name DV Port General Signal Definitions Address D7 D6 D5 DGP1 DGP1 OECV1 0x8F 2 1 DGP3 DGP3 OECV3 0x90 2 1 R/W Write/Read D1 D0 DGP0 DGP0 1 0 DGP2 DGP2 1 0 D4 DGP1 0 DGP3 0 D3 OECV0 OECV2 D2 DGP0 2 DGP2 2 Identification Bit Width Expression Default DVGDEF_DGP0 3 Binary 0x1 Description This register specifies the signal to output to the general-purpose signal pin DGP0 for the DV Line. Value Operation or Status 0 Horizontal blanking (DHB) (Blanking interval = "L") 1 Field ID (DFLD) (odd field ="L" / even field ="H") 2 Cb flag (DCBF) (Cb flag signal: Cb="H" / Cr="L") 3 VBI driving interval (DVBI) (VBI driving interval="H") 4 DV port FIFO is not empty (DVNE) (active Hi) 5 DV port FIFO is almost empty (DVAE) (active Hi) 6 DV port FIFO is almost full (DVAF) (active Hi) 7 DV port FIFO is full (DVFL) (active Hi) Note The polarity can be reversed by the register DVPOL_DGP0. Identification Bit Width Expression Default DVGDEF_OECV0 1 Binary 0x0 Description This register specifies how the DAVL controls the buffer for the general-purpose signal-out pin DGP0 for the DV Line. Value Operation or Status 0 Off (do not control the buffer * always driven) 1 On (driven while DVAL is active, otherwise Hi-Z) Note Identification Bit Width Expression Default DVGDEF_DGP1 3 Binary 0x2 Description This register specifies the signal to output to the general-purpose signal pin DGP1 for the DV Line. Value Operation or Status 0 Horizontal blanking (DHB) ) (Blanking interval = "L") 1 Field ID(DFLD) (odd field ="L" / even field ="H") 2 Cb flag(DCBF) (Cb flag signal: Cb="H" / Cr="L") 3 ANC driving interval (DANC) (ANC driving interval ="H") 4 DV port FIFO is not empty (DVNE) (active Hi) 5 DV port FIFO is almost empty (DVAE) (active Hi) 6 DV port FIFO is almost full (DVAF) (active Hi) 7 DV port FIFO is full (DVFL) (active Hi) Note The polarity can be reversed by the register DVPOL_DGP1. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 155 Identification Bit Width Expression Default DVGDEF_OECV1 1 Binary 0x0 Description This register specifies how DVAL controls the buffer for the general-purpose signal-out pin DGP1 for the DV Line. Value Operation or Status 0 Off (no buffer control * always driven) 1 On (driven while DVAL is active, otherwise Hi-Z) Note Identification Bit Width Expression Default DVGDEF_DGP2 3 Binary 0x0 Description This register specifies the signal to output to the general-purpose signal pin DGP2 (GPIO[8]) for the DV Line. Value Operation or Status 0 Horizontal blanking (DHB) ) (Blanking interval = "L") 1 Field ID (DFLD) (odd field ="L" / even field ="H") 2 Cb flag (DCBF) (Cb flag signal: Cb="H" / Cr="L") 3 SAV or EAV output period (DSAVEAV) (SAV EAV output period ="H") 4 DV port FIFO is not empty (DVNE) (active Hi) 5 DV port FIFO is almost empty (DVAE) (active Hi) 6 DV port FIFO is almost full (DVAF) (active Hi) 7 DV port FIFO is full (DVFL) (active Hi) Note To output DGP2 on pin GPIO[8], the register GPMD_GPSOH must be in DGP mode. Identification Bit Width Expression Default DVGDEF_OECV2 1 Binary 0x0 Description This register specifies how the DVAL controls the buffer for the general-purpose signal-out pin DGP2 (GPIO[8]) for the DV Line. Value Operation or Status 0 Off (no buffer control * always driven) 1 On (driven while DVAL is active, otherwise Hi-Z) Note Identification Bit Width Expression Default DVGDEF_DGP3 3 Binary 0x0 Description This register specifies the signal to output to the general-purpose signal pin DGP3(GPIO[9]) for the DV Line. Value Operation or Status 0 Horizontal blanking (DHB) ) (Blanking interval = "L") 1 Field ID(DFLD) (odd field ="L" / even field ="H") 2 Cb flag(DCBF) (Cb flag signal: Cb="H" / Cr="L") 3 ANC driving interval (DANC) (ANC driving interval ="H") 4 DV port FIFO is not empty (DVNE) (active Hi) 5 DV port FIFO is almost empty (DVAE) (active Hi) 6 DV port FIFO is almost full (DVAF) (active Hi) 7 DV port FIFO is full (DVFL) (active Hi) Note To output DGP3 on pin GPIO[9], the register GPMD_GPSOH must be in DGP mode. 156 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Identification Bit Width Expression Default DVGDEF_OECV3 1 Binary 0x0 Description This register specifies how DVAL controls the buffer for the general-purpose signal-out pin DGP3 (GPIO[9]) for the DV Line. Value Operation or Status 0 Off (no buffer control * always driven) 1 On (driven while DVAL is active, otherwise Hi-Z) Note SVPOL_ 0x91 Name SV Port Polarities Address D7 0x91 SCK R/W Write/Read D1 D0 SVS SHS D6 rsv D5 SFLD D4 SCBF D3 SVB D2 SHB Identification Bit Width Expression Default SVPOL_SHS 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SHS for the SV Line. Value Operation or Status 0 Normal (Horizontal sync signal: active LOW) 1 Reverse Note Identification Bit Width Expression Default SVPOL_SVS 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SVS for the SV Line. Value Operation or Status 0 Normal (Vertical sync signal: active LOW) 1 Reverse Note Identification Bit Width Expression Default SVPOL_SHB 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SHB for the SV Line. Value Operation or Status 0 Normal (Horizontal blanking signal: active LOW) 1 Reverse Note Identification SVPOL_SVB Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Bit Width 1 Expression Binary Default 0x0 Advanced Information 157 Description This register specifies the polarity of the signal driven to the control signal pin SVB for the SV Line. Value Operation or Status 0 Normal (Vertical blanking signal: active LOW) 1 Reverse Note Identification Bit Width Expression Default SVPOL_SCBF 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SCBF for the SV Line. Value Operation or Status 0 Normal 1 Reverse Note Please refer to the description on the register SVCDEF_SCBFS for the normal polarity of the output signal. Identification Bit Width Expression Default SVPOL_SFLD 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SFLD for the SV Line. Value Operation or Status 0 Normal 1 Reverse Note Please refer to the description on the register SVCDEF_SFLDS for the normal polarity of the output signal. Identification Bit Width Expression Default SVPOL_SCK 1 Binary 0x0 Description This register specifies the polarity of the signal driven to the control signal pin SCK for the SV Line. Value Operation or Status 0 Normal 1 Reverse Note DVPOL_ 0x92 Name DV Port Polarities Address D7 0x92 DCK R/W Write/Read D1 D0 DGVP DGHP D6 rsv D5 DTRDY D4 DVAL D3 DGP1 D2 DGP0 Identification Bit Width Expression Default Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC 158 Advanced Information XV750C Data Sheet DVPOL_DGHP 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DGHP. Value Operation or Status 0 Normal 1 Reverse Note As to the normal polarity of the output signal, please refer to the register DVCDEF_DGHP. Identification Bit Width Expression Default DVPOL_DGVP 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DGVP. Value Operation or Status 0 Normal 1 Reverse Note For the normal polarity of the output signal, please refer to the register DVCDEF_DGVP. Identification Bit Width Expression Default DVPOL_DGP0 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DGP0. Value Operation or Status 0 Normal 1 Reverse Note For the normal polarity of the output signal, please refer to the register DVCDEF_DGP0. Identification Bit Width Expression Default DVPOL_DGP1 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DGP1. Value Operation or Status 0 Normal 1 Reverse Note For the normal polarity of the output signal, please refer to the register DVCDEF_DGP1. Identification Bit Width Expression Default DVPOL_DVAL 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DVAL. Value Operation or Status 0 Normal 1 Reverse Note For the normal polarity of the output signal, please refer to the register DVCDEF_DVALG. Identification Bit Width Expression Default DVPOL_DTRDY 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal pin DTRDY. Value Operation or Status 0 Normal (target ready ="H") Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 159 1 Note Reverse Identification Bit Width Expression Default DVPOL_DCK 1 Binary 0x0 Description This register specifies the polarity of the signal given at the DV control signal IO pin DCK. Value Operation or Status 0 Normal 1 Reverse Note GPMD_ 0x93 Name General Purpose IO Mode Address D7 D6 0x93 GPSSH 1 GPSSH 0 D5 GPSSL 2 D4 GPSSL 1 D3 GPSSL 0 D2 GPSOH 1 R/W Write/Read D1 D0 GPSOH 0 GPSOL Identification Bit Width Expression Default GPMD_GPSOL 1 Binary 0x0 Description This register specifies the operation mode of GPIO[7:0], the lower 8 bits of the GPIO pins. Value Operation or Status 0 Register IO mode 1 Output mode of the internal status register Note Identification Bit Width Expression Default GPMD_GPSOH 2 Binary 0x0 Description This register specifies the operation mode of GPIO[9:8], the upper 2 bits of the GPIO pins. Value Operation or Status 0 Register IO mode 1 Output mode of the internal status register 2 DGP mode 3 CFR/CFS mode Note Identification Bit Width Expression Default GPMD_GPSSL 3 Binary 0x0 Description This register specifies the address of the status register directed to GPIO[7:0], the lower 8 bits of the GPIO pins. Value Operation or Status 0 to 6 Register address = GPMD_GPSSL + 0x02 7 Register address = 0xAB 160 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Note Effective only when GPMD_GPSOL=1 (internal status register out mode.) Identification Bit Width Expression Default GPMD_GPSSH 2 Binary 0x0 Description This register specifies the address of the status register directed to GPIO[9:8], the upper 2 bits of the GPIO pins. Value Operation or Status 0 to 3 Register address = GPMD_GPSSH + 0x02 others Reserved Note Effective only when GPMD_GPSOH=1 (internal status register out mode.) Only the lower 2 bits of the register will be output as the status. GPDIR_ 0x94 - 0x95 Name General Purpose IO pin Direction Settings Address D7 D6 D5 D4 GPDIR GPDIR GPDIR GPDIR 0x94 7 6 5 4 0x95 SOUT SIN rsv rsv R/W Write/Read D1 D0 GPDIR GPDIR 1 0 GPDIR GPDIR 9 8 D3 GPDIR 3 rsv D2 GPDIR 2 rsv Identification Bit Width Expression Default GPDIR_GPDIR 10 Binary 0x000 Description The value of this register determines the input/output direction of the buffer when the GPIO pins are in the register IO mode. The each bit of the register GPDIR_GPDIR[9:0] corresponds to each pin for GPIO[9:0]. Value Operation or Status 0 Input 1 Output Note Identification Bit Width Expression Default GPDIR_SIN 1 Binary 0x0 Description This register is used to approximately synchronize the data input between the upper 2 bits and lower 8 bits, when the GPIO pins are in the register IO mode. Value Operation or Status 0 The input timing for the upper 2-bit is independent from the lower 8-bit. 1 The input timing for the upper 2-bit is synchronized with the lower 8-bit. Note Refer to the description on the register GPIOD_. Identification Bit Width Expression Default GPDIR_SOUT 1 Binary 0x0 Description This register is used to approximately synchronize the data output between the upper 2 bits and lower 8 bits, when the GPIO pins are in the register IO mode. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 161 Value 0 1 Operation or Status The output timing for the upper 2-bit is independent from the lower 8-bit. The output timing for the upper 2-bit is synchronized with the lower 8-bit. Note Refer to the description on the register GPIOD_. FIMSK_ 0x96 Name FIFO Interrupt Mask Address D7 0x96 VBOV R/W Write/Read D1 D0 DVAE DVNE D6 VBAF D5 VBAE D4 VBNE D3 DVOV D2 DVAF Identification Bit Width Expression Default FIMSK_DVNE 1 Binary 0x1 Description This register masks the "DV port FIFO not empty" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_DVNE for the interrupt events. Identification Bit Width Expression Default FIMSK _DVAE 1 Binary 0x1 Description This register masks the "DV port FIFO almost empty" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_DVAE for the interrupt events. Identification Bit Width Expression Default FIMSK _DVAF 1 Binary 0x1 Description This register masks the "DV port FIFO almost full" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_DVAF for the interrupt events. Identification Bit Width Expression FIMSK _DVOV 1 Binary Description This register masks the "DV port FIFO Overflow" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Default 0x1 162 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Note Refer to the description on register FIRQ_DVOV for the interrupt events. Identification Bit Width Expression Default FIMSK _VBNE 1 Binary 0x1 Description This register masks the "VBI FIFO not empty" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_VBNE for the interrupt events. Identification Bit Width Expression Default FIMSK _VBAE 1 Binary 0x1 Description This register masks the "VBI FIFO almost empty" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_VBAE for the interrupt events. Identification Bit Width Expression Default FIMSK _VBAF 1 Binary 0x1 Description This register masks the "VBI FIFO almost full" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_VBAF for the interrupt events. Identification Bit Width Expression Default FIMSK _VBOV 1 Binary 0x1 Description This register masks the "VBI FIFO Overflow" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register FIRQ_VBOV for the interrupt events. MIMSK_ 0x97 Name Misc. Interrupt Mask Address D7 0x97 DCCD R/W Write/Read D1 D0 SDET VMCLM D6 NINT D5 INT D4 NSTD D3 STD D2 NSDET Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 163 Identification Bit Width Expression Default MIMSK_VMCLM 1 Binary 0x1 Description This register masks the "Video mode (video system) changed" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register MIRQ_VMCLM for the interrupt events. Identification Bit Width Expression Default MIMSK _SDET 1 Binary 0x1 Description This register masks the "Sync detected" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register MIRQ_SDET for the interrupt events. Identification Bit Width Expression Default MIMSK _NSDET 1 Binary 0x1 Description This register masks the "Out of sync" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register MIRQ_NSDET for the interrupt events. Identification Bit Width Expression MIMSK _STD 1 Binary Description This register masks the "Standard signal detected" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register MIRQ_STD for the interrupt events. Default 0x1 Identification Bit Width Expression Default MIMSK _NSTD 1 Binary 0x1 Description This register masks the "Standard signal not detected" interrupt event. Value Operation or Status 0 Unmasked 1 Masked Note Refer to the description on register MIRQ_NSTD for the interrupt events. Identification Bit Width Expression Default MIMSK _INT 1 Binary 0x1 Description This register masks the "Non-interlaced scan not detected " interrupt event. 164 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Value 0 1 Operation or Status Unmasked Masked Note Refer to the description on register MIRQ_INT for the interrupt events. Identification Bit Width Expression Default MIMSK _NINT 1 Binary 0x1 Description This register masks the "Non-interlaced scan detected " interrupt event. Value Operation or Status 0 Masking released 1 Masking applied Note Please refer to the description on register MIRQ_NINT for the interrupt events. Identification Bit Width Expression Default MIMSK _DCCD 1 Binary 0x1 Description This register masks "Copy Control Data Change" interrupt event. Value Operation or Status 0 Masking released 1 Masking applied Note Please refer to the description on register MIRQ_DCCD for the interrupt events. DVFLV_ 0x98 Name DV Port FIFO Trigger Level Address D7 D6 AFL AFL 0x98 3 2 R/W Write/Read D1 D0 AEL AEL 1 0 D5 AFL 1 D4 AFL 0 D3 AEL 3 D2 AEL 2 Identification Bit Width Expression Default DVFLV_AEL 4 Binary 0x8 Description This register set the level of "DV port FIFO almost empty". Value Operation or Status 1 to 14 Specifies the level where the "DV port FIFO almost empty" flag is set. When the number of FIFO stages filled becomes equal to or less than this setting value, the "DV port FIFO almost empty" flag becomes "1". others Reserved Note Identification Bit Width Expression DVFLV_AFL 4 Binary Description This register set the level for "DV port FIFO almost full". Value Operation or Status Default 0x8 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 165 1 to 14 others Note Specifies the level where the "DV port FIFO almost full" flag is set. When the number of empty FIFO stages becomes equal to or less than this setting value, the "DV port FIFO almost full" flag becomes "1". Reserved VBFLV_ 0x99 Name VBI FIFO Trigger Level Address D7 D6 AFL 0x99 rsv 2 R/W Write/Read D1 D0 AEL AEL 1 0 D5 AFL 1 D4 AFL 0 D3 rsv D2 AEL 2 Identification Bit Width Expression Default VBFLV_AEL 3 Binary 0x2 Description This register set the level for "VBI FIFO almost empty" Value Operation or Status 0 to 7 Specifies the level where the "VBI FIFO almost empty" flag is set. When the number of FIFO stages filled becomes equal to or less than the twice this setting value, the "VBI FIFO almost empty" flag is set. Note Identification Bit Width Expression Default VBFLV_AFL 3 Binary 0x2 Description This register set the level for "VBI FIFO almost full". Value Operation or Status 0 to 7 Specifies the level where the "VBI FIFO almost full" flag is set. When the number of empty FIFO stages becomes equal to or less than the twice this setting value, the "VBI FIFO almost full" flag is set. Note VBFDEF_ 0x9A Name VBI FIFO Definitions Address D7 0x9A CGCRC D6 CCNULL D5 WSERR D4 CGERR D3 CCERR D2 WWSS R/W Write/Read D1 D0 WCGMS WCC Identification Bit Width Expression Default VBFDEF_WCC 1 Binary 0x0 Description This register enables or disables writing the closed-caption extracted data into VBI FIFO. Value Operation or Status 166 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 1 Note Disable writing Enable writing Identification Bit Width Expression Default VBFDEF_WCGMS 1 Binary 0x0 Description This register enables or disables writing the CGMS extracted data into VBI FIFO. Value Operation or Status 0 Disable writing 1 Enable writing Note Identification Bit Width Expression Default VBFDEF_WWSS 1 Binary 0x0 Description This register enables or disables writing the WSS extracted data into VBI FIFO. Value Operation or Status 0 Disable writing 1 Enable writing Note Identification Bit Width Expression Default VBFDEF_CCERR 1 Binary 0x0 Description This register enables writing into VBI FIFO even when error was detected in the closed-caption extracted data. Value Operation or Status 0 Disable writing (Do not write into VBI FIFO when error is detected.) 1 Enable writing Note Effective only when the register VBFDEF_WCC ='1'. Identification Bit Width Expression Default VBFDEF_CGERR 1 Binary 0x0 Description This register enables writing into VBI FIFO even when error was detected in the CGMS extracted data. Value Operation or Status 0 Disable writing (Do not write into VBI FIFO when error is detected.) 1 Enable writing Note Effective only when the register VBFDEF_WCGMS= `1'. Identification Bit Width Expression Default VBFDEF_WSERR 1 Binary 0x0 Description This register enables writing into VBI FIFO even when error was detected in the WSS extracted data. Value Operation or Status 0 Disable writing (Do not write into VBI FIFO when error is detected.) 1 Enable writing Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 167 Note Effective only when the register VBFDEF_WWSS= `1'. Identification Bit Width Expression Default VBFDEF_CCNULL 1 Binary 0x0 Description This register enables writing into VBI FIFO even when NULL code (one or more NULL code on a line) was detected in the closed-caption extracted data. Value Operation or Status 0 Disable writing (Do not write into VBI FIFO when NULL is detected.) 1 Enable writing Note Effective only when the register VBFDEF_WCC= `1'. Identification Bit Width Expression Default VBFDEF_CGCRC 1 Binary 0x0 Description This register allows writing CRC when writing the CGMS extracted data into VBI FIFO. Value Operation or Status 0 Disable writing 1 Enable writing Note Effective only when the register VBFDEF_WCGMS= `1'. PWMS_ 0x9B Name PWM Settings Address D7 0x9B MOD R/W Write/Read D1 D0 TC TC 1 0 D6 rsv D5 rsv D4 TC 4 D3 TC 3 D2 TC 2 Identification Bit Width Expression Default PWMS_TC 5 Binary 0x0 Description This register specifies the time constant for the PWM signal directed to the VCXO pin. Value Operation or Status 0 to 31 Time constant: 0: Minimum* 31: Maximum Note Identification Bit Width Expression Default PWMS_MOD 1 Binary 0x1 Description This register specifies the limitation to the duty ratio for the PWM signal directed to the VCXO pin. Value Operation or Status 0 Duty ratio limit =50% ("H" level period does not go over 50%) 1 Duty ratio limit = None Note 168 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet VCXOS_ 0x9C - 0x9D Name VCXO Settings Address D7 0x9C 0x9D VXOFS 7 VXPOL D6 VXOFS 6 D5 VXOFS 5 D4 VXOFS 4 D3 VXOFS 3 D2 VXOFS 2 R/W Write/Read D1 D0 VXOFS 1 VXOFS 0 rsv rsv rsv VXTC 3 VXTC 2 VXTC 1 VXTC 0 Identification Bit Width Expression Default VCXOS_VXOFS 8 2's complement 0x00 Description This register specifies the offset for the VCXO control voltage. Value Operation or Status -128 to +127 The voltage level goes down if the value turns to minus, goes up if it turns to plus, based on zero (0) as its center. Note Identification Bit Width Expression VCXOS_VXTC 4 Binary Description This register specifies the time constant for the VCXO control. Value Operation or Status 0 to 15 Time constant: 0: Maximum * 15: Minimum Note Default 0xB Identification Bit Width Expression Default VCXOS_VXPOL 1 Binary 0x1 Description This register specifies the transition characteristics of the VCXO control voltage (set by the F-V characteristics for VCXO.) Value Operation or Status 0 Inverse F-V characteristic 1 Positive F-V characteristic Note CFRDEF_ 0x9E - 0x9F Name Color Field Reset Signal Definition Address D7 D6 0x9E 0x9F rsv LINE 4 FLDP 2 D5 FLDP 1 D4 FLDP 0 D3 rsv LINE 0 D2 rsv rsv R/W Write/Read D1 D0 FLDN 1 FLDN 0 LINE 3 LINE 2 LINE 1 rsv WID Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 169 Identification Bit Width Expression Default CFRDEF_FLDN 2 Binary 0x3 Description This register sets the color field number to output the resetting pulse (CFR), in the NTSC video mode. Value Operation or Status 0 to 3 Color field #1 ~ #4 Note Identification Bit Width Expression Default CFRDEF_FLDP 3 Binary 0x7 Description This register sets the color field number to output the resetting pulse (CFR), in the PAL video mode. Value Operation or Status 0 to 7 Color field #1 ~ #8 Note Identification Bit Width Expression CFRDEF_WID 1 Binary Description This register sets the output width of the resetting pulse. Value Operation or Status 0 1T(CLKX1) 1 1 line Note Default 0x1 Identification Bit Width Expression Default CFRDEF_LINE 5 2's complement 0x00 Description This register sets the line number to output the resetting pulse. (The top line of the Vsync shall be the 0 line.) Value Operation or Status -16 to +15 From -16th line up to +15th line Note SYNCDEF_ 0xA0 Name SYNC. Detection Definitions Address D7 D6 0xA0 rsv rsv R/W Write/Read D1 D0 SYRT 1 SYRT 0 D5 rsv D4 rsv D3 rsv D2 rsv Identification Bit Width Expression Default SYNCDEF_SYRT 2 Binary 0x0 Description This registrer sets the time to recover input synchronization from self-running sync output, at the time of weak field strength input. Value Operation or Status 170 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 to 3 The bigger the value, the quicker the recovery. Note The parameter only works in the case of unstable input signal such as weak field strength, it has almost no effect when switching over to stable signals like TV or signal generator. PDLDEF_ 0xA1 Name Pedestal Level Detection Definition Address D7 D6 D5 0xA1 rsv rsv rsv R/W Write/Read D1 D0 TC 1 TC 0 D4 ADPT D3 MOD D2 TC 2 Identification Bit Width Expression PDLDEF_TC 3 Binary Description This register sets the time constant to synchronize to the digial clamp. Value Operation or Status 0 to 7 The bigger the value, the quicker it synchronizes. Note Default 0x4 Identification Bit Width Expression PDLDEF_MOD 1 Binary Description This register sets the operation mode of the pedestal clamp. Value Operation or Status 0 Reserved 1 Normal setting Note Default 0x1 Identification Bit Width Expression Default PDLDEF_ADPT 1 Binary 0x1 Description This register sets the synchronization to the pedestal clamp input signal. Value Operation or Status 0 Always synchronizing 1 Stops synchronizing when the sync detection unstable. Note This register setting is only valid when the register PDLDEF_MOD = `1'. TPGENS_ 0xA2 Name Test Pattern Generator Setting Address D7 D6 0xA2 Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC AMPS 2 AMPS 1 D5 AMPS 0 D4 PICS 2 D3 PICS 1 D2 PICS 0 R/W Write/Read D1 D0 MODE 1 MODE 0 Advanced Information 171 Identification Bit Width Expression TPGENS_MODE 2 Binary Description Set the category of the test pattern image. Value Operation or Status 0 Image of the input signal (test pattern OFF) 1 Color bar image 2 Ramp image 3 Raster image Note Default 0x0 Identification Bit Width Expression Default TPGENS_PICS 3 Binary 0x0 Description This register selects the options for each test pattern image. Value Operation or Status 0 to 7 For the register TPGENS_MODE setting 1/2/3, the image varies. As for the details please refer to the Table 5.6. Note There are no other definitions other than Table 5.6. Identification Bit Width TPGENS_AMPS 2 Description This register sets options for each test pattern. Value Operation or Status 0 1.0 time 1 0.75 times 2 0.5 times 3 0.25 times 4 0 time 5-7 (1.0 time) Note Expression Binary Default 0x0 Table 5.6 Test Patterns Pattern Mode Color Bar Ramp Raster Pattern Option 100% Color bar 75% Color Bar Ramp Mod Ramp White Yellow Cyan Green Magenta Red Blue Black TPGENS_PICS 000 001 000 001 000 001 010 011 100 101 110 111 TPGENS_MODE 01 01 10 10 11 11 11 11 11 11 11 11 172 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet SNRMON_ 0xA8 - 0xA9 Name Signal Noise Ratio Monitor Address D7 D6 0xA8 0xA9 SLEV 7 NLEV 7 SLEV 6 NLEV 6 D5 SLEV 5 NLEV 5 D4 SLEV 4 NLEV 4 D3 SLEV 3 NLEV 3 D2 SLEV 2 NLEV 2 R/W Read D1 SLEV 1 NLEV 1 D0 SLEV 0 NLEV 0 Identification Bit Width SNRMON_SLEV 8 Description This register indicates the signal level. Value Operation or Status 0 to 0xFF Signal level Note Expression Binary Default - Identification Bit Width SNRMON_NLEV 8 Description This register indicates the noise level. Value Operation or Status 0 to 0xFF Noise level Note Expression Binary Default - HLJINF_ 0xAA Name H Lock Judgement Information Address D7 D6 0xAA LCKE 7 LCKE 6 D5 LCKE 5 D4 LCKE 4 D3 LCKE 3 D2 LCKE 2 R/W Read D1 LCKE 1 D0 LCKE 0 Identification Bit Width Expression Default HLJINF_LCKE 8 Binary Description This register indicates the deviation (error level) when operating in VCXO-H-Lock mode. Value Operation or Status 0 to 0xFF H-Lock error level Note CFSINF_ 0xAB Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 173 Name Color Field Sequence Information Address D7 D6 D5 0xAB rsv rsv rsv D4 rsv D3 CONF D2 CFSQ 2 R/W Read D1 CFSQ 1 D0 CFSQ 0 Identification Bit Width Expression CFSINF_CFSQ 3 Binary Description This register indicates the current color field number. Value Operation or Status 0 to 0x7 From color field No#1 to #8 Note Default - Identification Bit Width Expression CFSINF_CONF 1 Binary Description This register indicates 1 when CFSINF_CFSQ is firm. Value Operation or Status 0 Not defined yet 1 Firm Note Default - VTRDEF_ 0xAC Name VTR Detection Address D7 0xAC rsv R/W Read D1 VTR 1 D6 rsv D5 rsv D4 rsv D3 rsv D2 WEAK D0 VTR 0 Identification Bit Width Expression Default VTRDEF_VTR 2 Binary Description This register indicates the current input signal souce classification the XV750C acknowledges, resulting of VTR judgement. Value Operation or Status 0 Standard signal such as TV signal 1 Signal under VTR normal replay 2 Signal under VTR particular replay 3 Unable to distinguish Note Identification Bit Width Expression Default VTRDEF_WEAK 1 Binary Description This register indicates the current input signal souce classification the XV750C acknowledges, resulting of weak field strength judgement. Value Operation or Status 174 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 0 1 Note Stable signal Weak field signal Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 175 5.3. Default Values for Register Settings As for the default value (setting values when the XV750C once reset) in the register settings, please refer to the following main configurations. Video System Analog Input (mode 0) Analog Input (mode 1) Analog Input (mode 2) Analog Input (mode 3) Analog Input Selection Digital Output (SV mode) Digital Output (DV mode) DV mode Read Clock Operating Clock PJC TBC Comb Filter Selection (PAL) AGC/ACC Interrupt Masking GPIO VBI Data Extraction VBI Path Through Group Automatic (Active for all modes the XV750C supports) Composite Video S Video Component Video (7:3 Video/Sync Ratio) Component Video (10:4 Video/Sync Ratio) Analog Input Mode 0 ITU-R BT.656 Output Addition SAV and EAV Internal Supply Freeunning AUTO On Adaptive 5 line Comb Filter Hybrid Masking on every Interrupt Event Register IO Mode Ineffective Ineffective 176 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 6. Sample Circuit A sample circuit is shown in Figure 6.2. IIX Inc. recommends inserting a filter as shown in Figure 6.1 in the analog video signal input stage. This is to cope with the interfering distortion opt to be caused between the sampling clock of the XV750C and the input video signal superposed with 27MHz aliasing noise. In case input video signal carries no such problem, this filer is not required. C3 18p L1 1.8u 10u AINnm C1 220p C2 220p R1 75 XV750C L1:*(c)ZUg*"30MHz @* E OE " u Z Figure 6.1 Anti Aliasing Filter Sample Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 177 10uF 75 10uF +2.5V Analog VDD 75 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 103 111 117 125 100 101 105 109 119 75 10uF AGND AGND AGND AGND AGND 128 99 Analog GND AGND AVDD AVDD AVDD AVDD 10uF AVDD 5 GPIO0 6 GPIO1 7 75 118 220pF 120 AIN01 122 AIN02 10uF 124 AIN03 AIN00 GPIO2 8 GPIO3 10 GPIO4 11 GPIO5 12 GPIO6 13 GPIO7 GPIO 75 (open) (open) 10uF 116 AIN10 114 AIN11 112 AIN12 110 AIN13 SVO0 SVO1 GPIO9 GPIO8 16 17 22 23 75 25 10uF (open) (open) (open) 108 AIN20 106 AIN21 104 AIN22 102 AIN23 SVO2 26 SVO3 27 SVO4 28 SVO5 31 SVO6 32 SVO7 33 SVO8 34 SVO9 SV Port Data 75 121 VCM 123 VBG 127 VREFP 126 VREFN 0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 107 VBYP 113 VBYN 115 IBIAS SHS 49 SCK 79 CKX1 77 CKX2 43 DVO00 44 DVO01 27MHz 1M 84 VCXO 82 XTLI C2 R3 81 XTLO DVO04 52 DVO05 54 91 TDO 93 TDI 94 TMS 95 TCK 96 TRST_N DVO11 63 DVO12 1K 20 SCL 21 SDA 2 IOAS DVO15 67 DVO14 66 DVO13 65 64 DVO10 60 DVO09 59 DVO08 58 DVO07 57 DVO06 55 DVO03 51 DVO02 46 45 SVS 41 SHB 40 SVB 39 SCBF 38 SFLD 37 36 SV Port Timing XV750CQ1-01 EXT CLOCK C1 QFP128 JTAG (open) (open) (open) (open) +3.3V Digital VDD SerialClock SerialData DV Port Data Reset PowerDown OutputEnable 90 RST_N 86 PWDN 89 OE DTRDY 69 DCK 71 DVAL 72 DGHP 73 DGVP DV Port Timing (open) (open) (open) 1 TEST_N 87 TSCE_N 97 TAFE_N DGP1 DGP0 74 75 18 IRQ_N VDDI VDDI VDDI VSSI VSSI VDD VDD VDD VDD VDD VDD VDD VDD VSSI InterruptRequest VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 85 98 15 48 92 24 30 35 42 50 56 62 70 76 14 29 47 61 68 78 83 19 53 +3.3V Digital VDD 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 88 0.1uF JTAG'[ZqI*--a(2) (open) (open) (open) (open) 91 TDO 93 TDI 94 TMS 95 TCK 96 TRST_N JTAG'[ZqI*--(3) a (open) (open) (open) (open) 91 TDO 93 TDI 94 TMS 95 TCK 96 TRST_N 80 +2.5V Digital VDD 4 3 9 VSS Digital GND Figure 6.2 Sample circuit 178 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 7. Electrical Characteristics 7.1. Absolute Maximum Ratings Table 7.1 Absolute Maximum Ratings Item Power Supply Input Volt Storage Temp. Symbol VDD33 VDD25 VI Tstg Conditions Range -0.5 ~ +4.6 -0.5 ~ +3.5 -0.5 ~ +6.0 -65 ~ +150 Unit V V V o C 7.2. Recommended Operating Conditions Table 7.2 Recommended Operating Conditions Item Power Supply Operation Temp. High Level Input Voltage Low Level Input Voltage Junction Temp. Symbol VDD33 VDD25 VDD25A Topt VIH VIL Tj Conditions MIN. 3.0 2.25 2.25 0 2.0 -0.3 0 TYP. 3.3 2.5 2.5 25 MAX 3.6 2.75 2.75 75 5.5 0.8 Unit V V V o C V V o 25 125 C Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 179 7.3. DC, AC Characteristics 7.3.1. Analog Characteristics Table 7.3 Analog Characteristics Item Consumption Current ADC Effective Number Of Bits ADC Differential Non Linearity ADC Integration Non Linearity ADC Differential Gain ADC Differential Phase ADC Voltage Reference Analog Input Range AIN0n(n=0,1,2,3) Clamp Voltage AIN1n(n=0,1,2,3) Clamp Voltage AIN2n(n=0,1,2,3) Clamp Voltage Signal Noise Ratio Channel Cross Talk Symbol IDD25A ENOB DNL INL DG DP VREFN VREFP VINRG VCL0 VCL1 VCL2 SNR CCT Conditions Ych,Cch,Pch ON fin = 4.45MHz Fin = 4.45MHz Fin = 4.45MHz MIN. TYP. 100 9.5 +/-0.8 +/-1.5 +/-1 +/-1 0.8 1.8 2.0 0.03 1.3 1.3 MAX - Unit mA bit LSB LSB % Deg. V V V V V V dB dB 50 AIN0n - AIN1n AIN1n - AIN2n AIN0n - AIN2n -50 180 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet 7.3.2. DC Characteristics (Digital) Table 7.4 DC Characteristics (Digital) Item High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current Symbol VOH VOL IOH IOL Conditions IOH=8mA IOL=8mA VOH=2.4V VOL=0.4V MIN. 2.4 TYP. MAX Unit V V mA mA 0.4 9.5 8.1 7.3.3. AC Characteristics (Digital) Table 7.5 AC Characteristics (Digital) PIN RST_N XTLI DCK XTLO CKX2 SCK Symbol Trst Tclk Tclk Trise Tfall Trise Tfall Trise Tfall T13.5rise T13.5fall Trise Tfall T13.5rise T13.5fall T13.5aa T13.5dh T13.5aa T13.5dh T27aa T27dh T13.5aa T13.5dh T27aa T27dh T13.5aa T13.5dh T27aa T27dh T13.5aa Parameter Input Pulse Width Input Clock Frequency Input Clock Frequency Clock Rise Delay Clock Fall Delay Clock Rise Delay Clock Fall Delay Clock Rise Delay Clock Fall Delay Clock Rise Delay Clock Fall Delay Clock Rise Delay Clock Fall Delay Clock Rise Delay Clock Fall Delay Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) MIN 37 TYP MAX 27 54 3 3 16 14 18 16 24 22 16 15 19 18 26 25 10 20 8 20 8 21 9 21 9 20 8 20 Unit ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DCK CKX1 VCXO IRQ_N SVB 1 1 8 7 8 7 11 10 7 7 9 8 11 SHB SVS Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 181 PIN SHS SFLD SCBF SVO GPIO DGP0 DGP1 DGHP DGVP DVO DTRDY SDA SCL Symbol T13.5dh T27aa T27dh T13.5aa T13.5dh T27aa T27dh T13.5aa T13.5dh T27aa T27dh T13.5aa T13.5dh T27aa T27dh T13.5aa T13.5dh T13.5aa T13.5dh Twaa Twdh Traa Trdh Twaa Twdh Traa Trdh Twaa Twdh Traa Trdh Twaa Twdh Traa Trdh Twaa Twdh Traa Trdh Tds Tdh Tds Tdh Tds Tdh Tds Tdh Parameter Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(13.5MHz) Output Delay(27MHz) Output Delay(27MHz) Output Delay(DCK) Output Delay(DCK) Output Delay(27MHz) Output Delay(27MHz) Output Delay(DCK) Output Delay(DCK) Output Delay(27MHz) Output Delay(27MHz) Output Delay(DCK) Output Delay(DCK) Output Delay(27MHz) Output Delay(27MHz) Output Delay(DCK) Output Delay(DCK) Output Delay(27MHz) Output Delay(27MHz) Output Delay(DCK) Output Delay(DCK) Input Setup(27MHz) Input Hold(27MHz) Input Setup(DCK) Input Hold(DCK) Input Setup Input Hold Input Setup Input Hold MIN 8 8 TYP MAX 20 21 9 20 8 20 12 21 9 21 9 20 8 20 8 26 24 9 12 4 24 9 12 4 21 9 12 4 22 9 13 4 21 9 12 4 0 15 6 1 0 20 0 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 182 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Trst RST_N T c lk T W hig h T W lo w XT L I D CK T ris e XT L O CKX 2 SC K D CK Tfa ll T 13 .5rise T 13 .5 fall CKX 1 SCK T 27 aa Tw aa/ T raa T 27 d h Tw d h / T rd n O u tp ut D ela y ( 2 7M H z ) T 13 .5aa T 1 3 .5 d h O u tp ut D ela y ( 1 3.5 M H z ) Tds Tdh Inp u t S etu p / H o ld Figure 7.1 AC Characteristics (Digital) Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 183 8. Packaging 128pin QFP (XV750CQ1) E E1 E2 -AAE D1 D2 D -D- bbb C A - B D ccc M C A - B S D S AE 1 e ddd C SEATING PLANE - C b 4X 184 c Advanced Information 4X - 0.10 S aaa C A - B D 1L -B"A" A2 A1 A Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER SYMBOL AE 2 A A1 A2 D D1 R1 E E1 0.25 2.50 2.72 23.20 BASIC 20.00 BASIC 17.20 BASIC 14.00 BASIC 0.13 0.13 0* 1 0* 7* REF 15* 0.11 0.73 REF 0.23 1.03 0.004 0.029 7* 0.30 2.90 MIN. NOM. MAX. 3.40 0.010 0.098 0.107 0.114 MIN. NOM. MAX. 0.134 INCH 0.913 BASIC 0.787 BASIC 0.677 BASIC 0.551 BASIC 0.005 0.005 0* 0* 7* 15* REF REF 0.009 0.041 7* 0.012 -HR2 GAGE PLANE AE 0.25mm S AE 3 L R2 R1 AE ALLOY 42 L/F AE2 , AE3 COPPER L/F AE2 , AE3 c L L1 0.15 0.88 1.60 REF 0.006 0.035 0.063 REF DETAIL "A" S b e D2 0.20 0.170 0.200 0.50 BASIC 18.50 12.50 0.270 0.008 0.007 0.008 0.011 0.020 BASIC 0.728 0.492 NOTES: 1. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE - H DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. E2 TOLERANCES OF FORM AND POSITION aaa bbb ccc ddd 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 2. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 185 This device is protected by U.S. patent number 4,907,093 and other intellectual property rights. Purchase of I2C components of IIX, Inc., conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 186 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC XV750C Data Sheet Concerning the usage of technological information described in this document, IIX Inc. does not permit the use of industrial property rights, intellectual property rights or any other rights of IIX Inc. or of the third parties. Further, the information described in this document such as the circuit diagrams, is for the purpose of operational explanation and for the application example of our product, and not described aiming for the usage with the customers' equipment. Although IIX Inc. doing every effort to improve the our product quality and reliability, semiconductor product might cause miss-operations and failures. Please pay enough attention for the safety in designing such as redundant design, anti-fire-spreading design, miss-operation preventive design etc., in order not to cause any personal accidents, fire accidents, social damages etc., resulted from the miss-operations or failures of our product. When designing, please use the product within the range of product guarantee such as maximum ratings, operational power voltage etc, confirming the newest product specifications. Please understand that IIX Inc. will not take any responsibilities for the damages caused by the usage beyond the guaranteed range. The product described in this document is intended for the use only with common electronics equipment such as computer, personal electronics equipment, office equipment, telecommunications equipment, measuring equipment, home appliances etc. Please, therefore, refrain from applying for such equipment like atomic power control equipment, aerospace equipment, transport equipment, traffic signal equipment, combustion control equipment, medical equipment, various safety device etc, as to its miss-operation and failure might develop to threat human life directly or to cause bodily injuries. Please understand that IIX Inc. will not take any responsibilities for such usage and for such damage caused by the usage not intended by IIX Inc. Contents described herein are subject to change at any time without notice. Reprinting and/or reproduction of the contents of this document in whole or in part without written approval of IIX Inc., shall be strictly prohibited. Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC Advanced Information 187 188 Advanced Information Draft 1.03E Apr. 15, 2003 VDD-005-011-02 (c) 2003 IIX INC |
Price & Availability of XV750C
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |