MSM64164C
4-Bit Microcontroller User's Manual
FIRST EDITION December 1998
OKI ELECTRIC INDUSTRY CO., LTD.
E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan
Introduction
The MSM64164C is a high-performance single chip microcontroller that uses a 4-bit CPU core (nX-4/20). This Oki-original CPU core architecture is combined with additional on-Chip peripheral functions. This manual explains hardware of the MSM64164C. For details of the nX-4/20 core instruction set, refer to the "nX-4/20, nX-4/30 Core Instruction Manual".
Table of Contents
Chapter 1 Overview 1.1 1.2 1.3 1.4 1.5 Overview .......................................................................................................... 1-1 Features ........................................................................................................... 1-1 Block Diagram.................................................................................................. 1-3 Pin Configuration ............................................................................................. 1-4 Pin Description ................................................................................................. 1-7 1.5.1 Description of Each Pin ........................................................................ 1-7 1.5.2 Unused Pin Description ........................................................................ 1-12 1.6 Basic Timing .................................................................................................... 1-13 Chapter 2 CPU 2.1 Overview .......................................................................................................... 2-1 2.2 Layout of Registers .......................................................................................... 2-2 2.2.1 Registers A, B, H, L, X and Y ............................................................... 2-3 2.2.2 Program Counter (PC) .......................................................................... 2-4 2.2.3 Stack Pointer (SP) ................................................................................ 2-4 2.2.4 Carry Flag (C) ....................................................................................... 2-4 2.3 Memory Space ................................................................................................. 2-5 2.3.1 Program Memory Space ....................................................................... 2-5 2.3.2 Data Memory Space ............................................................................. 2-6 2.3.2.1 Data Memory Space ............................................................... 2-6 2.3.2.2 Bank Selection of Data Memory ............................................. 2-7 2.3.2.3 Addressing Modes of Data Memory ....................................... 2-8 Chapter 3 CPU Control Functions 3.1 Overview .......................................................................................................... 3-1 3.2 System Reset Function .................................................................................... 3-2 3.2.1 System Reset Operation by RESET Input Pin ...................................... 3-2 3.2.2 State at System Reset .......................................................................... 3-4 3.3 Halt Mode ......................................................................................................... 3-7 3.3.1 Halt Mode Register (HALT) .................................................................. 3-7 3.3.2 Operation of Halt Mode ........................................................................ 3-7 Chapter 4 Interrupt (INTC) 4.1 Overview .......................................................................................................... 4-1 4.2 Interrupt Sequence .......................................................................................... 4-3 4.3 Interrupt Control Registers ............................................................................... 4-4 4.3.1 Interrupt Request Registers (IRQ0, IRQ1 and IRQ2) ........................... 4-4 4.3.2 Interrupt Enable Registers (IE0, IE1 and IE2) ...................................... 4-7 4.3.3 Master Interrupt Enable Register (MIEF) .............................................. 4-9
-i-
Chapter 5 Clock Generation Circuit (2CLK) 5.1 5.2 5.3 5.4 5.5 Overview .......................................................................................................... 5-1 Layout of Clock Generation Circuit .................................................................. 5-1 Operation of Clock Generation Circuit ............................................................. 5-2 Frequency Control Register (FCON) ............................................................... 5-2 System Clock Switch Timing............................................................................ 5-3
Chapter 6 Time Base Counter (TBC) 6.1 6.2 6.3 6.4 Overview .......................................................................................................... 6-1 Layout of Time Base Counter .......................................................................... 6-1 Operation of Time Base Counter ..................................................................... 6-2 Time Base Counter Register (TBCR) .............................................................. 6-2
Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.1 Overview .......................................................................................................... 7-1 7.2 Port 0 and Port 1 (P0.0 to P0.3 and P1.0 to P1.3) ........................................... 7-2 7.2.1 Layout of Port 0 and Port 1 ................................................................... 7-2 7.2.2 Registers Related to Port 0 and Port 1 ................................................. 7-4 7.2.3 External Interrupt Generation Timing of Port 0 ..................................... 7-7 7.3 Port 2, Port 3 and Port 4 (P2.0 to P2.3, P3.0 to P3.3 and P4.0 to P4.3) ......... 7-9 7.3.1 Layout of Port 2, Port 3 and Port 4 ....................................................... 7-9 7.3.2 Registers Related to Port 2, Port 3 and Port 4 ..................................... 7-11 7.3.3 External Interrupt Generation Timing of Port 2, Port 3 and Port 4 ........ 7-27 Chapter 8 Serial Port (SIOP) 8.1 8.2 8.3 8.4 Overview .......................................................................................................... 8-1 Layout of Serial Port ........................................................................................ 8-2 Operation of Serial Port ................................................................................... 8-3 Registers Related to Serial Port....................................................................... 8-5
Chapter 9 Buzzer Driver (BD) 9.1 9.2 9.3 9.4 9.5 Overview .......................................................................................................... 9-1 Layout of Buzzer Driver ................................................................................... 9-1 Operation of Buzzer Driver .............................................................................. 9-1 Registers Related to Buzzer Driver.................................................................. 9-3 BD Output Waveform and External Circuit ...................................................... 9-5
Chapter 10 Capture Circuit (CAPR) 10.1 10.2 10.3 10.4 Overview .......................................................................................................... 10-1 Layout of Capture Circuit ................................................................................. 10-1 Operation of Capture Circuit ............................................................................ 10-2 Registers Related to Capture Circuit ............................................................... 10-3
- ii -
Chapter 11 Watchdog Timer (WDT) 11.1 11.2 11.3 11.4 Overview ......................................................................................................... 11-1 Layout of Watchdog Timer .............................................................................. 11-1 Operation of Watchdog Timer ......................................................................... 11-2 Watchdog Timer Control Register (WDTCON) ............................................... 11-3
Chapter 12 A/D Converter (ADC) 12.1 Overview ......................................................................................................... 12-1 12.2 Layout of A/D Converter ................................................................................. 12-1 12.3 Operation of A/D Converter ............................................................................ 12-1 12.3.1 RC Oscillation Circuit ......................................................................... 12-3 12.3.2 Counter A/B Reference Mode ........................................................... 12-6 12.3.3 Example of Usage of A/D Converter ................................................. 12-10 12.3.4 RC Oscillation Monitor ....................................................................... 12-16 12.4 Registers Related to A/D Converter................................................................ 12-17 Chapter 13 LCD Driver (LCD) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Overview ......................................................................................................... 13-1 Layout of LCD Driver ...................................................................................... 13-1 Operation of LCD Driver ................................................................................. 13-4 Display Control Register (DSPCON) .............................................................. 13-4 Display Registers 0 to 30 (DSPR0 to 30) ........................................................ 13-5 Output Port Selection by Mask Option ............................................................ 13-6 Bias Generation Circuit for LCD Driver (BIAS) ............................................... 13-7 LCD Driver Output Waveforms ....................................................................... 13-8
Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR) 14.1 14.2 14.3 14.4 Overview ......................................................................................................... 14-1 Layout of Constant Voltage Circuit for Logic Power Supply ........................... 14-1 Operation of Constant Voltage Circuit for Logic Power Supply ...................... 14-2 Backup Control Register (BUPCON) .............................................................. 14-3
Chapter 15 Test Circuit (TST) 15.1 Overview ......................................................................................................... 15-1 15.2 Operation of Test Circuit ................................................................................. 15-1
- iii -
Appendixes Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Appendix H List of Special Function Registers ............................................ Appendix-1 Description of Special Function Registers ................................ Appendix-5 Package Dimension Diagrams and Pad Coordinates .............. Appendix-38 Layout of Input/Output Circuits ................................................. Appendix-41 Examples of Application Circuit ................................................ Appendix-44 Mask Options ............................................................................ Appendix-46 Electrical Characteristics .......................................................... Appendix-54 Instruction List .......................................................................... Appendix-74
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Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9
Overview CPU CPU Control Functions Interrupt (INTC) Clock Generation Circuit (2CLK) Time Base Counter (TBC) Ports (P0, P1, P2, P3 and P4) Serial Port (SIOP) Buzzer Driver (BD)
1 2 3 4 5 6 7 8 9 10 11 12 13
Chapter 10 Capture Circuit (CAPR) Chapter 11 Watchdog Timer (WDT) Chapter 12 A/D Converter (ADC) Chapter 13 LCD Driver (LCD)
Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR) 14 Chapter 15 Test Circuit (TST) Appendixes 15
Chapter 1
1
Overview
This chapter describes the features, block diagrams, pin configurations, pin descriptions and basic operation timings.
MSM64164C User's Manual Chapter 1 Overview
Chapter 1 Overview
1.1 Overview The MSM64164C is a CMOS 4-bit microcontroller that has built-in 256-nibble RAM, 20 I/O ports, buzzer output, a serial port, a 2-channel RC oscillation type A/D converter and 34 LCD segment drivers. The MSM64164C uses a high-performance 4-bit CPU core (nX-4/20) with byte processing instructions and is best suited for applications such as thermometers, hygrometers and body thermometers because of its compact chip layout and rich peripheral functions. 1.2 Features (1) Rich instruction set including byte operation instructions * 148 instructions * Byte addition/subtraction, byte transfer and byte comparison instructions * Bit manipulation instructions * Data exchange instructions Rich addressing modes * Two kinds of indirect addressing modes using HL register and XY register * Bit manipulation on entire data memory area * Byte operation on entire data memory area Operating frequencies * Low speed clock 32.768 kHz crystal oscillation (minimum instruction execution time: 91 s) * High speed clock 400 kHz RC oscillation Built-in program memory : 4064 bytes Built-in data memory : 256 nibbles
1
(2)
(3)
(4) (5) (6)
I/O ports : 20 * 4-bit input/output port (NMOS open drain output/CMOS output selectable, input with pull-down/pull-up resistance or high-impedance input selectable) 3 * 4-bit input port (Input with pull-down/pull-up resistance selectable) 1 * 4-bit output port (NMOS open drain output/CMOS output selectable) 1 Buzzer output :1 * 4 output modes selectable Serial port :1
(7)
(8)
* Synchronous 8-bit transfer * External clock/internal clock selectable * MSB head/LSB head selectable 1-1
MSM64164C User's Manual Chapter 1 Overview (9) LCD driver : 34 * At 1/4 duty and 1/3 bias : 120 segments (30 4) * At 1/3 duty and 1/3 bias : 93 segments (31 3) * At 1/2 duty and 1/2 bias : 64 segments (32 2) * Output port selectable by mask option for 8 drivers
(10) RC oscillation method A/D converter : 2 channels * Time dividing 2-channel method * A counter: 1/(104 8) 1 * B counter :1/214 1 (11) Capture circuit : 2 channels * 256 Hz, 128 Hz, 64 Hz and 32 Hz (12) Watchdog timer (13) Interrupt causes: 10 causes * 2 external causes, 5 time base causes, 1 serial port cause, 1 A/D converter cause and 1 watchdog timer cause (14) Power supply voltage * 1.5 V/3 V selectable by mask option * Low power consumption (15) Exterior * Chip : MSM64164C-xxx * 80-pin flat package (QFP) : MSM64164C-xxxGS-K (QFP80-P-1414-0.65-K) MSM64164C-xxxGS-BK (QFP80-P-1420-0.80-BK) MSM64164C-xxxTS-K (TQFP80-P-1212-0.50-K)
1-2
Figure 1-1 shows the block diagram of the MSM64164C.
1.3 Block Diagram
BIAS
VSS1 VSS2 VSS3 C1 C2 L0 L1 to L33 VSS
BSR HALT C
TR2
TR0 (4) ALU
TR1
ROM 4064B PORT ADDRESS
LCD
PCM PCL
PCH A11 to A8 A7 to A0 RAM 256N
Figure 1-1 MSM64164C Block Diagram
B
A
H
L
X
Y
P2 P3 P4 INT VSS
P2.0 P2.1 to P4.3
MIEF
(4)
(4)
DB7 to DB0 OSC2 OSC1 XT XT
(8)
1-3
2CLK
TIMING CONTROLLER
SP
ROMR
SIOP
P1
P1.0 P1.1 P1.2 P1.3 VSS
IR DECODER
INT IR (8) INT P0 PORT ADDRESS DB7 to DB0 P0.0 P0.1 P0.2 P0.3
RESET
RSTC
TBC 5 INT
MSM64164C User's Manual Chapter 1 Overview
TST1 TST2
TST
VSSL
VR INT WDT INT Indicates the CPU core (nX-4/20) INTC CAPR BD ADC
VSS VDD
BD
IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1
1
MSM64164C User's Manual Chapter 1 Overview 1.4 Pin Configuration The pin configuration of the package of MSM64164C and the chip exterior figure are shown in Figure 1-2, 1-3 and 1-4.
RESET OSC1 66 OSC2 65
TST2
TST1
80
79
78
77
76
75
74
73
72
71
70
69
68
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
67
VDD
P0.3
P0.2
P0.1
P0.0
P1.3
P1.2
P1.1
P1.0
XT
XT
64 63 62 61 60 59 58 57 56 55 54
L33/P6.3 L32/P6.2 L31/P6.1 L30/P6.0 L29/P5.3 L28/P5.2 L27/P5.1 L26/P5.0 L25 L24 L23 L22 L21 L20 L19 L18 L17 C2 C1 VSS3 VSS2 VSS VSS1 RT1
[NOTE]: Since pins 32 and 67 are shorted inside the IC, VDD can be supplied from either side.
53 52 51 50 49 48 47 46 45 44 43 42 41
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 CS1
P3.3
P4.0
P4.1
P4.2
P4.3
CRT0
IN0
RT0
RS0
CS0
IN1
Figure 1-2 MSM64164C (QFP: GS-BK) Pin Configuration 1-4
VSSL
VDD
RS1
BD
40
MSM64164C User's Manual Chapter 1 Overview
L33/P6.3
L32/P6.2
RESET
OSC1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
OSC2
TST2
TST1
1
VDD
P0.3
P0.2
P0.1
P0.0
P1.3
P1.2
P1.1
P1.0
XT
XT
L1
L0
62
L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
L31/P6.1 L30/P6.0 L29/P5.3 L28/P5.2 L27/P5.1 L26/P5.0 L25 L24 L23 L22 L21 L20 L19 L18 L17 C2 C1 VSS3 VSS2 VSS
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 RT1
CRT0
IN0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
VDD
RT0
RS0
CS0
IN1
CS1
VSSL
RS1
BD
[NOTE]: Since pins 30 and 65 are short-circuited inside the IC, VDD can be supplied from either side.
Figure 1-3 MSM64164C (QFP: GS-K, TQFP: TS-K) Pin Configuration
1-5
VSS1
40
MSM64164C User's Manual Chapter 1 Overview MSM64164C-xxx Chip size : 5.39 mm 4.48 mm / Thickness : 350 m (Typ.)
Y
X
* Power supply of the back of chip is VDD * Numbers 1 through 80 show pad numbers (PAD No.) Figure 1-4 MSM64164C Chip Exterior Figure
1-6
MSM64164C User's Manual Chapter 1 Overview 1.5 Pin Description 1 1.5.1 Description of Each Pin The basic functions of each pin of the MSM64164C are shown in Table 1-1 and their secondary functions are shown in Table 1-2.
Table 1-1 (A) Description of Pin (Basic Function)
Pin No. Classification Power supply Pin name VDD VSS1 GS-BK 32, 67 42 GS-K TS-K 30, 65 40
Pad No. Input/ Output 32, 67 42 -- --
Function 0 V power supply Negative side power supply (at 1.5 V spec.) Bias output for driving LCD (-1.5 V) (at 3.0 V spec.) Negative side power supply (at 3.0 V spec.) Bias output for driving LCD (-3.0 V) (at 1.5 V spec.) Bias output for driving LCD (-4.5 V) Negative side power supply for input/ output port interface Capacitor connection pin for LCD driving bias generation Negative side power supply pin for internal logic (internally generated constant voltage) Low speed side clock oscillation input pin: Connects to the crystal oscillator (32.768 kHz)
VSS2
44
42
44
--
VSS3 VSS C1 C2 VSSL
45 43
43 41
45 43
-- --
46 47 31
44 45 29
46 47 31
-- -- --
Oscillation
XT
69
67
69
Input
XT
68
66
68
Output Low speed side clock oscillation output pin: Connects to the crystal oscillator (32.768 kHz) High speed side clock oscillation pin: Connects to the external resistance of Output oscillation (ROS). Input Input Input Input Input pin for test: Pulled-up to VDD inernally. System reset input: When this pin becomes "H" level from "L" level, the internal state is initialized and execution of an instruction starts from address 000H. Pulled-up to VDD internally.
OSC1 OSC2 Test TST1 TST2 Reset RESET
66 65 71 72 70
64 63 69 70 68
66 65 71 72 70
1-7
MSM64164C User's Manual Chapter 1 Overview Table 1-1 (B) Pin Description (Basic Functions)
Pin No. Classification Port Pin name P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 GS-BK 77 78 79 80 73 74 75 76 18 19 20 21 22 23 24 25 26 GS-K TS-K 75 76 77 78 71 72 73 74 16 17 18 19 20 21 22 23 24
Pad No. Input/ Output 77 78 79 80 73 74 75 76 18 19 20 21 22 23 24 25 26 Input Input Input Input
Function 4-bit input port (P0): Can select (1) input with pull-up resistance, (2) input with pull-down resistance or (3) input with high impedance by the port 01 control register (P01CON). As a secondary function, P0.0 to P0.3 are assigned external interrupt functions and P0.0 and P0.1 are assigned a capture trigger function.
Output 4-bit output port (P1): Can select NMOS open drain output or Output CMOS output by the port 01 control Output register (P01CON). P1.0 is a large current drive output port. Output Input/ 4-bit input/output port (P2): Output Can select (1) pull-up or pull-down resistance input, (2) high impedance Input/ input, (3) NMOS open drain output or Output (4) CMOS output by the port 2 control Input/ registers 0 to 3 (P20CON to P23CON). Output As secondary functions, P2.0 to P2.3 are assigned external interrupt Input/ functions. Output Input/ 4-bit input/output port (P3): Output Can select (1) pull-up or pull-down resistance input, (2) high impedance Input/ input, (3) NMOS open drain output or Output (4) CMOS output by the port 3 control Input/ registers 0 to 3 (P30CON to P33CON). Output As secondary functions, P3.0 to P3.3 are assigned external interrupt Input/ functions, and P3.3 is assigned a Output serial port function. Input/ 4-bit input/output port (P4): Output Can select (1) pull-up or pull-down resistance input, (2) high impedance Input/ input, (3) NMOS open drain output or Output (4) CMOS output by the port 4 control registers 0 to 3 (P40CON to 43CON). Input/ As secondary functions, P4.0 to P4.3 Output are assigned external interrupt functions, P4.0 to P4.2 are assigned a serial port function and P4.3 is assigned Input/ a monitor function for the A/D converter Output RC oscillation clock.
P4.1
27
25
27
P4.2
28
26
28
P4.3
29
27
29
1-8
MSM64164C User's Manual Chapter 1 Overview Table 1-1 (C) Pin Description (Basic Functions) 1
Pin No. Classification Buzzer A/D converter Pin name BD RT0 GS-BK 30 33 GS-K TS-K 28 31 Pad No. Input/ Output 30 33 Function
Output Output pin for the buzzer drive Output Resistance sensor connection pin for measurement of Channel 0 Output Resistance/capacitance sensor connection pin for measurement of Channel 0. Output Reference resistance connection pin of Channel 0 Output Reference capacitance connection pin of Channel 0 Input Input pin of RC oscillation circuit of Channel 0
CRT0
34
32
34
RS0
35
33
35
CS0
36
34
36
IN0
37
35
37
RT1
41
39
41
Output Resistance sensor connection pin for measurement of Channel 1 Output Reference resistance connection pin of Channel 1 Output Reference capacitance connection pin of Channel 1 Input Input pin of RC oscillation circuit of Channel 1
RS1
40
38
40
CS1
39
37
39
IN1
38
36
38
1-9
MSM64164C User's Manual Chapter 1 Overview Table 1-1 (D) Pin Description (Basic Functions)
Pin No. Classification LCD driver Pin name L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26/P5.0 L27/P5.1 L28/P5.2 L29/P5.3 L30/P6.0 L31/P6.1 L32/P6.2 L33/P6.3 GS-BK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GS-K TS-K 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Pad No. Input/ Output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Function
Output LCD segment/common signal output pins. Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output LCD segment/common signal output Output pins. Output Can function as output ports by the Output mask option. Output Output Output Output
1-10
MSM64164C User's Manual Chapter 1 Overview Table 1-2 Pin Description (Secondary Functions) 1
Pin No. Classification External interrupt Pin name P0.0 P0.1 P0.2 P0.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 Capture trigger Serial port P0.0 P0.1 P3.3 GS-BK 77 78 79 80 18 19 20 21 22 23 24 25 26 27 28 29 77 78 25 GS-K TS-K 75 76 77 78 16 17 18 19 20 21 22 23 24 25 26 27 75 76 23 Pad No. Input/ Output 77 78 79 80 18 19 20 21 22 23 24 25 26 27 28 29 77 78 25 Input Input Secondary function: Trigger input pin of the capture circuit. Secondary function: Assigned to data input (SIN) of the serial port. Input Secondary function: An external interrupt input pin. Can receive interrupt by level change. Input Function Secondary function: An external interrupt input pin. Can receive interrupt by level change.
P4.0
26
24
26
Output Secondary function: Assigned to data output (SOUT) of the serial port. Output Secondary function: Assigned to ready output (SPR) of the serial port. Input/ Output Secondary function: Assigned to clock input/output (SCLK) of the serial port. Secondary function: Monitor output pin of the RC oscillation clock for the system clock and the RC oscillation clock for the A/D converter.
P4.1
27
25
27
P4.2
28
26
28
RC oscillation monitor
P4.3
29
27
29
Input
1-11
MSM64164C User's Manual Chapter 1 Overview 1.5.2 Unused Pin Description Table 1-3 shows processing of unused pins.
Table 1-3 Processing of Unused Pins
Pin OSC1 OSC2 TST1, TST2 P0.0 to P0.3 P1.0 to P1.3 P2.0 to P2.3 Open Open Open "L" level, "H" level or open (depends on input mode selection) Open At input: "L" level, "H" level or open (depends on input mode selection) At output: Open P3.0 to P3.3 At input: "L" level, "H" level or open (depends on input mode selection) At output: Open P4.0 to P4.3 At input: "L" level, "H" level or open (depends on input mode selection) At output: Open BD RT0 CRT0 RS0 CS0 IN0 RT1 RS1 CS1 IN1 L0 to L33 Open Open Open Open Open Open Open Open Open Open Open Recommended pin connection
1-12
MSM64164C User's Manual Chapter 1 Overview 1.6 Basic Timing 1 The MSM64164C generates a system clock (CLK) by one of two methods, a 32.768 kHz crystal oscillator or a 400 kHz RC oscillator. A phase of CLK correspondes with a phase of XT or OSC1. Each instruction is processed/executed between one machine cycle (minimum) and five machine cycles (maximum). One machine cycle consists of three states S1 to S3. One state is a period from the falling edge of CLK to the next falling edge. The S1 state of the first machine cycle (M1) of an instruction is M1*S1. Figure 1-5 shows the relationship among system clock (CLK), the three states (S1, S2 and S3) and machine cycles.
M1 Machine cycles
M2
M3
States
S1
S2
S3
S1
S2
S3
S1
S2
S3
CLK
M1 * S1
Figure 1-5 Machine Cycle Definition
1-13
MSM64164C User's Manual Chapter 1 Overview
1-14
Chapter 2
2
CPU
MSM64164C User's Manual Chapter 2 CPU
Chapter 2 CPU
2.1 Overview 2 The instruction set of the MSM64164C is composed of 148 different instructions that contain byte operations. The address space of the MSM64164C is divided into 8-bit width program memory area and a 4-bit width data memory area. Program data and 32-byte test data are assigned to the program memory area inside the chip. The data memory area has 256-nibble RAM in Bank 7 and the special function registers (SFRs) in Bank 0. Stacks for subroutines and interrupts are placed in the 128 nibbles from address 780H to address 7FFH in Bank 7 by the stack pointer. Figure 2-1 shows each register and memory space.
Data memory 7FFH BANK7 RAM 256N SP 780H 700H PC
Program memory Test data area FFFH FE0H FDFH
Program ROM BSR X H 100H BANK0 SFR 80H 00H C B Y L 03EH A Interrupt area CZP area 020H 010H 000H
Figure 2-1 Registers and Memory Space
Notes: (1) Banks in data memory can be specified by the contents of the bank select registers (BSR0 and BSR1) and the state of the bank control flags (BCF and BEF). (2) The 32 bytes of address 0FE0H to 0FFFH in the program memory are for a factory test data area and cannot be used for a program data area.
2-1
MSM64164C User's Manual Chapter 2 CPU 2.2 Layout of Registers Figure 2-2 shows the layout of registers of the MSM64164C.
3 B register
0
3 A register (accumulator)
0
11 Program counter (PC)
0
BA register pair
3 H register
0
3 L register
0
7 1
6 Stack pointer (SP)
1
0 1
HL register pair "1" fixed 3 X register XY register pair 0 3 Y register 0 C C (carry flag) "1" fixed
3 BEF
2
1 BSR1
0
3 BCF
2
1 BSR0
0
Bank select register (BSR)
Figure 2-2 Register Layout of MSM64164C
2-2
MSM64164C User's Manual Chapter 2 CPU 2.2.1 Registers A, B, H, L, X and Y The A register (accumulator) is a central register of each operation processing. There are five working registers of B, H, L, X and Y. The B register combined with the A register plays a central role for processing byte data. H and L registers and X and Y registers are used for indirect addressing of data memory and for working registers of byte processing when they are used in pair. Figure 2-3 shows the possible combination of data transfer among each register and data memory. (a) 4-bit transfer
nX-4/20 Data memory H L Md
2
B
A
M (HL)
X
Y
M (XY)
(b) 8-bit transfer
nX-4/20 Data memory H L Mbd
B
A
Mb (HL)
X
Y
Mb (XY)
Note: , : data transfer instruction : data exchange instruction Figure 2-3 Combination of Data Transfer among Registers
Here, "M" refers to data memory, index "d" refers to direct addressing mode, "(HL)" and "(XY)" refer to indirect addressing mode and "b" refers to byte data. The arrow indicates the data transfer direction. When an interrupt is generated, the register pairs of BA and HL are automatically saved to the stack.
2-3
MSM64164C User's Manual Chapter 2 CPU 2.2.2 Program Counter (PC) This is a counter of 12 bits and can select a program area of internal 4K bytes.
2.2.3 Stack Pointer (SP) The stack pointer (SP) is a register to indicate the top address of the stack assigned from 7EH to 7FH on data memory bank 0. SP is a 6-bit byte-processing-only up/down counter in which the lowest and the highest bits are fixed as "1". SP is counted down when data was saved to the stack and is counted up when data was returned from the stack. At system reset, SP becomes "0FFH" and the stack addresses become 0FFH and 0FEH in Bank 7. Please use a byte processing instruction for modification and read-out of the contents of SP. 4-bit processing instructions cannot read/write the contents of SP. Bits 0 and 7 of SP are ignored at data write instructions and "1" is always read out by data read instructions.
(BANK0) 7FH SP 1 1 1 1 1 7EH 0 1 1 Address 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH 0F9H 0F8H 0F7H
Stack (BANK7)
7 Stack address 1
6 1
5 1
4 1
3 1
2 0
1 1
0 1/0
Figure 2-4 Relation between Stack Pointer (SP) and Stack Address
2.2.4 Carry Flag (C) This is a one-bit flag and is loaded with a carry at the add instruction and is loaded with a borrow at the subtraction instruction. When an interrupt is generated, it is automatically saved to a stack.
2-4
MSM64164C User's Manual Chapter 2 CPU 2.3 Memory Space 2.3.1 Program Memory Space The program memory space is a memory area for program data, the interrupt area, the CZP area, the start address area and the test data area. The data length is 8 bits and is assigned from address 0 to address 4095. 2
FFFH FDFH
Test data area
32B
4096B 03EH 020H 010H 000H Interrupt area CZP area Start address area Note: "B" means 8 bits. 8 Bits 30B 16B
Figure 2-5 Program Memory Address Space
The address space of program memory is shown in Figure 2-5. Address 0H is the start address of the instruction execution at system reset. The "CZP area" from address 10H to 1FH is the start address range of a CZP subroutine of one byte call instruction and maximum of 8 instructions can be placed. The interrupt area is assigned from address 020H to 03DH. 32 bytes from address 0FE0 to 0FFF are a test data area and cannot be used as a program memory area. For details of interrupts, refer to Chapter 4 "Interrupt" and related chapters for peripheral functions.
2-5
MSM64164C User's Manual Chapter 2 CPU 2.3.2 Data Memory Space 2.3.2.1 Data Memory Space The data memory space is assigned data memory and special function registers (SFRs) and is located in a different address space from the program memory space. The data length is 4 bits. The data memory space uses two bank areas with 256 nibbles as one bank unit; one for the SFR area of Bank 0; the other for the data/stack area from address 700H to address 7FF in Bank 7.
7FFH BANK 7 6FFH RAM area Data/stack area 128N 256N Data area 128N
5FFH Access disabled area 4FFH (address) 3FFH 07FH 07EH 2FFH 07DH MIEF 07CH 1FFH 128N Other SFR areas Stack pointer HALT BANK 0
0FFH 07FH 000H BANK 0 SFR area 4 Bits 000H 4 Bits Note: "N" means 4 bits.
Figure 2-6 Data Memory Address Space
Figure 2-6 shows the address space of data memory. The "stack area" is a data-escape area used by subroutines and interrupts and is valid up to maximum 128 N in the direction toward lower addresses starting from the highest address of 7FFH of data memory. Special function registers (SFRs) are assigned from address 07FH in Bank 0 in the direction toward lower addresses. For addressing mode of the data memory space, the upper 3 bits of the 11 bits of the data memory address can be determined by specifying the bank while the lower 8 bits are determined by either the HL indirect addressing mode, the XY indirect addressing mode or the direct addressing mode. However, addresses 0H to 7FH of Bank 0 are an exception and if this area is selected by setting the bank common flag (BCF) to 1 in direct addressing mode, Bank 0 is always selected unconditionally. Bank selection is ignored for this case.
2-6
MSM64164C User's Manual Chapter 2 CPU 2.3.2.2 Bank Selection of Data Memory Bank selection in data memory can be performed by the bank select registers (BSR0 and BSR1), the bank common flag (BCF) and the bank enable flag (BEF). These registers and flags can be saved and resorted to the stack altogether by the "PUSH BSR" and "POP BSR" instructions. The HL indirect addressing mode, the XY indirect addressing mode, the direct addressing mode and the stack indirect addressing mode are available for intra-bank addressing in data memory. How each bank can be selected depends on the above mode. Table 2-1 shows the functions of BCF and BEF. As shown in this table, the bank can be selected by BCF, BEF and addressing mode. "BSR0" and "BSR1" in the table indicate that a bank can be selected by BSR0 and BSR1, respectively. In direct addressing mode, Bank 0 can be selected unconditionally only when BCF = 1 and the addresses are specified as 0 to 7FH. Table 2-2 shows the correspondence between the contents of BSR0 and BSR1 and the bank number.
2
Table 2-1 Relation between BCF, BEF and Bank Specification by Addressing Mode
HL indirect addressing BSR0 BSR0 BSR0 XY indirect addressing BSR0 BSR1 BSR0 BSR0 BSR1 * When addresses in bank are 0 to 7FH: * When addresses in bank are 80 to FFH:BSR0 1 1 BSR0 BSR1 * When addresses in bank are 0 to 7FH: * When addresses in bank are 80 to FFH:BSR1 SP indirect addressing
BCF 0 0 1
BEF 0 1 0
Direct addressing
Table 2-2 Correspondence between Contents of BSR0, BSR1 and Bank Number
BSR0, BSR1 0 1 2 3 Bank number BANK0 BANK7 BANK0 BANK7 BSR0, BSR1 4 5 6 7 Bank number BANK0 BANK7 BANK0 BANK7
2-7
MSM64164C User's Manual Chapter 2 CPU 2.3.2.3 Addressing Modes of Data Memory (1) HL indirect addressing mode Addresses within a bank can be specified by the HL register pair.
H register L register
H3
H2
H1
H0
L3
L2
L1
L0
Bank specification
10 Data memory address
9
8
7 H3
6 H2
5 H1
4 H0
3 L3
2 L2
1 L1
0 L0
Figure 2-7 Data Memory Address of HL Indirect Addressing
(2) XY indirect addressing mode Addresses within a bank can be specified by the XY register pair.
X register
Y register
X3
X2
X1
X0
Y3
Y2
Y1
Y0
Bank specification
10 Data memory address
9
8
7 X3
6 X2
5 X1
4 X0
3 Y3
2 Y2
1 Y1
0 Y0
Figure 2-8 Data Memory Address of XY Indirect Addressing
2-8
MSM64164C User's Manual Chapter 2 CPU (3) Direct addressing mode Addresses in a bank can be specified by 8-bit immediate data contained in the instruction code.
Immediate data
2
m7
m6
m5
m4
m3
m2
m1
m0
Bank specification
10 Data memory address
9
8
7 m7
6 m6
5 m5
4 m4
3 m3
2 m2
1 m1
0 m0
Figure 2-9 Data Memory Address of Direct Addressing
(4) Stack pointer indirect addressing mode Addresses within Bank 7 can be specified by the stack pointer (SP). This mode is used when manipulating stacks such as the "PUSH" and "POP" instructions and subroutine call, return instructions and interrupts. In this mode, Bit 0 of the address is not valid as data are always handled in 8 bits (two nibbles). Although SP is an 8 bit register, the highest and the lowest bits always are fixed as "1" and the remaining 6 bits function as an up/down counter.
Stack Pointer
1
SP6
SP5
SP4
SP3
SP2
SP1
1
10 Data memory address 1
9 1
8 1
7 1
6 SP6
5 SP5
4 SP4
3 SP3
2 SP2
1 SP1
0 1
0
Figure 2-10 Data Memory Address by Stack Pointer Indirect Addressing
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MSM64164C User's Manual Chapter 2 CPU
2-10
Chapter 3
3
CPU Control Functions
MSM64164C User's Manual Chapter 3 CPU Control Functions
Chapter 3 CPU Control Functions
3.1 Overview The MSM64164C has halt mode besides operation mode. Operation status can be classified as follows including system reset mode: * Normal operation mode * System reset mode * Halt mode Figure 3-1 shows transition among each state.
3
Normal operation mode
HLT = "1" Halt mode Interrupt generated RESET = "L"
RESET = "L"
RESET = "H"
System reset mode
Power-on detected Crystal oscillation halt detected
Figure 3-1 Operation Transition Diagram
Normal operation mode is a state that the CPU executes instructions successively. System reset mode is a state starting when the CPU begins system reset processing until each register and each pin are initialized to start execution of the instruction. Halt mode is a state that the CPU repeats fetching the next instruction only and suspends the execution of instruction. Count-up to the PC is not performed in halt mode. Although the execution of the instruction is suspended in halt mode, internal peripheral functions continue to operate. Transition to this state begins by setting the HLT flag to "1". Halt mode does not influence the functions of ports and peripheral functions.
3-1
MSM64164C User's Manual Chapter 3 CPU Control Functions 3.2 System Reset Function 3.2.1 System Reset Operation by RESET Input Pin System reset mode is started when either power is turned on, crystal oscillation stops or the RESET pin becomes "L" level. In system reset mode, the following take place: (1) The CPU is initialized. (2) The power supply VSSL for the crystal oscillation circuit and the logic circuit is set to the VSS1 or VSS2 voltage level. VSS1 is chosen if 1.5 V spec. is selected and VSS2 is chosen if 3.0 V spec. is selected. At 0.5 second after crystal oscillation starts, VSSL is switched to a constant voltage level which is output of the power supply generation circuit for logic (VR). (3) The power supply generation circuit for logic (VR) is activated. (4) The output from the LCD driver is turned off at the VDD level. At about 63 ms after the crystal oscillation starts, waveforms are output to the LCD driver. (5) All the special function registers (SFRs) are initialized. After the system reset processing, the execution of an instruction is started from address 000H. Figures 3-2 and 3-3 show the system reset generation circuit and each signal at system reset.
VDD 2 k (Typ.)
RESET VSS1/VSS2 Power ON detection S 8 Hz R Q
RESET0 (Time base counter reset) RESETS (System reset)
VSS1/VSS2 Time base clock (32.768 kHz) 1 Hz (from the time base counter)
S R
Q
Detection of oscillation halt
CNT VSSL (Logic power supply control)
Figure 3-2 System Reset Generation Circuit
3-2
RESET 0 (Time base counter reset) XTAL oscillation output
VDD Logic power supply VSSL
RESETS (System reset) VDD LCD driver output
,,, ,,,
MSM64164C User's Manual Chapter 3 CPU Control Functions
32.768 kHz 0.5 sec VSS1 or VSS2 1.3 V level 1.5 V or 3.0 V 63 msec (OFF) ON waveform CPU start
3
Figure 3-3 Each Signal at System Reset Generation
3-3
MSM64164C User's Manual Chapter 3 CPU Control Functions 3.2.2 State at System Reset Table 3-2 shows the state of the registers after system reset.
Table 3-2 (a) Initial Values at System Reset
Value at system reset 000H 0H 0H 0 00H 00H 0FFH 0H 0H 0 0 0H 0H 0H 0H 0H Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled Port 21 control register (P21CON) 0H Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled Port 22 control register (P22CON) 0H Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled Port 23 control register (P23CON) 0H Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled
Register/Flag Program counter (PC) A register (A) B register (B) Carry flag (C) HL register pair (HL) XY register pair (XY) Stack pointer (SP) Bank select register 0 (BSR0) Bank select register 1 (BSR1) Bank common flag (BCF) Bank enable flag (BEF) Port 1 register (P1) Port 2 register (P2) Port 3 register (P3) Port 4 register (P4) Port 20 control register (P20CON)
Note
3-4
MSM64164C User's Manual Chapter 3 CPU Control Functions Table 3-2 (b) Initial Values at System Reset
Value at system reset 0H
Register/Flag Port 30 control register (P30CON)
Note Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled
3
Port 31 control register (P31CON)
0H
Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled
Port 32 control register (P32CON)
0H
Input mode, input with pull-up/pull-down resistance, 64 Hz sampling, interrupt disabled
Port 33 control register (P33CON)
0H
Input mode, input with pull-up/pull-down resistance, interrupt disabled
Port 40 control register (P40CON)
0H
Input mode, input with pull-up/pull-down resistance, interrupt disabled
Port 41 control register (P41CON)
0H
Input mode, input with pull-up/pull-down resistance, interrupt disabled
Port 42 control register (P42CON)
0H
Input mode, input with pull-up/pull-down resistance, interrupt disabled
Port 43 control register (P43CON)
0H
Input mode, input with pull-up/pull-down resistance, interrupt disabled
Port 01 control register (P01CON)
8H
P1 CMOS output mode, P0, P2, P3, P4 input with pull-up resistance
Serial port control register (SCON) Serial port buffer lower register (SBUFL) Serial port buffer upper register (SBUFH) Frequency control register (FCON) Buzzer driver control register (BDCON)
0H 0H 0H 0EH 0H
MSB head, internal clock, transfer disabled
Crystal oscillation clock Positive logic output, buzzer disabled, discontinuous sound 1 output
Buzzer frequency control register (BFCON) Capture control register (CAPCON) Capture register 0 (CAPR0) Capture register 1 (CAPR1) Display control register (DSPCON) Display registers 0 to 30 (DSPR0 to 30)
0H 0H 0H 0H 0CH 0H
Output halt Capture 0,1 halt
1/4 duty
3-5
MSM64164C User's Manual Chapter 3 CPU Control Functions Table 3-2 (C) Initial Values at System Reset
Value at system reset 0CH 0H 0H 0H 0H 0H 8H 0H 0H 0H 0CH -- 0EH 0H 0H 0CH 0H 0H 0EH 0EH 0EH Interrupt disabled Interrupt disabled Interrupt disabled Normal operation mode Interrupt disabled Reset the watchdog timer counter VDD-1.3 V level
Register/Flag A/D converter control register 0 (ADCON0) A/D converter control register 1 (ADCON1) A/D converter counter A register 0 (CNTA0) A/D converter counter A register 1 (CNTA1) A/D converter counter A register 2 (CNTA2) A/D converter counter A register 3 (CNTA3) A/D converter counter A register 4 (CNTA4) A/D converter counter B register 0 (CNTB0) A/D converter counter B register 1 (CNTB1) A/D converter counter B register 2 (CNTB2) A/D converter counter B register 3 (CNTB3) Watchdog timer control register (WDTCON) Backup control register (BUPCON) Interrupt request register 0 (IRQ0) Interrupt request register 1 (IRQ1) Interrupt request register 2 (IRQ2) Interrupt enable register 0 (IE0) Interrupt enable register 1 (IE1) Interrupt enable register 2 (IE2) Helt mode register (HALT) Master interrupt enable register (MIEF)
Note Counter A select, RC oscillation halt IN0 clock input mode
Note: System reset has the highest priority over all other processing and all the processes are suspended at system reset. Consequently, there is no guarantee for the contents of RAM that is initialized at system reset.
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MSM64164C User's Manual Chapter 3 CPU Control Functions 3.3 Halt Mode 3.3.1 Halt Mode Register (HALT) This is a special function register (SFR) that controls transition to halt mode. 3 b3 HALT (7DH) (R/W) -----* b2 -----* b1 -----* b0 HLT
Halt mode transition selection flag 0: Normal operation mode (initial value) 1: Halt mode *Reserved bit: "1" is always read out. Not valid for write.
Bit 0: HLT This is a flag to enter halt mode. By setting the HLT flag to "1", the CPU enters halt mode at the first machine cycle of the next instruction.
3.3.2 Operation of Halt Mode When executing an instruction to set the HLT flag to "1", the CPU enters halt mode at the first machine cycle of the next instruction. However, since the condition for the release of halt mode is an interrupt request, the CPU does not enter halt mode in interrupt request state. In halt mode, operation of oscillation and the time base counter is still continued and the CPU halts at fetching state S1 for the next instruction. System reset or an interrupt can release halt mode (reset of the HLT flag). To release halt mode by an interrupt, it is necessary to set the interrupt enable flag to "1" before entering halt mode. Figure 3-4 shows timing to enter halt mode and release timing of halt mode by an interrupt. Execution of instructions after the release of halt mode depends on the status of the master interrupt enable flag (MI). When the MI flag is "1", execution of instructions is resumed after one dummy cycle by an interrupt process routine as shown in Figure 3-4. When the MI flag is "0", execution of instructions is resumed with a dummy cycle after the following address that the halt instruction is placed as shown in Figure 3-5. Note: To release halt mode, it is necessary to set an individual interrupt enable flag to "1" regardless of the state of the MI flag. When halt mode is released while the MI flag is "0", the individual interrupt request flag is set to "1".
3-7
MSM64164C User's Manual Chapter 3 CPU Control Functions
M1 System clock: CLK HLT Interrupt request: INT
LMAD 7DH : M(7DH) A M2 (A = 1H) S3 S1 S2 S3 S1 S1 S1 S1 S2 S3 S1 S2 S3 S1
S1 S2
Halt instruction execution
Halt mode
Dummy cycle
Interrupt routine
Figure 3-4 Timing of Halt Mode Set and Halt Mode Reset by Interrupt (when the MI flag = 1)
M1 System clock: CLK HLT Interrupt request: INT
LMAD 7DH : M(7DH) A M2 (A = 1H) S3 S1 S2 S3 S1 S1 S1 S1 S2 S3 S1 S2 S3 S1
S1 S2
Halt instruction execution
Halt mode
Dummy cycle Execution of instruction at next address of halt instruction
Figure 3-5 Timing of Halt Mode Set and Halt Mode Reset by Interrupt (when the MI flag = 0)
3-8
Chapter 4
4
Interrupt (INTC)
MSM64164C User's Manual Chapter 4 Interrupt (INTC)
Chapter 4 Interrupt (INTC)
4.1 Overview The MSM64164C has ten interrupt causes (10 vector addresses), two of which are external interrupts from ports and 8 are internal interrupts. Of the ten interrupt causes, only the watchdog interrupt cannot be disabled (non-maskable interrupt) and other 9 interrupts are controlled by the master interrupt enable flag (MI) and each interrupt enable register (IE0, IE1 and IE2) for enabling/disabling interrupts. When an interrupt condition is met, CPU branches to a vector address corresponding to the interrupt cause. Table 4-1 shows the list of interrupt causes and vector address and Figure 4-1 shows the interrupt control equivalent circuit. Table 4-1 List of Interrupt Causes 4
No. 1 2 3 4 5 6 7 8 9 10
Interrupt cause Watchdog timer interrupt External 0 interrupt (P2, P3, P4) Serial port interrupt External 1 interrupt (P0) A/D converter interrupt 256 Hz interrupt 32 Hz interrupt 16 Hz interrupt 1 Hz interrupt 0.1 Hz interrupt
Mnemonic WDTINT XI0INT SIOINT XI1INT ADINT 256HzINT 32HzINT 16HzINT 1HzINT 01HzINT
Vector address 03BH 038H 035H 032H 02FH 02CH 029H 026H 023H 020H
When two interrupt causes are generated simultaneously, the interrupt with the higher vector address (WDTINT has the highest priority) is given the priority and is executed accordingly. For details of each interrupt operation, refer to Chapter 6 "Time Base Counter," Chapter 7 "Ports," Chapter 8 "Serial Port," and Chapter 12 "A/D Converter".
(Notes) The interrupt requests which are generated in the following cases are temporarily held. 1) As a result which executed an instruction with skip, when the skip condition is established. (The skip action expends the same tine as the executive machine cycle of the instruction to be skipped. For this reason, the interrupt requests are held during the same as the executive machine cycle of the instruction to be skipped.) 2) When LAI and LLI instructions (vertical stack instruction) are executed. 3) When ADCS and SUBCS instructions are executed. The interrupt requests which are temporarily held in the abovementioned cases are received after the execution of the instructions is finished if the next coming instructions are not fitted to the aforementioned conditions.
4-1
MSM64164C User's Manual Chapter 4 Interrupt (INTC)
IRQ0 XI0INT
IRQ0.0 QXI0 IE0.0
IE0
EXI0
SIOINT
IRQ0.1
QSIO
IE0.1
ESIO
XI1INT
IRQ0.2
QXI1
IE0.2
EXI1
ADINT
IRQ0.3
QAD
IE0.3
EAD
IRQ1 256HzINT
IRQ1.0 Q256Hz IE1.0
IE1
E256Hz
Interrupt vector address
Priority encoder
32HzINT
IRQ1.1
Q32Hz
IE1.1
E32Hz
Interrupt request
16HzINT
IRQ1.2
Q16Hz
IE1.2
E16Hz
1HzINT
IRQ1.3
Q1Hz
IE1.3
E1Hz
IRQ2 01HzINT
IRQ2.0 Q01Hz IE2.0
IE2
E01Hz
WDTINT
IRQ2.1
QWDT
MI
Figure 4-1 Interrupt Control Equivalent Circuit
4-2
MSM64164C User's Manual Chapter 4 Interrupt (INTC) 4.2 Interrupt Sequence Transition to interrupt processing is performed by generating an individual interrupt cause while the MI flag is set to "1". An interrupt transition cycle is equivalent to 5 machine cycles and the following are executed: (1) (2) (3) (4) The MI flag is reset to "0". The contents of PC, A, B, H and L registers and the carry flag (C) are saved to stack. The stack pointer (SP) is decremented by 4 (SP SP-4). The program counter (PC) is loaded with the head address of the vector address. At the same time, the interrupt request flag for that interrupt is reset. 4
Figure 4-1 shows the contents of the stack after the generation of an interrupt.
BANK 7
3 SP location before interrupt 0FFH 0FEH 0FDH -1 0FCH 0FBH -2 0FAH 0F9H -3 0F8H SP location after interrupt 0F7H -4 0F6H L A H PC3 to B PC0 C PC11 PC7 2 1 to to 1 1 0 1 PC8 PC4
Figure 4-2 Contents of Stack after Interrupt Generation
Return from the interrupt routine is performed by the "RTI" instruction. The return cycle is equivalent to 5 machine cycles and the following are carried out: (1) (2) (3) The contents of PC, A, B, H and L registers and the carry flag (C) are restored from the stack. The stack pointer (SP) is incremented by 4 (SP SP+4). The MI flag is set to "1".
4-3
MSM64164C User's Manual Chapter 4 Interrupt (INTC) 4.3 Interrupt Control Registers 4.3.1 Interrupt Request Registers (IRQ0, IRQ1 and IRQ2) Each interrupt request register (IRQ0, IRQ1 and IRQ2) is composed of a 4-bit register. When an interrupt request is generated, a corresponding bit is set to "1" in the S1 state of the first machine cycle. When an interrupt is enabled by the interrupt enable register (IE0 to 2), the interrupt is requested to the CPU. The watch dog timer interrupt does not have an interrupt mask function caused by the interrupt enable register. By writing "1" to the interrupt request register, it is possible to generate a soft interrupt. When an interrupt is received, the corresponding bits of IRQ0, IRQ1 and IRQ2 are reset to "0" by hardware. IRQ0, IRQ1 and IRQ2 are initialized to 0H at system reset.
b3 IRQ0 (34H) (R/W) QAD
b2 QXI1
b1 QSIO
b0 QXI0
A/D converter interrupt request flag 0: No request (initial value) 1: Request External 1 interrupt request flag 0: No request (initial value) 1: Request Serial port interrupt request flag 0: No request (initial value) 1: Request External 0 interrupt request flag 0: No request (initial value) 1: Request
Bit 3: QAD This bit is set to "1" by the counter overflow signal of the A/D converter. Bit 2: QXI1 This bit is set to "1" by the change of input level of P0.0 to P0.3. Bit 1: QSIO This bit is set to "1" when data transfer of 8 bits of the serial port is finished. Bit 0: QXI0 This bit is set to "1" by the change of input level of P2.0 to P.2.3, P3.0 to P3.3 and P4.0 to P4.3.
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MSM64164C User's Manual Chapter 4 Interrupt (INTC)
b3 IRQ1 (35H) (R/W) Q1Hz
b2 Q16Hz
b1 Q32Hz
b0 Q256Hz
1 Hz interrupt request flag 0: No request (initial value) 1: Request 16 Hz interrupt request flag 0: No request (initial value) 1: Request 32 Hz interrupt request flag 0: No request (initial value) 1: Request 256 Hz interrupt request flag 0: No request (initial value) 1: Request
4
Bit 3: Q1Hz This bit is set to "1" by falling of the 1 Hz output of the time base counter. Bit 2: Q16Hz This bit is set to "1" by falling of the 16 Hz output of the time base counter. Bit 1: Q32Hz This bit is set to "1" by falling of the 32 Hz output of the time base counter. Bit 0: Q256Hz This bit is set to "1" by falling of the 256 Hz output of the time base counter.
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MSM64164C User's Manual Chapter 4 Interrupt (INTC)
b3 IRQ2 (33H) (R/W) Watchdog timer interrupt request flag 0: No request (initial value) 1: Request 0.1 Hz interrupt request flag 0: No request (initial value) 1: Request -----*
b2 -----*
b1 QWDT
b0 Q01Hz
*Reserved bit: "1" is always read out. Not valid for write.
Bit 1: QWDT This bit is set to "1" by overflow of the watchdog timer. Interrupt disable cannot be allowed by the interrupt enable register. Bit 0: Q01Hz This bit is set to "1" by falling of the 0.1 Hz output of the time base counter.
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MSM64164C User's Manual Chapter 4 Interrupt (INTC) 4.3.2 Interrupt Enable Registers (IE0, IE1 and IE2) Each interrupt enable register (IE0, IE1 and IE2) is composed of a 4-bit register and determines whether a request is sent to the CPU or not by AND with a corresponding bit of the interrupt request registers (IRQ0, IRQ1 and IRQ2). When multiple interrupts are requested to the CPU, those interrupts with higher priority (higher vector address) as shown in Table 4-1 are processed first and the interrupts with lower priority are held up during that time. Although the master interrupt enable flag (MI) is cleared to "0" during an interrupt transition cycle, each bit of IE0 to IE2 is not cleared. The held interrupt request remains held up so long as the MI flag is not set to "1" during the processing of the accepted interrupt request. The interrupt processing is ended by the RTI instruction. When the MI flag is automatically set to "1", the held interrupt request is accepted. The interrupt enable registers (IE0 to 2) can be rewritten only when the master interrupt enable flag (MI) is reset to "0".
b3 IE0 (30H) (R/W) EAD b2 EXI1 b1 ESIO b0 EXI0
4
A/D converter interrupt enable flag 0: Disabled (initial value) 1: Enabled External 1 interrupt enable flag 0: Disabled (initial value) 1: Enabled Serial port interrupt enable flag 0: Disabled (initial value) 1: Enabled External 0 interrupt enable flag 0: Disabled (initial value) 1: Enabled
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MSM64164C User's Manual Chapter 4 Interrupt (INTC)
b3 IE1 (31H) (R/W) E1Hz
b2 E16Hz
b1 E32Hz
b0 E256Hz
1 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 16 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 32 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 256 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled
b3 IE2 (32H) (R/W) -----*
b2 -----*
b1 -----*
b0 E01Hz
0.1 Hz interrupt enable flag 0: Disabled (initial value) 1: Request *Reserved bit: "1" is always read out. Not valid for write.
4-8
MSM64164C User's Manual Chapter 4 Interrupt (INTC) 4.3.3 Master Interrupt Enable Register (MIEF) The MI flag of the master interrupt enable register (MIEF) is to control disabling/enabling of all the interrupts excepting watchdog timer interrupt. When set to "1", interrupt is enabled and when set to "0", interrupt is disabled. When an interrupt is received, the MI flag is reset to "0" during the interrupt transition cycle and is set to "1" by executing the RTI instruction which is a return instruction from the interrupt process routine. It is also possible to do multiple interrupt processing by setting this flag to "1" during an interrupt process routine.
4
b3 MIEF (7CH) (R/W) Master interrupt enable flag 0: Interrupt disabled (initial value) 1: Interrupt enabled -----*
b2 -----*
b1 -----*
b0 MI
*Reserved bit: "1" is always read out. Not valid for write.
Table 4-2 shows the list of interrupt-related registers.
Table 4-2 List of Interrupt Related Registers
Register name Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 2 Interrupt request register 0 Interrupt request register 1 Master interrupt enable register
Symbol IE0 IE1 IE2 IRQ2 IRQ0 IRQ1 MIEF
Address Read/Write Byte access 30H 31H 32H 33H 34H 35H 7CH R/W R/W R/W R/W R/W R/W R/W Yes Yes Yes No
Value at system reset 0H 0H 0EH 0CH 0H 0H 0EH
4-9
MSM64164C User's Manual Chapter 4 Interrupt (INTC)
4-10
Chapter 5
5
Clock Generation Circuit (2CLK)
MSM64164C User's Manual Chapter 5 Clock Generation Circuit (2CLK)
Chapter 5 Clock Generation Circuit (2CLK)
5.1 Overview The clock generation circuit (2CLK) of the MSM64164C is composed of a 32.768 kHz crystal oscillation circuit, a 400 kHz RC oscillation circuit and a clock control part. It generates the system clock (CLK) and the time base clock (32.768 kHz). The system clock is the basic operation clock of the CPU while the time base clock is the basic operation clock of the time base counter and the buzzer driver. By the contents of the frequency control register (FCON) the system clock can be switched at between 32.768 kHz which is output of the crystal oscillation circuit and 400 kHz which is output of the RC oscillation circuit. Note: The oscillation frequency of the RC oscillation circuit varies depending on the value of external resistance (ROS), operating power supply voltage (VDD) and ambient temperatures (Ta). In this manual, the output of the RC oscillation circuit is taken as 400 kHz for convenience. 5
5.2 Layout of Clock Generation Circuit Figure 5-1 shows layout of the clock generation circuit.
MSM64164C
VDD 32.768 kHz crystal oscillation circuit Mask option CG XT 32.768 kHz crystal XT OSC2 VDD 400 kHz: To port 4.3 ROS COS Clock switch control 400 kHz RC oscillation circuit VDD CD Rf 32.768 kHz 400 kHz VSSL Time base clock (32.768 kHz)
MPX
System clock (CLK)
OSC1 VSS FCON Write FCON VSS1/VSS2 1 Internal data bus
Figure 5-1 Layout of Clock Generation Circuit
5-1
MSM64164C User's Manual Chapter 5 Clock Generation Circuit (2CLK) 5.3 Operation of Clock Generation Circuit The 32.768 kHz crystal oscillation circuit oscillates by installing a 32.768 kHz crystal externally. When micro-tuning the 32.768 kHz frequency by an external capacitor, the builtin capacitance (CG) can be cut off by selecting a mask option. The 400 kHz oscillation circuit oscillates by installing a resistance (ROS) externally. The RC oscillation circuit operates only when the system clock is set to the 400 kHz RC oscillation clock or when it is set to CPU clock output mode for high speed system clock by test functions. Otherwise it halts oscillation. For details of the test functions, refer to Chapter 15 "Test Circuit". Selection of the system clock is performed by the frequency control register (FCON). When Bit 0 of FCON (CPUCLK) is reset to "0", output of the crystal oscillation circuit (32.768 kHz) becomes the system clock and when CPUCLK is set to "1", output of the RC oscillation circuit (400 kHz) becomes the system clock. Even though the 400 kHz oscillation circuit is selected, the crystal oscillation circuit is not halted. When the crystal oscillation circuit is chosen as the system clock, oscillation of the RC oscillation circuit is halted and power consumption of the RC oscillation circuit becomes "0". Consequently, it is possible to lower power consumption by writing software in such a way that output of the RC oscillation circuit is selected (CPUCLK = 1) only when high speed operation is needed and that output of the crystal oscillation circuit (CPUCLK = 0) is selected otherwise. Since the OSC1 pin is pulled up to VDD when the 400 kHz RC oscillation circuit is not selected, leave OSC1/OSC2 open when not using output from the RC oscillation circuit (400 kHz).
5.4 Frequency Control Register (FCON) The frequency control register (FCON) is a 4-bit special function register (SFR) to select a system clock. b3 FCON (09H) (R/W) -----* b2 -----* b1 -----* b0 CPUCLK
System clock selection 0: Crystal oscillation output (initial value) 1: 400 kHz RC oscillation output *Reserved bit: "1" is always read out. Not valid for write.
Bit 0: CPUCLK This bit is to select a system clock. At system reset, it is reset to "0" and the crystal oscillation output is selected.
5-2
MSM64164C User's Manual Chapter 5 Clock Generation Circuit (2CLK) 5.5 System Clock Switch Timing When the CPUCLK bit of the frequency control register (FCON) is set to "1", the system clock is switched from crystal oscillation output (32.768 kHz) to RC oscillation output (400 kHz) and the internal logic power supply is switched from the VSSL level to the applied power supply voltage level (VSS1 or VSS2) simultaneously. This switching is made in order to get a larger high-speed margin by increasing the internal voltage. It takes 1 ms or more until the internal logic power supply reaches the power supply level (VSS). For high-speed clock operaiton, do programming according to the following procedure using the backup control register described in Chapter 14 (refer to Figure 5-2). 5 (1) Set the bit 0 (BUPF) of the backup control register (BUPCON) to "1" before switching to high-speed clock, and switch the internal logic voltage to the power supply voltage level (VSS1 or VSS2). (2) 1 ms or more later, set the CPUCLK bit of the frequency control register (FCON) to "1", and switch the system clock from crystal oscillation output (32.768 kHz) to RC oscillation output (400 kHz) *Program example SMBD 37H,0 ; Set BUPF to "1" [WAIT 1 ms] ; Wait 1 ms SMBD 09H,0 ; Set CPUCLK to "1". (3) After switching the system clock to the high-speed clock mode, BUPF may be reset to "0" at any timing. Take care of the status of BUPF when the system clock returns to the lowspeed clock mode. It is impossible to get a low current consumption without resetting BUPF to "0". Figure 5-2 shows the system clock switch timing and the internal logic power supply.
(1) (3) BUPF 1 ms min. CPUCLK (2)
System clock
32.768 kHz
400 kHz
32.768 kHz 0 to 30 msec
0.5 to 1 clock of 400 kHz Internal logic voltage VDD 1.3 V (Typ.) VSSL VSS1 or VSS2
Figure 5-2 System Clock Switch Timing
5-3
MSM64164C User's Manual Chapter 5 Clock Generation Circuit (2CLK) Table 5-1 shows the clock generation circuit related pins. Table 5-2 shows typical values of oscillation frequencies of the RC oscillation circuit. Table 5-1 Clock Generation Circuit-Related Pins Pin No. Input/ GS-K Pad No. Note Output GS-BK TS-K 69 67 69 Input Low speed side clock oscillation input pin: This pin is connected to the crystal oscillator (32.768 kHz). 68 66 68 Output Low speed side clock oscillation output pin: This pin is connected to the crystal oscillator (32.768 kHz). 66 64 66 Input High speed side clock oscillation pin: This pin is connected to the external 65 63 65 Output resistance (ROS) for oscillation.
Pin name XT
XT
OSC1 OSC2
Table 5-2 Typical Values of Oscillating Frequencies of RC Oscillation Circuit (Ta = 25C)
VDD (V) 3.0 1.5
ROS (kW) 100 300
fOSC (kHz) 400 220
5-4
Chapter 6
6
Time Base Counter (TBC)
MSM64164C User's Manual Chapter 6 Time Base Counter (TBC)
Chapter 6 Time Base Counter (TBC)
6.1 Overview The MSM64164C has a built-in time base counter (TBC) that generates clocks to be supplied to internal peripheral circuits. The time base counter is composed of 15 binary counters and a 1/10 frequency dividing circuit. The count clock of the time base is supplied with the oscillation clock (32.768 kHz) of the crystal oscillation circuit. Output of the time base counter is used for the buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, sampling clocks of each port and the capture circuit.
6.2 Layout of Time Base Counter Figure 6-1 shows the layout of the time base counter (TBC).
6
RESET0 (from the system reset circuit)
Write TBCR
Time base clock 32.768 kHz
R 1/211 frequency division
0 1 2 3 4 5 6 7 8 9 10
R 1/2 4 frequency division
11 12 13 14
R 1/10 frequency division
LCD bias circuit Buzzer driver System reset circuit
1 kHz 1 Hz 8 Hz 16 Hz 1 Hz 8 Hz
Read TBCR 1 Hz 2 Hz Internal data 4 Hz bus 8 Hz 16 Hz watchdog timer 0.1 Hz 1 Hz 16 Hz 32 Hz 256 Hz
Interrupt controller
64 Hz input/output port 32 Hz 64 Hz 128 Hz 256 Hz 2 kHz
Capture circuit
Figure 6-1 Layout of Timer Base Counter
6-1
MSM64164C User's Manual Chapter 6 Time Base Counter (TBC) 6.3 Operation of Time Base Counter The time base counter (TBC) starts count-up from 0000H after system reset. Count-up is started by falling of the time base clock (32.768 kHz). 256 Hz/32 Hz/16 Hz/1 Hz/0.1 Hz output of the time base counter is used as the timer base interrupt and a time base interrupt request is generated at falling of each output. The 16 Hz output of the time base counter is output to the watchdog timer. The output of 1 Hz/8 Hz/16 Hz is used by the buzzer driver and various buzzer sounds are output. The 64 Hz output is used as a sampling clock of input ports. The 1 Hz/8 Hz output is input to the system reset circuit and is used to generate reset timing at system reset and to switch a logic power supply. The output of 256 Hz/128 Hz/64 Hz/32 Hz becomes input data for the capture circuit. The output of 1 Hz/2 Hz/4 Hz/8 Hz of the time base counter can be read by the time base counter register (TBCR). When a write operation is performed on TBCR, the counters of 0.1 Hz/1 Hz/2 Hz/4 Hz/8 Hz are reset to "0". Figure 6-2 shows interrupt timing of the time base counter and reset timing by writing to TBCR. Note: Output of 8 Hz to 1 Hz of the time base counter can be read by the time base counter register (TBCR) and they are reset to "0" by writing to TBCR. In this write operation, data to write have no significance. For example, writing by the "LMAD TBCR" instruction does not depend on the contents of the A register at all. When writing to TBCR and resetting 8 Hz to 1 Hz of the time base counter, a time base interrupt is generated when each output is "1". For example, when the 1 Hz output is "1", a 1 Hz interrupt request is generated. When an interrupt is invalidated, please write to TBCR and reset the interrupt request flag (Q1Hz) to "0" after resetting the master interrupt enable flag (MI) or the interrupt enable flag (E1Hz) to "0".
6.4 Time Base Counter Register (TBCR) This register is a 4-bit special function register (SFR) to read 8 Hz to 1 Hz output of the time base counter. When writing, it resets the 8 Hz to 1 Hz output and the 0.1 Hz output.
b3 TBCR (0FH) (R/W) 1Hz
b2 2Hz
b1 4Hz
b0 8Hz
Values of 8 Hz to 1 Hz of the time base counter
6-2
MSM64164C User's Manual Chapter 6 Time Base Counter (TBC)
256 Hz 128 Hz 64 Hz 32 Hz 16 Hz
6
Write TBCR 16 Hz 8 Hz 4 Hz
2 Hz 1 Hz 0.1 Hz
+0 -1/16
1 Reset by "Write TBCR".
seconds
Write TBCR 1 Hz 0.1 Hz 10
+0 -1/16
seconds
Note:
indicates interrupt timing.
Figure 6-2 Time Base Counter Interrupt Timing and Reset Timing by TBCR Writing
6-3
MSM64164C User's Manual Chapter 6 Time Base Counter (TBC)
6-4
Chapter 7
Ports (P0, P1, P2, P3 and P4)
7
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
Chapter 7 Ports (P0, P1, P2, P3 and P4)
7.1 Overview The MSM64164C has one 4-bit input port, three 4-bit input/output ports and one 4-bit output port built-in. Table 7-1 shows the list of functions of each port. For secondary functions of the capture timer, the A/D converter and the serial port, refer to Chapter 10 "Capture Circuit", Chapter 12 "A/D Converter", and Chapter 8 "Serial Port", respectively. Table 7-1 List of Functions of Each Port
Pin No. Pin name P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3/SIN P4.0/SOUT P4.1/SPR P4.2/SCLK P4.3/MON Pad No. GS-BK GS-K TS-K 77 78 79 80 73 74 75 76 18 19 20 21 22 23 24 25 26 27 28 29 75 76 77 78 71 72 73 74 16 17 18 19 20 21 22 23 24 25 26 27 77 78 79 80 73 74 75 76 18 19 20 21 22 23 24 25 26 27 28 29
Input/ Output Input Input Input Input Output Output Output Output
Function
7
4-bit input port (P0): Can select (1) pull-up resistance input, (2) pull-down resistance input or (3) high-impedance input by the port 01 control register (P01CON). As a secondary function, P0.0 to P0.3 are assigned external interrupt functions and P0.0 and P0.1 are assigned a capture trigger function. 4-bit output port (P1): Can select NMOS open drain output or CMOS output by the port 01 control register (P01CON). P1.0 is a large current drive output port.
Input/Output 4-bit input/output port (P2): Selection of (1) pull-up/pull-down resistance input, (2) Input/Output high-impedance input, (3) NMOS open drain output and Input/Output (4) CMOS output by the port 2 control registers 0 to 3 (P20CON to P23CON) is possible. As a secondary Input/Output function, an external interrupt function is assigned. Input/Output 4-bit input/output port (P3): Selection of (1) pull-up/pull-down resistance input, (2) Input/Output high-impedance input, (3) NMOS open drain output and (4) CMOS output by the port 3 control registers 0 to 3 Input/Output (P30CON to P33CON) is possible. As a secondary function, P3.0 to P3.3 are assigned an external interrupt Input/Output function and P3.3 is assigned a serial port function. Input/Output 4-bit input/output port (P4): Selection of (1) pull-up/pull-down resistance input, (2) high-impedance input, (3) NMOS open drain output and Input/Output (4) CMOS output by the port 4 control registers 0 to 3 (P40CON to P43CON) is possible. As a secondary Input/Output function, P4.0 to P4.3 are assigned an external interrupt function, P4.0 to P4.2 are assigned a serial port function and P4.3 is assigned a monitor function of the RC Input/Output oscillation clock for A/D conversion.
7-1
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.2 Port 0 and Port 1 (P0.0 to P0.3 and P1.0 to P1.3) 7.2.1 Layout of Port 0 and Port 1 Port 0 is a 4-bit input only port. Port 0 can be switched to either pull-up resistance input, pulldown resistance input or high-impedance input by the port 01 control register (P01CON). As a secondary function, an external interrupt function is assigned by level change. P0.0 and P0.1 are also assigned as trigger input pins of the capture circuit. For details of the capture circuit, refer to Chapter 10 "Capture Circuit". Port 1 is a 4-bit output only port. Port 1 can be switched to either CMOS output or NMOS open drain output by the port 01 control register (P01CON). Figure 7-1 shows the layout of Port 0 and Port 1.
4
VSS VDD
P0.0 to P0.3 : To A/D conversion circuit P0.0 P0.1 To capture 64 Hz Level change detection XI1INT (External interrupt 1)
P0.2 000 0 P0.3
P0.0 to P0.3
4 4 VSS VDD
Gate control circuit
Read P0
P1.0 to P1.3
4 0
I 4 4 WriteP1 4 P1 4
VSS 0 0 0
C C C C I I I Read P1
4
P0MOD P1MOD PUD To Ports 2 to 4
P01 CON
2
Write P01CON
Internal data bus
Figure 7-1 Layout of Port 0 and Port 1
7-2
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) The power supply for the input circuit of Port 0 and the output circuit of Port 1 is at VDD-VSS level. When connecting Port 0 and Port 1 to equipment operated by a different power supply externally, supply power to the external equipment between the VDD-VSS pins is shown in Figure 7-2. When all the signal levels of all the ports of Port 0, Port 1 and Ports 2 to 4 can be the same as the power supply voltage of the IC, connect the VSS pin to either VSS1 (for 1.5 V spec.) or VSS2 (for 3.0 V spec.).
External equipment P0.0 VDD P0.1 P0.2 P0.3 P1.0 P1.1 VSS P1.2 P1.3
MSM64164C
VDD
7
IC power supply VSS1 or VSS2
VSS
Figure 7-2 Connection of Port 0 and Port 1 to External Equipment with Different Power Supply
7-3
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.2.2 Registers Related to Port 0 and Port 1 (1) Port 0 register (P0) The port 0 register is a 4-bit read only special function register (SFR) to read out the level of each port of Port 0.
b3 P0 (03H) (R) P03 b2 P02 b1 P01 b0 P00
Pin level of each bit of Port 0 0: "L" level 1: "H" level
(2)
Port 1 register (P1) The port 1 register is a 4-bit special function register (SFR) to set the output value of Port 1.
b3 P1 (04H) (R/W) P13
b2 P12
b1 P11
b0 P10
At system reset, P1 is reset to "0". When writing data to the port 1 register, actual timing of the change of the pin is the second half of State 3 of the last machine cycle of the write instruction. Figure 7-3 shows an example of varying timing of the port.
LMAD m8 M1 S1 CLK S2 S3 S1 S2 S3 S1 M2 S2 S3 S1 S2 S3 S1
Port 1
Old Data
New Data
Figure 7-3 Example of Writing to Port Data Register by "LMAD m8" Instruction
7-4
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) In case the data is read from the port, the data is taken in the accumulator (A Register) or the BA register pair at the latter half of the state 2 (S2) of the last machine cycle of the read instruction. Figure 7-4 shows an example of timing.
LAMD m8 M1 S1 CLK S2 S3 S1 S2 S3 S1 M2 S2 S3 S1 S2 S3 S1
Port 0,1
7
A Register Old Data New Data
Figure 7-4 Example of Reading the Data from the Port by the "LAMD m8" Instruction
7-5
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) (3) Port 01 control register (P01CON) The Port 01 control register (P01CON) is a 4-bit special function register (SFR) to control input mode of Port 0, output mode of Port 1 and pull-down/pull-up resistance input when Ports 2 to 4 are selected as input. Since P01CON is a write-only register, bit manipulation and increment/decrement instructions cannot be used.
b3 P01CON (1CH) (R/W) -----*
b2 PUD
b1 P1MOD
b0 P0MOD
Selection of input mode of P0, P2, P3 and P4 0: Pull-up resistance input (initial value) 1: Pull-down resistance input Selection of output mode of P1 0: CMOS output (initial value) 1: NMOS open drain output Selection of input mode of P0 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input *Reserved bit: Not valid for write.
Bit 2: PUD This bit is to select a pull-down/pull-up resistance when P0MOD is reset to "0" and Port 0 is selected as pull-down/pull-up resistance input. When PUD is reset to "0", Port 0 becomes pull-up resistance input and when PUD is set to "1", Port 0 becomes pull-down resistance input. When Ports 2 to 4 are set as input and pull-down/pull-up resistance input, PUD can select either pull-up resistance input or pull-down resistance input. At system reset, PUD is reset to "0". Note: Input setting of Ports 2 to 4 and selection of pull-down/pull-up resistance input can be done by resetting the DIR bits and the MOD bits of the control registers of Ports 2 to 4 (P20CON to P23CON, P30CON to P33CON and P40CON to P43CON). It is not possible to specify pull-up resistance input and pull-down resistance input of Port 0 and Ports 2 to 4 separately. Bit 1: P1MOD This bit is to select output mode of Port 1. By resetting P1MOD to "0", Port 1 becomes CMOS output and by setting P1MOD to "1", Port 1 becomes NMOS open drain output. At system reset, P1MOD is reset to "0". (It is not possible to control P1.0 to P1.3 separately.)
7-6
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) Bit 0: P0MOD This bit is to select input mode of Port 0. By resetting P0MOD to "0", Port 0 becomes pull-down/pull-up resistance input and by setting P0MOD to "1", Port 0 becomes highimpedance input. When selecting pull-down/pull-up resistance input, either pull-down resistance input or pull-up resistance input is selected by the PUD bit. At system reset, P0MOD is reset to "0". (It is not possible to control P0.0 to P0.3 separately).
7.2.3 External Interrupt Generation Timing of Port 0 External interrupt generation of Port 0 is triggered by the falling of the 64 Hz output of the time base counter which is the sampling clock. Delay time until the External 1 interrupt request flag (QXI1) is set after the level of P0.n is changed to output XI1INT signal is a maximum period of 64 Hz (15.625 ms). Since the External 1 interrupt request flag (QXI1) is set by level change of OR signal of Port 0 ports, which port the interrupt request comes from is judged by reading out Port 0. The External 1 interrupt is generated by OR of P0.0 to P0.3. When the PUD bit is set to "1", the External 1 interrupt is generated when (1) input to all the ports is set to the "L" level when all the ports is in "H" and (2) input to any one of the ports is set to the "H" level when all the ports is in "L". When the PUD bit is reset to "0", the External 1 interrupt is generated when (1) input to any one of the ports is set to the "L" level when all the ports is in "H" and (2) input to all the ports is set to the "H" level when all the ports is in "L". The interrupt vector address of the External 1 interrupt is address 032H. Figure 7-5 shows the generation circuit of External 1 interrupt. Figure 7-6 and Figure 7-7 show generation timing of the External 1 interrupt according to the PUD bit.
7
P0.0 P0.1 P0.2 P0.3 D R PUD 64 Hz Q D R Q XI1INT
RESETS Level change detection circuit
Figure 7-5 External 1 Interrupt Generation Circuit
7-7
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
64 Hz P0.0
P0.1
P0.2
P0.3
XI1INT
QXI1
Figure 7-6 External 1 Interrupt Generation Timing (When PUD = 1)
64 Hz P0.0
P0.1
P0.2
P0.3
XI1INT
QXI1
Figure 7-7 External 1 Interrupt Generation Timing (When PUD = 0)
7-8
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.3 Port 2, Port 3 and Port 4 (P2.0 to P2.3, P3.0 to P3.3 and P4.0 to P4.3) 7.3.1 Layout of Port 2, Port 3 and Port 4 Ports 2 to 4 are 4-bit input/output ports. Each bit can be switched to either pull-up resistance input/pull-down resistance input, high-impedance input, CMOS output or NMOS open drain output by the Control registers of Ports 2 to 4 (P20CON to P23CON, P30CON to P33CON and P40CON to P43CON). Pull-up resistance input or pull-down resistance input can be selected by the PUD bit of the Port 01 control register (P01CON). These ports are assigned an external interrupt function by level change as a secondary function. A serial port input/output function is assigned for P3.3, P4.0 to P4.2 and P4.3 is assigned a monitor function of the RC oscillation clock is assigned for P4.3. For details of the serial port input/output functions and the monitor functions of the RC oscillation clock, refer to Chapter 8 "Serial Port", Chapter 12 "A/D Converter" and Chapter 15 "Test Circuit". Figure 7-8 shows the layout of Port 2, Port 3 and Port 4. 7
VSS
VDD PUD (from PO1CON) Pull-up/pull-down control
Bit manipulation, increment and decrement instructions Read P2 to P4
Internal data bus P2.n P3.n P4.n VSS VDD Gate control circuit Output data P2, P3, P4 data register
Write P2 to P4
MPX
1
Note) n = 0 to 3
EINT FSMPL
Mode control
4
P2nCON P3nCON P4nCON
VSS
OUT mode 4
Level change detection
Interrupt enable circuit 64 Hz System clock (CLK) 11
400 kHz:from 2CLK OSCCLK:from ADC SOUT SIN from SIOP SCLK SPR XI0INT (External interrupt 0) to interrupt controller
From other input/output port
Figure 7-8 Layout of Port 2, Port 3 and Port 4 7-9
Port selector
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) The power supply of Port 2, Port 3 and Port 4 is at the VDD-VSS level. When connecting Ports 2 to 4 to external equipment operated by a different power supply, please supply the power of the external equipment to the VDD-VSS pins, as shown in Figure 7-9.
External equipment P2.0 VDD P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 VSS P4.2 P4.3
MSM64164C
VDD
IC power supply
VSS1 or VSS2
VSS
Figure 7-9 Connection of Ports 2 to 4 to External Equipment of Different Power Supply
When the signal level of all the ports of Port 0, Port 1 and Ports 2 to 4 can be the power supply voltage of the IC, connect the VSS pin to either VSS1 (for 1.5 V spec.) or VSS2 (for 3.0 V spec.).
7-10
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.3.2 Registers Related to Port 2, Port 3 and Port 4 (1) Port 2 register (P2) The Port 2 register is a 4-bit special function register to set the output value of the port. When bit 1 (P20DIR to P23DIR) of the Port 2 control register (P20CON to P23CON) is set to "1" to select output mode, the contents of the Port 2 register are output to the port. When reading out P2 while output mode is selected (P20DIR to P23DIR = 1), the contents of the Port 2 register are read. However, when P2 is read while input mode is selected (P20DIR to P23DIR = 0), the pin level of Port is read out. b3 P2 (00H) (R/W) P23 b2 P22 b1 P21 b0 P20 7
(2) Port 3 register (P3) The Port 3 register is a 4-bit special function register to set the output value of the port. When bit 1 (P30DIR to P33DIR) of the Port 3 control register (P30CON to P33CON) is set to "1" to select output mode, the contents of the Port 3 register are output to the port. When reading out P3 while output mode is selected (P30DIR to P33DIR = 1), the contents of the Port 3 register are read. However, when P3 is read while input mode is selected (P30DIR to P33DIR = 0), the pin level of port is read out. b3 P3 (01H) (R/W) P33 b2 P32 b1 P31 b0 P30
(3) Port 4 register (P4) The Port 4 register is a 4-bit special function register to set the output value of the port. When bit 1 (P40DIR to P43DIR) of the Port 4 control register (P40CON to P43CON) is set to "1" to select output mode, the contents of the Port 4 register are output to the port. When reading out P4 while output mode is selected (P40DIR to P43DIR = 1), the contents of the Port 4 register are read. However, when P4 is read while input mode is selected (P40DIR to P43DIR = 0), the pin level of port is read out. b3 P4 (02H) (R/W) P43 b2 P42 b1 P41 b0 P40
7-11
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) It is possible to specify input/output bitwise by each Port control register for Ports 2 to 4. Consequently, depending on how each DIR bit is specified, contents of each register are read for some bits while the level of each pin are read for other bits. At system reset, the Port 2 to Port 4 register (P2 to P4) is reset to "0". When writing data to each register, actual timing of each pin is the second half of State 3 of the last machine cycle of the write instruction. Figures 7-10 shows an example of varying timing of the ports.
LMAD m8 M1 S1 CLK Port 2, 3 and 4 S2 S3 S1 S2 S3 S1 M2 S2 S3 S1 S2 S3 S1
Old Data
New Data
Figure 7-10 Example of Writing of Port Data Register by the "LMAD m8" Instruction In case the data is read from the port, the data is taken in the accumulator (A Register) and the BA register pair at the latter half of the state 2 (S2) of the last machine cycle of the read instruction. Figure 7-11 shows an example of timing.
LAMD m8 M1 S1 CLK S2 S3 S1 S2 S3 S1 M2 S2 S3 S1 S2 S3 S1
Port 2,3,4
A Register
Old Data
New Data
Figure 7-11 Example of Reading the Data from the Port by the "LAMD m8" Instruction (4) Port 2 control registers (P20CON to P23CON) The Port 2 control registers (P20CON to P23CON) are 4-bit special function registers (SFRs) to perform selection of input/output mode, selection of pull-down/pull-up resistance input or high impedance input in input mode, selection of CMOS output or NMOS open drain output in output mode, selection of external interrupt disable or enable and selection of sampling clocks of external interrupts. Since P20CON to P23CON are writeonly registers, it is not possible to use bit manipulation instructions and increment/ decrement instructions.
7-12
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P20CON (10H) (W) P20IE
b2 P20F
b1 P20DIR
b0 P20MOD
Selection of P2.0 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P2.0 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P2.0 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P2.0 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P2.0 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
7
7-13
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P21CON (11H) (W) P21IE
b2 P21F
b1 P21DIR
b0 P21MOD
Selection of P2.1 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P2.1 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P2.1 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P2.1 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P2.1 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P22CON (12H) (W) P22IE
b2 P22F
b1 P22DIR
b0 P22MOD
Selection of P2.2 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P2.2 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P2.2 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P2.2 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P2.2 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
7
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P23CON (13H) (W) P23IE
b2 P23F
b1 P23DIR
b0 P23MOD
Selection of P2.3 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P2.3 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P2.3 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P2.3 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P2.3 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
7-16
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) (5) Port 3 control registers (P30CON to P33CON) The Port 3 control registers (P30CON to P33CON) are 4-bit special function registers (SFRs) to perform selection of input/output mode, selection of pull-down/pull-up resistance input or high impedance input in input mode, selection of CMOS output or NMOS open drain output in output mode, selection of external interrupt disable or enable and selection of sampling clocks of external interrupts. There is no selection bit of sampling clock of an external interrupt for Port 3.3 and selection of the SIN function is assigned which is a secondary function of the serial port. Since P30CON to P33CON are write-only registers, it is not possible to use bit manipulation instructions and increment/decrement instructions.
b3 P30CON (14H) (W) P30IE
b2 P30F
b1 P30DIR
b0 P30MOD 7
Selection of P3.0 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P3.0 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P3.0 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P3.0 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P3.0 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P31CON (15H) (W) P31IE
b2 P31F
b1 P31DIR
b0 P31MOD
Selection of P3.1 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P3.1 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P3.1 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P3.1 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P3.1 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P32CON (16H) (W) P32IE
b2 P32F
b1 P32DIR
b0 P32MOD
Selection of P3.2 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Selection of P3.2 external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock Selection of P3.2 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P3.2 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P3.2 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
7
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P33CON (17H) (W) P33IE
b2 SIN
b1 P33DIR
b0 P33MOD
Selection of P3.3 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Switching of P3.3/SIN pin functions 0: Input/output port function (initial value) 1: Serial port data input function (P3.3 is selected to input mode in disregard of P33DIR) Selection of P3.3 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P3.3 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P3.3 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
7-20
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) (6) Port 4 control registers (P40CON to P43CON) The port 4 control registers (P40CON to P43CON) are 4-bit special function registers (SFRs) to perform selection of input/output mode, selection of pull-down/pull-up resistance input or high impedance input in input mode, selection of CMOS output or NMOS open drain output in output mode, selection of external interrupt disable or enable and selection of SOUT, SPR, SCLK functions of the serial port or RC oscillation monitor functions which are a secondary function. Since P40CON to P43CON are write-only registers, it is not possible to use bit manipulation instructions and increment/decrement instructions. b3 P40CON (18H) (W) P40IE b2 SOUT b1 P40DIR b0 P40MOD 7
Selection of P4.0 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Switching of P4.0/SOUT pin functions 0: Input/output port function (initial value) 1: Serial port data output function (P4.0 is selected to output mode in disregard of P40DIR) Selection of P4.0 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P4.0 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P4.0 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P41CON (19H) (W) P41IE
b2 SPR
b1 P41DIR
b0 P41MOD
Selection of P4.1 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Switching of P4.1/SPR pin functions 0: Input/output port function (initial value) 1: Serial port data ready signal output function (P4.1 is selected to output mode in disregard of P41DIR) Selection of P4.1 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P4.1 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P4.1 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P42CON (1AH) (W) P42IE
b2 SCLK
b1 P42DIR
b0 P42MOD
Selection of P4.2 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Switching of P4.2/SCLK pin functions 0: Input/output port function (initial value) 1: Serial port clock input/output function (P4.2 input/output mode is selected by EXSC of Serial port control register (SCON)) Selection of P4.2 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P4.2 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P4.2 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output 7
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
b3 P43CON (1BH) (W) P43IE
b2 MON
b1 P43DIR
b0 P43MOD
Selection of P4.3 external interrupt disable/enable 0: Interrupt disabled (initial value) 1: Interrupt enabled Switching of P4.3/MON pin functions 0: Input/output port function (initial value) 1: RC oscillation clock monitor output function (P4.3 is selected to output mode in disregard of P43DIR) Selection of P4.3 input/output mode 0: Input mode (initial value) 1: Output mode Selection of P4.3 pull-down/pull-up resistance input/ high-impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input Selection of P4.3 CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Bit 3: P20IE to P23IE, P30IE to P33IE and P40IE to P43IE This bit is to select disabling/enabling external interrupts. When each IE bit is reset to "0", external interrupts are disabled and when each IE bit is set to "1", the external 0 interrupt request is generated by detecting the change of input level of the pin if the corresponding port is in input mode. At system reset, each IE bit is reset to "0". Bit 2: P20F to P23F and P30F to P32F This bit is to select a sampling clock of an external interrupt. When each F bit is reset to "0", the 64 Hz output of the time base counter is selected as the sampling clock and when each F bit is set to "1", the system clock (32.768 kHz or 400 kHz) is chosen as the sampling clock. At system reset, each F bit is reset to "0". There is no selection function of the sampling clock of external interrupts for P3.3 and P4.0 to P4.3 and it is fixed at 64 Hz.
7-24
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) Bit 2: SIN (P33CON) This bit selects data input (SIN) of the serial port which is a secondary function of Port 3.3. When SIN is reset to "0", P3.3 becomes a normal port function and when SIN is set to "1", the data input function of the serial port is assigned. When SIN is set to "1", P3.3 is automatically set to input mode. At system reset, SIN is reset to "0". Bit 2: SOUT (P40CON) This bit sets data output (SOUT) of the serial port which is a secondary function of Port 4.0. When SOUT is reset to "0", P4.0 becomes a normal port function and when it is set to "1", the data output function of the serial port is assigned. When SOUT is set to "1", P4.0 is set to output mode automatically. At system reset, SOUT is reset to "0". Bit 2: SPR (P41CON) This bit sets data ready signal (SPR) of the serial port which is a secondary function of Port 4.1. When SPR is reset to "0", P4.1 becomes a normal port function and when it is set to "1", the data ready signal output function of the serial port is assigned. When SPR is set to "1", P4.1 is set to output mode automatically. At system reset, SPR is reset to "0". Bit 2: SCLK (P42CON) This bit sets transfer clock input/output (SCLK) of the serial port which is a secondary function of Port 4.2. When SCLK is reset to "0", P4.2 becomes a normal port function and when it is set to "1", the transfer clock input/output function of the serial port is assigned. When SCLK is set to "1", P4.2 is set to output mode automatically in the mode where the system clock is set as the transfer clock after resetting the EXSC bit of the serial port control register (SCON) to "0". P4.2 is set to input mode in the mode where the EXSC bit is set to "1". At system reset, SCLK is reset to "0". Bit 2: MON (P43CON) This bit sets output of the RC oscillation clock (MON) which is a secondary function of Port 4.3. When MON is reset to "0", P4.3 becomes a normal port function and when it is set to "1", the output function of the A/D converter RC oscillation clock is assigned. When MON is set to "1", P4.3 is set to output mode automatically. At system reset, MON is reset to "0". Bit 1: P20DIR to P23DIR, P30DIR to P33DIR and P40DIR to P43DIR This bit selects input/output of each port. When each DIR bit is reset to "0", each port becomes input mode and when each DIR bit is set to "1", each port becomes output mode. At system reset, each DIR bit is reset to "0". Bit 0: P20MOD to P23MOD, P30MOD to P33MOD and P40MOD to P43MOD When each DIR bit is reset to "0" to select input mode, pull-down/pull-up resistance input or high-impedance input is selected.
7
7-25
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) When each DIR bit is set to "1" to select output mode, CMOS output or NMOS open drain output is selected. When each MOD bit is reset to "0", pull-down/pull-up resistance input is selected in input mode and CMOS output mode is selected in output mode. When each MOD bit is set to "1", high-impedance input is selected in input mode and NMOS open drain output mode is selected in output mode. Selection of pull-down/pull-up input is done by bit 2 (PUD) of the Port 01 control register (P01CON). When PUD is reset to "0", it becomes pull-up resistance input and when PUD is set to "1", it becomes pull-down resistance input. At system reset, each MOD bit is reset to "0". Table 7-2 shows the relationship among each DIR bit, each MOD bit and each PUD bit.
Table 7-2 Relation among Each DIR Bit, Each MOD Bit and Each PUD Bit Each DIR 0 0 0 1 1 Each MOD 0 0 1 0 1 PUD 0 1 -- -- -- State of input/output Pull-up resistance input selected Pull-down resistance input selected High-impedance input selected CMOS output selected NMOS open drain output selected
7-26
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) 7.3.3 External Interrupt Generation Timing of Port 2, Port 3 and Port 4 External interrupt of Ports 2 to 4 is generated when each IE bit (P20IE to P23IE, P30IE to P33IE and P40IE to P43IE) of P2.0 to P2.3, P3.0 to P3.3 and P4.0 to P4.3 are set to "1" and by the change of an input level of those ports for which each DIR bit (P20DIR to P23DIR, P30DIR to P33DIR and P40DIR to P43DIR) is set to "0" (set for interrupt enable and input mode). The External 0 interrupt (XI0INT) is generated by OR signal of each level change detection signal. Change of input level can be sampled by 64 Hz output of the time base counter which is the sampling clock or by falling of the system clock (32.768 kHz or 400 kHz). Selection of the sampling clock is performed by Bit 2 (P20F to P23F, P30F to P32F) of each port control register and when the F bit is reset to "0", the sampling clock becomes 64 Hz and when the F bit is set to "1", the sampling clock changes to the system clock. There is no function to select the sampling clock for P3.3 and P4.0 to P4.3 and they are fixed at 64 Hz output of the time base counter. Delay time until the External 0 interrupt request flag (QXI0) is set after the level of Port 2 to Port 4 is changed to output XI0INT signal is one period of the sampling clock or less. Since the External 0 interrupt request flag (QXI0) is set by input level change of one of Port 2 to Port 4, which port the interrupt request comes from should be judged by checking the signal level after reading out each port. The interrupt vector address of External interrupt XI0INT is address 038H. Figures 7-12 and 7-13 show the External 0 interrupt generation circuit and timing.
7
P2nDIR P3nDIR P4nDIR
P2nIE P3nIE P4nIE XI0INT (to interrupt controller) 11 From other I/O ports
P2.n P3.n P4.n
D R
Q
D R
Q
64 Hz System clock (32 kHz/ 400 kHz) P2nF P30F P31F P32F Sampling clock RESETS (n = 0 to 3) Level change detection circuit
Figure 7-12 External 0 Interrupt Generation Circuit (one bit)
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
64 Hz or system clock
P2.n P3.n P4.n P2.nIE P3.nIE P4.nIE
XIOINT
QXI0
Figure 7-13 External 0 Interrupt Generation Timing
7-28
MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4) Table 7-3 shows the list of port-related registers.
Table 7-3 List of Port-Related Registers
Value at system reset 0H 0H 0H Depends on input value 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 8H 0H 0H
Register name Port 2 register Port 3 register Port 4 register Port 0 register Port 1 register Port 20 control register Port 21 control register Port 22 control register Port 23 control register Port 30 control register Port 31 control register Port 32 control register Port 33 control register Port 40 control register Port 41 control register Port 42 control register Port 43 control register Port 01 control register Interrupt enable register 0 Interrupt request register 0
Symbol P2 P3 P4 P0 P1 P20CON P21CON P22CON P23CON P30CON P31CON P32CON P33CON P40CON P41CON P42CON P43CON P01CON IE0 IRQ0
Address 00H 01H 02H 03H 04H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 30H 34H
Read/Write R/W R/W R/W R R/W W W W W W W W W W W W W W R/W R/W
Byte access
Yes
Yes No Yes
7
Yes
Yes
Yes
Yes
Yes No Yes Yes
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MSM64164C User's Manual Chapter 7 Ports (P0, P1, P2, P3 and P4)
7-30
Chapter 8
Serial Port (SIOP)
8
MSM64164C User's Manual Chapter 8 Serial Port (SIOP)
Chapter 8 Serial Port (SIOP)
8.1 Overview The MSM64164C has an 8-bit synchronous serial port. Receive/transmit operation of the serial port is performed simultaneously and the serial transfer clock can select either internal or external mode. Direction of transfer data can be either MSB as a head or LSB as a head. Each pin of the serial port is assigned as secondary functions of P3.3 and P4.0 to P4.2. Setting each bit of SIN, SOUT, SPR and SCLK of P33CON and P40CON to P42CON to "1" makes each pin valid.
8
8-1
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) 8.2 Layout of Serial Port Figure 8-1 shows the layout of the serial port. In Figure 8-1, P3.3 is the data receive pin, P4.0 is the data transmit pin, P4.1 is the serial port ready pin and P4.2 is the transfer clock pin.
P3.3/SIN 8-bit shift register (SR) D S Q P4.0/SOUT
ENTR P4.2/SCLK 8 System clock Serial port controller 32.768 kHz/400 kHz Internal clock generation EXSC SIOINT interrupt request SEND ENTR SIDR LSB/MSB switch P4.1/SPR
SCON
SBUFH
SBUFL
3
2
1
0
Internal data bus
Figure 8-1 Layout of Serial Port
8-2
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) 8.3 Operation of Serial Port By setting the ENTR bit of the Serial port control register (SCON) to "1" after writing send data to the Serial port buffers (SBUFH and SBUFL), serial transfer begins. When serial transfer is finished, the SEND bit of SCON is set to "1" and the Serial port interrupt request SIOINT is generated. The vector address of the Serial port interrupt request is at address 035H. When serial transfer is finished, receive data is written to SBUFH and SBUFL. It is not necessary to write send data if only the receive operation is performed. The SDIR bit of SCON is used to select the direction of transfer data and if SDIR is reset to "0", MSB of SBUFH and SBUFL becomes head data and if SDIR is set to "1", LSB becomes head data. The EXSC bit of SCON is used to select transfer clocks. When EXSC is reset to "0", the system clock is selected as the transfer clock and the system clock is output to the P4.2/SCLK pin. By setting EXSC to "1", the external clock can be selected as the transfer clock and those clocks input from the P4.2/SCLK pin become the transfer clocks. Figure 8-2 shows the operation time chart of the serial port.
w e
P4.1/SPR tCLK P4.2/SCLK P4.0/SOUT P3.3/SIN 1/2 tCLK 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 1/2 tCLK Set by software 1/2 tCLK ENTR SBUFH, SBUFL SR SIOINT o Send data Reset by hardware 1/2 tCLK When internal clock generated
8
r
y
Receive data
q
o
t
y
tCLK : period of system clock Interrupt request
Figure 8-2 Serial Port Operation Time Chart
8-3
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) As shown in Figure 8-2, when serial transfer is started by setting the ENTR bit to "1", the P4.1/ SPR pin of the transfer ready pin becomes "L" level. After the other side of the communication detects "L" level of the P4.1/SPR pin, sending data is triggered at the falling of the transfer clock of P4.2/SCLK and receiving data is gotten at the rising. When the external clock is selected, it is necessary to input transfer clocks after detecting "L" level of P4.1/SPR. Internal operation when the transfer is started by setting the ENTR bit to "1" is shown below:
q The contents of SBUFH and SBUFL are written to the 8-bit shift register (SR). w "L" level is output to the P4.1/SPR pin. e With the falling of the transfer clock of the P4.2/SCLK pin, data in SR is output to the P4.0/
SOUT pin and with the rising of the transfer clock, input data of the P3.3/SIN pin are received by SR.
r When the 8-bit transfer is finished, "H" level is output to the P4.1/SPR pin. t The contents of SR are written to SBUFH and SBUFL. y The ENTR bit is reset to "0", the SEND bit is set to "1" and a Serial port interrupt request
(SIOINT) is generated. When transmission and reception are not made simultaneously, it is possible to do the data signal lines to a single line by connecting SIN and SOUT terminals at external. In this case, we recommend you respectively to set the SOUT terminal to a NMOS open drain mode (P40MOD bit of P40CON is made to "1") and to set the SIN terminal to a pull-up resistance mode. (PUD bit of P01CON is made to "0".) If the PUD bit of P01CON can not be set to "0" for using a pull-down mode in other, do the SIN terminal to a high impedance mode (P33MOD bit of P33CON is made to "1") and pull-up to VDD at external.
8-4
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) 8.4 Registers Related to Serial Port (1) Serial Port Control Register (SCON) The Serial port control register (SCON) is a 4-bit special function register (SFR) to control the Serial port. b3 SCON (08H) (R/W) Selection of transfer data direction 0: MSB (SD7) head (initial value) 1: LSB (SD0) head Selection of serial clock 0: Internal clock (initial value) 1: External clock Serial transfer finish flag 0: Transfer not finished (initial value) 1: Transfer finished Serial transfer enable flag 0: Transfer halted (initial value) 1: Transfer started Bit 3: SDIR This bit is used to select the direction of serial transfer data. When reset to "0", MSB becomes the head transfer data and when set to "1", LSB becomes the head transfer data. At system reset, it is reset to "0" and is in MSB head mode. Bit 2: EXSC This bit is used to select the transfer clock of serial transfer. When reset to "0", the system clock is selected as the transfer clock and when set to "1", the external clock that is input from P4.2/SCLK is selected. At system reset, it is reset to "0" and the system clock is selected as the transfer clock. Bit 1: SEND This bit is used to indicate the completion of serial transfer. When serial transfer is completed, the SEND bit is set to "1" and the Serial port interrupt request (SIOINT) is generated. When reading or writing from/to the serial port control register (SCON), the SEND bit is reset to "0". The SEND bit is a read-only bit and is reset to "0" at system reset. Bit 0: ENTR This bit specifies whether serial transfer is enabled or not. When reset to "0", serial transfer is halted and is started when this bit is set to "1". At system reset, it is reset to "0" and serial transfer is halted. When ENTR is set to "1", this bit is automatically reset after serial transfer is completed. Writing "0" to ENTR during serial transfer (when ENTR = 1) interrupts serial transfer. At that time, the serial port interrupt request (SIOINT) is not generated. 8-5 SDIR b2 EXSC b1 SEND b0 ENTR
8
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) (2) Serial Port Buffer Registers (SBUFH, SBUFL) The Serial port buffer registers are 4-bit special function registers (SFRs) to write send data or to read receive data.
b3 SBUFL (06H) (R/W) SD3
b2 SD2
b1 SD1
b0 SD0
Value of lower bits of the serial port buffer
b3 SBUFH (07H) (R/W) SD7 (MSB) Value of upper bits of the serial port buffer
b2 SD6
b1 SD5
b0 SD4
Bit 0 of SBUFL(SD0) is LSB and Bit 3 of SBUFH(SD7) is MSB. Byte processing is possible for these two registers. When SBUFL and SBUFH are read after the completion of serial transfer, the contents become receive data. Figure 8-3 shows the bit composition of serial data output from the SOUT pin as well as input to the SIN pin and the contents of SBUFL and SBUFH.
a) When SIR = "0" (MSB as head)
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7 (Head)
Transfer direction
b) When SDIR = "1" (LSB as head)
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0 (Head)
Transfer direction
Figure 8-3 Bit Composition of Transfer Data
8-6
MSM64164C User's Manual Chapter 8 Serial Port (SIOP) Tables 8-1 and 8-2 show the list of serial port-related registers and pins.
Table 8-1 List of Serial Port-Related Registers
Register name Serial port buffer lower register Serial port buffer upper register Serial port control register Interrupt enable register 0 Interrupt request register 0
Symbol SBUFL SBUFH SCON IE0 IRQ0
Address 06H 07H 08H 30H 34H
Read/Write R/W R/W R/W R/W R/W
Byte access
Value at system reset 0H 0H 0H 0H 0H
Yes No Yes Yes
Table 8-2 List of Serial Port-Related Pins 8
Pin No. Pin name P3.3 P4.0 P4.1 P4.2 Pad No. GS-BK GS-K TS-K 25 26 27 28 23 24 25 26 25 26 27 28 Input/ Output Input Output Output Note Serial port data input (SIN) Serial port data output (SOUT) Serial port ready output (SPR)
Input/Output Serial port transfer clock input/output (SCLK)
8-7
MSM64164C User's Manual Chapter 8 Serial Port (SIOP)
8-8
Chapter 9
Buzzer Driver (BD)
9
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD)
Chapter 9 Buzzer Driver (BD)
9.1 Overview The MSM64164C has a built-in buzzer driver with 15 buzzer output frequencies and 4 buzzer output modes. Each buzzer output is selected by the Buzzer control register (BDCON) and the Buzzer frequency control register (BFCON).
9.2 Layout of Buzzer Driver Figure 9-1 shows the layout of the buzzer driver.
From time base counter 16 Hz 8 Hz 1 Hz
Time base clock 32.768 kHz
Frequency division circuit
Buzzer driver circuit
9
BD
VSS1/VSS2
BFCON
BDCON
Internal data bus
0
1
2
3
0
1
2
Figure 9-1 Layout of Buzzer Driver 9.3 Operation of Buzzer Driver When Bit 2 (EBD) of the Buzzer control register (BDCON) is set to "1", buzzer drive signals are output at the buzzer driver pin (BD). The Buzzer frequency control register (BFCON) can select 15 buzzer output frequencies. In buzzer output mode, two kinds of discontinuous sounds, a single sound and a continuous sound can be selected by Bit 1/0 (BM1/BM0) of BDCON. Bit 3 (SELF) of BDCON can select output logic of the BD pin. When the SELF bit is reset to "0", positive logic output ("L" level output at halt) is selected and negative logic output ("H" level output at halt) is selected when it is set to "1". The duty of buzzer output frequencies is 50%.
9-1
SELF
3
BM 1
BM0
EBD
BF0
BF1
BF2
BF3
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD) In (a) discontinuous sound 1 mode, waveforms which are synchronized with 8 Hz output of the time base counter are output. In (b) discontinuous 2 mode, waveforms that are synchronized to the logical AND of 8 Hz signal output and a "L" level of 1 Hz signal are output. In (c) single sound mode, output begins synchronizing with the rising of EBD and stops at the falling of 16 Hz output of the time base counter. In (d) continuous sound mode, output is continued while EBD is "1". Figure 9-2 shows output waveforms in each output mode. Shaded area in the figure indicates the buzzer output frequency signal.
EBD 8 Hz BD Output
ON OFF
(a) BM1 = 0, BM0 = 0 (Discontinuous sound 1)
EBD 8 Hz 1 Hz BD Output
ON OFF
(b) BM1 = 0, BM0 = 1 (Discontinuous sound 2)
EBD 16 Hz BD Output
ON OFF
(c) BM1 = 1, BM0 = 0 (Single sound)
EBD BD Output
ON OFF
(d) BM1 = 1, BM0 = 1 (Continuous sound)
Figure 9-2 Buzzer Driver Output Waveforms in Each Output Mode
9-2
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD) 9.4 Registers Related to Buzzer Driver (1) Buzzer control register (BDCON) The Buzzer control register (BDCON) is a 4-bit special function register (SFR) that controls output logic of the BD pin, 4 types of buzzer output modes and ON/OFF of buzzer output. b3 BDCON (0AH) (R/W) Selection of buzzer output logic 0: Positive logic output (initial value) 1: Negative logic output Selection of buzzer enable/disable 0: Buzzer stop (initial value) 1: Buzzer output Selection of buzzer frequency output BM1 BM0 0 0: Discontinuous sound 1 output (initial value) 0 1: Discontinuous sound 2 output 1 0: Single sound output 1 1: Continuous sound output SELF b2 EBD b1 BM1 b0 BM0
9
Bit 3: SELF This bit selects output logic of the BD pin. When reset to "0", positive logic output is selected ("L" level output when output is halted) and negative logic output ("H" level output when output is halted) is selected when set to "1". At system reset, it is reset to "0" and positive logic output is selected. Bit 2:EBD This bit selects ON/OFF of the buzzer driver output. At system reset, it is reset to "0" so that no buzzer is output. Bits 1 and 0: BM1 and BM0 This bit selects output mode of the buzzer driver. It can select two types of discontinuous sounds, a single sound and a continuous sound. At system reset, BM1 and BM0 are reset to "0" so that discontinuous sound 1 output is selected.
9-3
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD) (2) Buzzer frequency control register (BFCON) The buzzer frequency control register (BFCON) is a 4-bit special function register (SFR) to control output frequencies of the buzzer.
b3 BFCON (0BH) (R/W) BF3
b2 BF2
b1 BF1
b0 BF0
Selection of buzzer output frequencies BF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BF2 BF1 BF0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0: Output stop (initial value) 1: 5.461 kHz 0: 4.096 kHz 1: 3.277 kHz 0: 2.730 kHz 1: 2.341 kHz 0: 2.048 kHz 1: 1.820 kHz 0: 1.638 kHz 1: 1.489 kHz 0: 1.365 kHz 1: 1.260 kHz 0: 1.170 kHz 1: 1.092 kHz 0: 1.024 kHz 1: 0.964 kHz
Bits 3 to 0: BF3 to 0 These bits select buzzer output frequency. At system reset, all are reset to "0" so that output is halted. Each output frequency is output with 50% duty.
9-4
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD) Tables 9-1 and 9-2 show the lists of buzzer driver-related registers and related pins. Table 9-1 Buzzer Driver-Related Registers
Value at system reset 0H 0H
Register name Buzzer driver control register Buzzer frequency control register
Symbol BDCON BFCON
Address 0AH 0BH
Read/Write R/W R/W
Byte access
Yes
Table 9-2 Buzzer Driver-Related Pins
Pin No. Pin name BD Pad No. GS-BK GS-K TS-K 30 28 30
Input/ Output Output Buzzer driver pin
Note
9 9.5 BD Output Waveform and External Circuit Figure 9-3 shows the output waveform of the output pin of the buzzer driver. Output level of VDD-VSS1/VSS2 is output at the BD pin.
Positive logic output Negative logic output
SELF bit
Output frequency (selected by BFCON) VDD BD output VSS1 or VSS2 Sound output state No sound state Sound output state
Figure 9-3 Waveform at BD Pin
9-5
MSM64164C User's Manual Chapter 9 Buzzer Driver (BD) Figure 9-4 shows a circuit example of a buzzer driver mounted outside. As illustrated blow, the buzzer must be driven through a transistor mounted outside and do not drive the buzzer directly at the BD terminal.
VDD MSM64164C
Buzzer
BD npn transistor
VSS1/VSS2
(a) In the case of SELF bit = "0"
VDD MSM64164C
BD pnp transistor
Buzzer VSS1/VSS2
(b) In the case of SELF bit = "1"
Figure 9-4 Circuit Example of a Buzzer Driver Mounted Outside
9-6
Chapter 10
Capture Circuit (CAPR)
10
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR)
Chapter 10 Capture Circuit (CAPR)
10.1 Overview The MSM64164C has a capture circuit that fetches 32 Hz to 256 Hz output of the time base counter at the falling of Port 0.0 or 0.1 (P0.0 or P0.1) to "L" level when the pull-up resistance input is chosen or at the rising to "H" level when the pull-down resistance input is chosen. The capture circuit is composed of the Capture control register (CAPCON) and the Capture registers (CAPR0, CAPR1) that fetch output from the time base counter. 10.2 Layout of Capture Circuit Figure 10-1 shows the layout of the capture circuit.
CAPCON
b3 P0.1 input signal CAPR1 READ delay
D S R Q
CRF1
b2 P0.0 input signal delay CAPR0 READ PUD ECAP1
Q R D D S R Q
10
CRF0
b1
Internal data bus
2 kHz RESETS ECAP0
Q R D
b0
CAPCON WRITE CAPCON READ
From time base counter
CAPR0 32 Hz 64 Hz
D Q L
b3 b2 b1 b0 CAPR1
128 Hz 256 Hz
L
b3 b2
Q
D
b1 b0 CAPR1 READ CAPR0 READ
Figure 10-1 Layout of Capture Circuit 10-1
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR) 10.3 Operation of Capture Circuit Figure 10-2 shows data latch timing of the Capture data register 0 (CAPR0). In Figure 10-1, CRF0 is set to "1" at the rising edge of 2 kHz output of the time base counter either when P0.0 input signal becomes "L" level selecting pull-up resistance input or when it becomes "H" level selecting pull-down resistance input while ECAP0 is set to "1" (q in Figure10-2). When CRF0 is set to "1", the latch signal of the Capture data register 0 (CAPR0) becomes "L" level and 32 Hz to 256 Hz of the time base counter is latched to CAPR0 (w). When CAPR0 is read out, CRF0 is reset to "0" (e). A similar operation is performed when "1" is written to CRF0 even though P0.0 input signal is neither at "L" level nor at "H" level (r). When ECAP0 is reset to "0" during the latching state, latch operation of CAPR0 is cancelled (t). If the latch signal of CAPR0 is at "H" level (i.e. CRF0 or ECAP0 is reset to "0"), when CAPR0 is read out, 32 Hz to 256 Hz of the time base counter then is read out. In Figure 10-1, CRF1 is set to "1" at the rising edge of 2 kHz output of the time base counter either when P1.1 of the input port becomes "L" level selecting pull-up resistance input or when it becomes "H" level selecting pull-down resistance input while ECAP1 is set to "1". When CRF1 is set to "1", the latch signal of the Capture data register 1 (CAPR1) becomes "L" level and 32 Hz to 256 Hz of the time base counter is latched to CAPR1. When CAPR1 is read out, CRF1 is reset to "0". A similar operation is performed when "1" is written to CRF1 even though P0.1 input signal is neither in "L" level nor in "H" level. If the latch signal of CAPR1 is at "H" level (i.e. CRF1 or ECAP1 is reset to "0"), when CAPR1 is read, 32 Hz to 256 Hz of the time base counter then is read out.
Time base output 256 Hz 128 Hz 64 Hz 32 Hz
CAPR0 output PUD ECAP0 P0.0 CRF0
E
F
0
1
2
3 wLatch
5
6 Latch
8 t
9
A
B
C
Pull-down resistance input mode
q
e
r CAPR0 read
Data latch CAPR0 Data latch (P0.0 = 1) read-out (CRF0 = 1)
Figure 10-2 Data Latch Timing of Capture Data Register 0 (CAPR0) 10-2
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR) 10.4 Registers Related to Capture Circuit (1) Capture control register (CAPCON) The Capture control register (CAPCON) is a 4-bit special function register (SFR) to control the capture circuit. b3 CAPCON (0EH) (R/W) CRF1 b2 CRF0 b1 ECAP1 b0 ECAP0
Selection of capture 1 data latch 0: Does not do capture 1 data latch (initial value) 1: Does capture 1 data latch Selection of capture 0 data latch 0: Does not do capture 0 data latch (initial value) 1: Does capture 0 data latch Selection of capture 1 enable/disable 0: Capture 1 disable (initial value) 1: Capture 1 enable Selection of capture 0 enable/disable 0: Capture 0 disable (initial value) 1: Capture 0 enable
10
Bit 3:CRF1 This bit is the capture flag for the Capture register 1 (CAPR1). CRF1 is set to "1" when P0.1 of the input port detects "L" level selecting pull-up resistance input or when it detects "H" level selecting pull-down resistance input. When CRF1 is set to "1" while ECAP1 is set to "1", 32 Hz to 256 Hz output of the time base counter is latched to CAPR1. When "1" is written to CRF1, a similar operation to the detection of "H" level or "L" level by P0.1 is performed. CRF1 is reset to "0" when reading out CAPR1. At system reset, CRF1 is reset to "0". Bit 2:CRF0 This bit is the capture flag for the Capture register 0 (CAPR0). CRF0 is set to "1" when P0.0 of the input port detects "L" level selecting pull-up resistance input or when it detects "H" level selecting pull-down resistance input. When CRF0 is set to "1" while ECAP0 is set to "1", 32 Hz to 256 Hz output of the time base counter is latched to CAPR0. When "1" is written to CRF0, a similar operation to the detection of "H" level or "L" level by P0.0 is performed. CRF0 is reset to "0" when reading out CAPR0. At system reset, CRF0 is reset to "0".
10-3
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR) Bit 1:ECAP1 This bit enables or disables latch of output of the time base counter by the Capture register 1 (CAPR1). When ECAP1 is reset to "0", output of the time base counter is not latched and when CAPR1 is read out, the time base counter value at that time is read out. When CRF1 is set to "1" while ECAP1 is set to "1", 32 Hz to 256 Hz of the time base counter is latched by CAPR1 and when CAPR1 is read out, the value of latched time base counter is read out. At system reset, ECAP1 is reset to "0". Bit 0:ECAP0 This bit enables/disables latch of output of the time base counter by the Capture register 0 (CAPR0). When ECAP0 is reset to "0", output of the time base counter is not latched and when CAPR0 is read out, the time base counter value at that time is read out. When CRF0 is set to "1" while ECAP0 is set to "1", 32 Hz to 256 Hz of the time base counter is latched by CAPR0 and when CAPR0 is read out, the value of latched time base counter is read out. At system reset, ECAP0 is reset to "0".
(2)
Capture registers (CAPR0, CAPR1) The capture registers (CAPR0, CAPR1) are 4-bit special function registers (SFRs) to read out latch data of 32 Hz to 256 Hz of the time base counter.
b3 CAPR0 (0CH) (R) 32Hz
b2 64Hz
b1 128Hz
b0 256Hz
Value of 32 Hz to 256 Hz of time base counter
b3 CAPR1 (0DH) (R) 32Hz
b2 64Hz
b1 128Hz
b0 256Hz
Value of 32 Hz to 256 Hz of time base counter
10-4
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR) Tables 10-1 and 10-2 show the list of capture circuit-related registers and pins.
Table 10-1 List of Capture Circuit-Related Registers
Value at system reset 0H 0H 0H
Register name Capture control register Capture register 0 Capture register 1
Symbol CAPCON CAPR0 CAPR1
Address 0EH 0CH 0DH
Read/Write R/W R R
Byte access No Yes
Table 10-2 Capture Circuit-Related Pins
Pin No. Pin name P0.0 P0.1 Pad No. GS-BK GS-K TS-K 77 78 75 76 77 78
Input/ Output Input Input Trigger input of CAPR0 Trigger input of CAPR1
Note
10
10-5
MSM64164C User's Manual Chapter 10 Capture Circuit (CAPR)
10-6
Chapter 11
Watchdog Timer (WDT)
11
MSM64164C User's Manual Chapter 11 Watchdog Timer (WDT)
Chapter 11 Watchdog Timer (WDT)
11.1 Overview The MSM64164C has a built-in watchdog timer to prevent the CPU from crashing. The watchdog timer is composed of a 6-bit watchdog timer (WDT) and a watchdog timer control register (WDTCON) to reset WDT.
11.2 Layout of Watchdog Timer Figure 11-1 shows the layout of the watchdog timer.
WDTCON Internal pointer T Write WDTCON R Q
Q
4
Detection of "5H" and latch
QWDACK (interrupt acknowledge signal) RESETS
11
Detection of "AH"
Internal data bus
R 1/2 6 Timer counter
O
WDTINT (interrupt request)
16 Hz (from timer base counter)
WDTC
Figure 11-1 Layout of Watchdog Timer
11-1
MSM64164C User's Manual Chapter 11 Watchdog Timer (WDT) 11.3 Operation of Watchdog Timer When the system reset is released, the Watchdog timer (WDT) is automatically started and the Watchdog timer counter (WDTC) begins count-up. WDTC reset can be performed by writing "5H" and "0AH" alternatively to the Watchdog timer control register (WDTCON). If WDTC is not reset, WDTC overflows after 1.9 to 2.0 seconds and the Watchdog timer interrupt request (WDTINT) is generated. WDINT is an interrupt that software cannot disable (non-maskable interrupt) and has the highest priority over other interrupts. Normally WDTC is to be programmed to be reset every one second by software. When reset of WDTC is not performed normally by a CPU crash, WDTC overflows and WDTINT is generated. In the watchdog timer interrupt routine, the return operation to a normal routine should be performed from an abnormal state. Note: The watchdog timer cannot detect all abnormal operations. If WDTC is in reset state, error cannot be detected even if the CPU crashes. Figure 11-2 shows the reset flowchart of the watchdog timer. As shown in the figure, WDT is reset by writing "5H" when the internal pointer is "0" and writing "0AH" when it is "1" to WDTCON. The internal pointer is reset to "0" at system reset and by WDTC overflow and is reversed each time WDTCON is written.
System reset WDTC is reset
Processing
5H is written to WDTCON
Internal pointer:0 1
Processing
Processing time within 1.9 seconds AH is written to WDTCON Internal pointer:1 0
Processing
Figure 11-2 Flowchart of Watchdog Timer
11-2
MSM64164C User's Manual Chapter 11 Watchdog Timer (WDT) Figure 11-3 shows the operation time chart of the watchdog timer.
q RESETS Write signal to WDTCON u Internal pointer Overflow Contents of WDTC 0 WDTINT (interrupt signal) 1.9 to 2 seconds Interrupt request w Data : 5 e A r 5 t A y 5 Trouble occurs.
5
Figure 11-3 Operation Time Chart of the Watchdog Timer
The operation of the watchdog timer is as follows: q The contents of the internal pointer and the Watchdog timer counter (WDTC) are reset by the system reset (RESETS). w "5H" is written to WDTCON (internal pointer 01). e "0AH" is written to WDTCON and the watchdog timer is reset (internal pointer 10). r "5H" is written to WDTCON (internal pointer 01). t "0AH" is written to WDTCON and the watchdog timer is reset (internal pointer 10). y "5H" is written to WDTCON (internal pointer 01). u When "0AH" is not written to WDTCON while the internal pointer is "1" (i.e. the CPU crashes and the watchdog timer is not reset), the watchdog timer interrupt (WDTINT) is generated by WDTC overflow. The internal pointer becomes "0" then.
11
11.4 Watchdog Timer Control Register (WDTCON) The watchdog timer control register (WDTCON) is a 4-bit special function register (SFR) to reset the watchdog timer.
b3 WDTCON (36H) (W) d3
b2 d2
b1 d1
b0 d0
11-3
MSM64164C User's Manual Chapter 11 Watchdog Timer (WDT)
11-4
Chapter 12
A/D Converter (ADC)
12
MSM64164C User's Manual Chapter 12 A/D Converter (ADC)
Chapter 12 A/D Converter (ADC)
12.1 Overview The MSM64164C has a built-in 2-channel RC oscillation method A/D converter. The A/D converter is composed of a 2-channel oscillation circuit, Counter A (CNTA0 to 4) which is a 4.8-digit decade counter, Counter B (CNTB0 to 3) which is a 14-bit binary counter and A/D converter control registers 0 and 1 (ADCON0, ADCON1). By counting oscillation frequencies due to resistance or capacitance connected to the RC oscillation circuit, the A/D converter converts resistance values or capacitance values to corresponding digital values. By using a thermistor or a humidity sensor as a resistance, a thermometer or a hygrometer can be constructed. By applying sensors to the 2-channel RC oscillation circuit, it is also possible to extend measurement ranges or measurement at two places.
12.2 Layout of A/D Converter Figure 12-1 shows the layout of the A/D converter.
12.3 Operation of A/D Converter As shown in Figure 12-1, the RC oscillation circuit can be made by connecting resistors and capacitors to each pin. Counter A (CNTA0 to 4) is a 4.8-digit decade counter (1/104 x 8) to count the system clock (CLK) which is the time reference and can count up to a maximum of 79,999. Counter B (CNTB0 to 3) is a 14-stage binary counter to count the oscillation clock (OSCCLK) of the RC oscillation circuit and can count up to a maximum of 16,383. Both Counter A and Counter B have the overflow flags (OVFA and OVFB) and overflow output generates the A/D converter interrupt request (ADINT). ADINT due to overflow of either Counter A or Counter B is selected by Bit 1 (SADI) of the A/D converter control register 0 (ADCON0). By resetting SADI to "0", overflow of Counter A is selected and by setting SADI to "1", overflow of Counter B is selected. The vector address of ADINT is at address 02FH. Bit 0 (EADC) of ADCON0 is a bit to select operation/halt of the A/D conversion. By resetting EADC to "0", the RC oscillation is halted and no counting is performed. By setting EADC to "1", the RC oscillation is begun and counting of the RC oscillation clock and the system clock is started. Various oscillation mode of the RC oscillation part is performed by the A/D converter control register 1 (ADCON1). The RC oscillation clock can be monitored by outputting to P4.3 in test function. For details of the test functions, refer to Chapter 15 "Test Circuit". 12
12-1
MSM64164C User's Manual Chapter 12 A/D Converter (ADC)
14-stage binary counter OSCCLK B0
a0-3
B1
a4-7
B2 1/214
a8-11
B3
a12-13
Differ- OVFB entiation
4
4
4
2
CLK
4.8-digit decade counter System clock (CLK) (32.768 kHz /400 kHz)
CRON
A0
a0-3
A1
A2 A3 1/(10 4 x 8)
a8-11
A4
Differ- OVFA entiation
Interrupt request ADINT
a4-7
a12-15 a16-18
4
4
4 EADC
4
3
CLK
Synchronization From
1 3 RESETS
SADI R
RESETS
P0.0 to P0.2 TST1, TST2, P0.3 1
CLK
0
Decoder
EADC R
8
OM 0 to 3
4 Internal data bus 8 OSCCLK
1
VSS VSS1/VSS2
2
TST1, TST2 MON
3
4
5
6
7
8
CROSC Monitor
VSS
VSS
Inside IC
IN0 RI0
CS0
CS0
CRT0
RT0-1
RT0
CT0
RS0
RT0 RS0
IN1
RI1
CS1 RT1 RS1
CS1 RT1 RS1
P4.3
Figure 12-1 Layout of A/D Converter
12-2
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) 12.3.1 RC Oscillation Circuit The A/D converter of the RC oscillation method performs A/D conversion by digitizing the ratio of a reference resistance (or capacitance) to a resistanc sensor, such as thermistor sensor (or capacitance sensor). By taking the ratio of oscillation frequencies of the reference to the sensor, it is possible to A/ D convert the characteristics of a sensor itself by canceling error factors intrinsic to the RC oscillation circuit. Consequently, it is necessary to oscillate the reference side and the sensor side with the same oscillation circuit and a pair of the reference side and the sensor side is usually used. Table 12-1 shows the oscillation mode by Bits 3 to 0 (OM3 to OM0) of the A/D converter control register (ADCON1). Figures 12-2 to 12-5 show the layout and values of the OM3 to 0 bits.
Table 12-1 Oscillation Mode by OM3 to OM0 Bits
ADCON1 OM3 OM2 OM1 OM0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 -- 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 -- CROSC0 output pins RS0 Z 1/0 Z Z 1/0 Z Z Z Z RT0 CRT0 CS0 Z Z 1/0 Z Z Z Z Z Z Z Z Z 1/0 0/1 Z Z Z Z Z 0/1 0/1 0/1 Z Z Z Z Z CROSC1 output pins RS1 Z Z Z Z Z 1/0 Z Z Z RT1 Z Z Z Z Z Z 1/0 Z Z IN0 external clock input mode RS0-CS0 oscillation RT0-CS0 oscillation RT0-1-CS0 oscillation RS0-CT0 oscillation RS1-CS1 oscillation RT1-CS1 oscillation CROSC1 oscillation mode CROSC0 oscillation mode Mode
Mode No.
0 1 2 3 4 5 6 7 8
12
IN1 external clock input mode --
Note: Z: High-impedance output 1/0, 0/1: Active output --: Arbitrary
12-3
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) Modes No.0 and No.7 in Table 12-1 measure the external clock which is input to the IN0 pin or the IN1 pin by halting the operation of the RC oscillation circuit. As shown in Table 12-1, no two oscillation circuits can operate simultaneously. This prevents interference to the oscillation operation when two are operated simultaneously. An equation between oscillation frequency (fOSCCLK), capacitance value (C) and resistance value (R). 1 fOSCCLK = tOSCCLK = kOSCCLK * C * R
where tOSCCLK is the period of the oscillation frequency, kOSCCLK is a proportionality constant and C * R is product of CS or CT and RS or RT . The value of kOSCCLK varies slightly depending on VDD (power supply voltage), RI, C and R and its standard values are listed in Table 122.
Table 12-2 Standard Value of kOSCCLK of RC Oscillation Circuit
VDD (V) 3 1.5 RIn (kW) 10 10 CSn, CTn (pF) 820 820 820 820 RSn, RTn (kW) 100 10 100 10 kOSCCLK (Typ.) 1.9 2.2 2.1 2.3
Note: n = 0, 1, 0-1
12-4
MSM64164C User's Manual Chapter 12 A/D Converter (ADC)
RS0 RT0
RS0 RT0
OM3 OM2 0 0 0 0
OM1 OM0 0 1 1 0
Oscillation mode Oscillation with reference resistance RS0 Oscillation with sensor RT0
CS0 RI0
CS0 IN0
Figure 12-2 Measurement of CROSC0 by a Resistance Sensor
RS0 RT0 RS0-1 CS0 RI0 RS0 RT0 CRT0 0 CS0 IN0 0 1 1 Oscillation with reference resistance RS0-1 OM3 OM2 0 0 0 0 OM1 OM0 0 1 1 0 Oscillation mode Oscillation with reference resistance RS0 Oscillation with sensor RT0
Figure 12-3 Measurement of CROSC0 by a Resistance Sensor (when two-point adjustment with two reference resistances)
RS0 RS0 OM3 OM2 0 0 CT0 CS0 RI0 CRT0 CS0 IN0 0 1 OM1 OM0 0 0 1 0 Oscillation mode Oscillation with reference capacitance CS0 Oscillation with sensor CT0
12
Figure 12-4 Measurement of CROSC0 by a Capacitance Sensor
RS1 RT1 RS1 RT1
OM3 OM2 0 0 1 1
OM1 OM0 0 1 1 0
Oscillation mode Oscillation with reference resistance RS1 Oscillation with sensor RT1
CS1 RI1
CS1 IN1
Figure 12-5 Measurement of CROSC1 by a Resistance Sensor Note: Unused pins should be left open. 12-5
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) 12.3.2 Counter A/B Reference Mode The conversion operation of the A/D converter is performed by one of the following two modes. * Counter A Reference Mode (SADI bit of ADCON0 = 0) This is the mode to set gate time by the system clock (CLK) and Counter A, to count the RC oscillation clock (OSCCLK) by Counter B with the gate time and to output contents of Counter B as a digital value. The digital value is proportional to the RC oscillation frequency. Counter B Reference Mode (SADI bit of ADCON0 = 1) This is the mode to set gate time by the RC oscillation clock (OSCCLK) and Counter B, to count the system clock (CLK) by Counter A with the gate time and to output contents of Counter A as a digital value. The digital value is inverse proportional to the RC oscillation frequency.
*
(1) Operation of Counter A Reference Mode Figure 12-6 shows the operating timing of Counter A reference mode. Counter A reference mode is performed by the following procedure: (refer to Figure 12-6) [1] Subtract "nA0" (the count value) from the maximum value + 1 (80,000) and set that value to Counter A (CNTA4 to 0). The count value, "nA0", indicates the gate time. Counter A 80,000 - nA0 [2] Clear Counter B (CNTB3 to 0) to 0000H. Counter B 0000H [3] Set the OM 3 to 0 bits of ADCON1 to a necessary oscillation mode (refer to Table12-1). [4] Write "1H" to ADCON0 (SADI = 0, EADC = 1). Note: The order of [1] to [3] is arbitrary.
By [4], A/D conversion starts. Counter A starts counting the system clock (CLK) when EADC is set to "1" and the CRON signal that synchronizes with the falling of the system clock is set to "1". When Counter A overflows, [5] the EADC bit is automatically reset and the counting is finished. At the same time, [6] the A/D converter interrupt request signal (ADINT) becomes "1" to generate the A/D converter interrupt request. When the CRON signal is set to "1", the RC oscillation is started and Counter B starts counting the RC oscillation clock (OSCCLK). When Counter A overflows and the EADC bit is automatically reset, the counting of counter B is finished.
12-6
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) The last count value of "nB0" at Counter B is the count value of OSCCLK during the gate time "nA0 * tSYSCLK" and is expressed by tSYSCLK tOSCCLK
nB0 = nA0 * .
.
fOSCCLK
where tSYSCLK is the period of CLK and tOSCCLK is the period of OSCCLK. In other words, "nB0" is proportional to the RC oscillation frequency (fOSCCLK).
[4]
EADC
[5] tSYSCLK
CLK
CRON
[1] Overflow
Counter A
(80000-nA0)
(+1)
(+2)
(+3)
79996
79997 79998 79999
00000
Gate time nA0 * t SYSCLK tOSCCLK RC oscillation circuit input waveform IN0/IN1 OSCCLK
12
[2]
Counter B
0000H
0001H
0002H nB0 * tOSCCLK
nB0-2
nB0-1
nB0
ADINT nA0: reference count value nB0: measured count value
[6] Interrupt request
Figure 12-6 Operating Timing of Counter A Reference Mode
12-7
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) (2) Operation of Counter B Reference Mode Figure 12-7 shows the operating timing of Counter B reference mode. Counter B reference mode is performed by the following procedure: (refer to Figure 12-7) [1] Subtract "nB1" (the count value) from the maximum value + 1 (4000H) and set the result to Counter B (CNTB3 to 0). The count value, "nB1", denotes the gate time. Counter B 4000 - nB1 [2] Clear Counter A (CNTA4 to 0) to 0000H. Counter A 0000H [3] Set the OM 3 to 0 bits of ADCON1 to a necessary oscillation mode (refer to Table 12-1). [4] Write "3H" to ADCON0 (SADI = 1, EADC = 1). Note: The order of [1] to [3] is arbitrary.
By [4], A/D conversion starts. Counter B starts counting the RC oscillation clock (OSCCLK) when the EADC bit is set to "1" and the CRON signal (signal that synchronizes with the falling of the system clock) is set to "1". When Counter B overflows, [5] the EADC bit is automatically reset and the conversion is finished. At the same time, [6] the A/D converter interrupt request signal (ADINT) becomes "1" to generate the A/D converter interrupt request. When the CRON signal is set to "1", Counter A starts counting the system clock (CLK). When Counter B overflows and the EADC bit is automatically reset, the counting of counter A is finished. The last count value of "nA1" at Counter A is the count value of SYSCLK during the gate time "nB1* tOSCCLK" and is expressed by
.
nA1 = nB1 * .
tOSCCLK tSYSCLK
1 fOSCCLK
In other words, "nA1" is inversely proportional to the RC oscillation frequency (fOSC).
12-8
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) Note: n = 0, 1, 0-1
[4] [5] EADC
tSYSCLK
CLK
CRON [2]
Counter A
00000
00001
00002
00003
nA1-3
nA1-2
nA1-1
nA1
nA1 * tSYSCLK tOSCCLK RC oscillation circuit input waveform IN0/IN1
OSCCLK [1] overflow Counter B (4000-nB1) (+1) (+2) 3FFDH 3FFEH 3FFFH 0000H
12
nB1 * tOSCCLK Gate time ADINT
nA1: measured count value nB1: reference count value
[6] Interrupt request
Figure 12-7 Operating Timing of Counter B Reference Mode
12-9
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) 12.3.3 Example of Usage of A/D Converter The method to perform A/D conversion of sensor values by using Counter A reference mode and Counter B reference mode is explained by taking temperature measurement with a thermistor as an example. Figure 12-8 shows the layout of RC oscillation circuit.
Reference resistance RS0 Thermistor RT0 MSM64164C-XXX RS0 RT0
CS0 RI0
CS0 IN0
Figure 12-8 Layout of RC Oscillation Circuit of a Thermistor Using CROSC0 Figure 12-9 shows the temperature characteristics of the resistance value, RT0, of the thermistor.
Thermistor resistance RT0
RT0 = f(T)
Digital value nT0
nT0 = K * RT0 = K * f(T)
Temperature T
RT0
Figure 12-9 Temperature Characteristics of Thermistor RT0 is expressed as a function of temperature T as RT0 = f (T)
Figure 12-10 A/D Conversion Characteristics
Figure 12-10 shows the ideal characteristics of A/D conversion taking RT0 as an analog quantity and the A/D conversion value nT0 is completely proportional to RT0. The value of nT0 is expressed by temperature T and the proportionality factor K as 12-10
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) nT0 = K * RT0 = K * f (T) - - - - - equation (a)
Consequently, by performing conversion processing corresponding to the characteristics shown by Figure 12-9 to nT0, it is possible to express temperatures by digital values. The conversion method from an analog value of RT0 to a digital value of nT0 is now explained. To convert RT0 to a digital value, the ratio of oscillation frequencies of RT0 to RS0 (ideal if independent of temperature) is used. This is to cancel the error factors of the oscillation characteristics. As shown in Figures 12-9 and 12-11, RT0 depends on temperature T and RS0 is always constant regardless of temperature T. The oscillation characteristics, fOSC-T, using these resistances is ideal if the solid lines of Figures 12-12 and 12-13 can be realized. However, in reality, the dotted lines are obtained due to error factors of the temperature characteristics of the IC and others. Since the conditions of fOSC(RT0) and fOSC(RS0) are about the same except the resistance, their error should be similar each to other and consequently, if the ratio of one to the other is taken, the error should be canceled. The ratio of fOSC(RT0) to fOSC(RS0) corresponds to the A/D conversion value of nT0 which, ideally, depends solely on RT0.
Reference resisgtance value RS0
f OSC (RT0)
With error due to factors other than RT0
Ideal f OSC (RS0) = Temperature T Temperature T 1 KOSCCLK * CS0 * RT0
12
Figure 12-11 Temperature Characteristics of Thermistor
Figure 12-12 Oscillation Characteristics of Thermistor
f OSC (RS0)
With error due to factors other than RS0
Ideal Temperature T
f OSC (RS0) =
1 KOSCCLK * CS0 * RS0
Figure 12-13 Oscillation Characteristics of Reference Resistance
12-11
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) Figure 12-14 shows the conversion to digital values from the RT0 values, i.e. one cycle time chart of temperature measurement. One cycle of A/D conversion needs to be composed of two steps shown in Figure 12-14 because the reference resistance and the thermistor must be oscillated independently when taking the ratio of them.
In this example, those two steps are taken by the following combination: First step = RC oscillation by RS0 with A counter reference Second step = RC oscillation by RT0 with B counter reference
Various other methods are possible besides the one above. In the above method, the operating time by the second step varies by the value of thermistor RT0. However, if it is necessary to avoid such variation, the following combination is recommended: First step = RC oscillation by RS0 with B counter reference Second step = RC oscillation by RT0 with A counter reference
In the following, the procedure of A/D conversion will be explained taking Figure 12-14 as an example.
12-12
MSM64164C User's Manual Chapter 12 A/D Converter (ADC)
[1] System clock(CLK) ADCON1 (Bits 2 to 0) 400 kHz 32.768 kHz [4] 1H [5] ADCON0 (Bits 1, 0) 1H (SADI = 0, EADC = 1) nA0 * tSYSCLK = nB0 * tOSCCLK (RS0) RC oscillation state (CROSC0) 0.366 second Stop Oscillates at RS0 (A counter reference) Stop Oscillates at RT0 (B counter reference) Stop [c] 0H [9] 3H (SADI = 1, EADC = 1) nB0 * tOSCCLK (RT0) = nA1 * tSYSCLK [8] 2H [f] 2H
[2] CNTA4 to 0 68,000 [3] CNTB3 to 0 0000H (Count-up by OSCCLK (RS0)) [a] ADC interrupt request ADINT (Count-up by CLK)
Overflow 0000000000 (Count-up by CLK) nA1
Overflow nB0 [7] (Count-up by OSCCLK (RT0)) 4000H-nB0 [d] INT generation [10] 0000H
INT generation [6]
12
HLT [b] [e]
Notes: nA0 = 12,000, tSYSCLK = 1/32768 Hz, [1] to [10]: software processing, [a] to [f ] : hardware processing Figure 12-14 Time Chart of One Cycle of Temperature Measurement
12-13
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) [1] Set the system clock to 32.768 kHz (Write 0H to FCON), if using 400 kHz clock as system clock. [2] Set "80,000-nA0" to Counter A. Note: nA0 is taken as 12,000 in order to set the gate time nA0 * tSYSCLK of oscillation mode of the reference resistance RS0 as 0.366 second. The value of nA0 depends on the size of quantum error of A/D conversion and the larger nA0, the smaller the error. [3] Clear Counter B to "0000H". [4] Write "1H" to ADCON1 and set it to oscillation mode with reference resistance RS0. Note: The order of [1] to [4] is arbitrary. [5] Write "1H" to ADCON0 and start A/D conversion in Counter A reference mode. [6] Set the HLT bit of HALT register to "1" for halt mode. Note: By selecting halt mode, noise to the RC oscillation circuit may be reduced. In regular usage, halt mode is recommended during RC oscillation operation.
The RC oscillation circuit (CROSC0) continues oscillation with reference resistance RS0 for about 0.366 second at this time and when Counter A overflows, [a] the ADINT signal is set to "1" and the A/D converter interrupt request is generated. By the generation of the interrupt request, [b] halt mode is released and [c] the A/D conversion operation is stopped (the EADC bit = 0). At this moment, Counter A is in 00000 state. The contents of Counter B are expressed as nB0 = nA0 * tSYSCLK tOSCCLK(RS0) - - - - - equation (b)
[7] Calculate "4000H-nB0" by the contents "nB0" of Counter B and set that value to Counter B. Note: Although clearing of Counter A is needed, additional processing is not necessary as it is already in "00000" state. [8] Write "2H" to ADCON1 and start oscillation mode with thermistor RT0. [9] Write "3H" to ADCON0 and start A/D conversion in Counter B reference mode. [10] Set the HLT bit of HALT register to "1" to start halt mode.
12-14
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) The RC oscillation circuit (CROSC0) oscillates with thermistor RT0 from this time until overflow of Counter B. This period is equivalent to product of "nB0" from first step and tOSCCLK(RT0) due to RT0. When Counter B overflows, [d] the ADINT signal is set to "1" and the A/D converter interrupt request is generated. By the generation of the interrupt request, [e] halt mode is released and [f] the A/D conversion operation is stopped (the EADC bit = "0").The contents of Counter A becomes the A/D conversion value of nA1 and is expressed by the following:
nA1 = nB0 *
tOSCCLK(RT0) tSYSCLK
- - - - - equation (c)
By equations (b) and (c), nA1 is expressed as tOSCCLK(RT0) tOSCCLK(RS0)
nA1 = nA0 *
- - - - - equation (d)
where tOSCCLK (RS0) is the period of the oscillation clock by reference resistance RS0 and tOSCCLK (RT0) is the period of the oscillation clock by thermistor RT0. The oscillation period is expressed ideally as
tOSCCLK (RS0) = kOSCCLK * CS0 * RS0 - - - - - equation (e) tOSCCLK (RT0) = kOSCCLK * CS0 * RT0
12
By substituting equation (e) to equation (d), nA1 is expressed as
nA1 = nA0 *
RT0 RS0
As "nA0" (12,000 in this example) and RS0 are fixed constants, "nA1" becomes a digital value proportional to RT0. This "nA1" is equivalent to "nT0" in equation (a). The obtained "nA1" must be further converted to a temperature display value depending on the temperature-resistance characteristics of the thermistor in a program.
12-15
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) 12.3.4 RC Oscillation Monitor By setting Bit 2 (MON) of the Port 43 control register (P43CON) to "1", the RC oscillation clock (OSCCLK) can be output to P4.3. By using the test functions, the RC oscillation clock can be output at P4.3 without using software. For details of the test functions, refer to Chapter 15 "Test Circuit". The RC oscillation monitor is useful when checking the characteristics of the RC oscillation circuit. For instance, it is possible to measure the relationship between sensors such as a thermistor and an oscillation frequency. For example, by examining the relationship between ambient temperature of a thermistor built-in RC oscillation circuit and oscillation frequencies of the thermistor RT0 and the reference resistance RS0, it is possible to obtain the conversion coefficient from the value of nA1 to the temperature display values.
12-16
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) 12.4 Registers Related to A/D Converter (1) A/D converter control register 0 (ADCON0) The A/D converter control register 0 (ADCON0) is a 4-bit special function register (SFR) that selects start/stop of RC oscillation of the A/D converter and the A/D converter interrupt by Counter A or Counter B.
b3 ADCON0 (2AH) (R/W) -----*
b2 -----*
b1 SADI
b0 EADC
Selection of A/D interrupt 0: Interrupt request by Counter A overflow (initial value) 1: Interrupt request by Counter B overflow Selection of A/D conversion start/stop 0: Stop of RC oscillation (initial value) 1: RC oscillation start *Reserved bit: "1" is always read. Not valid for write.
Bit 1: SADI This bit selects the A/D converter interrupt request (ADINT) by overflow of either Counter A or Counter B. By resetting SADI to "0", the interrupt request by overflow of Counter A is selected and by setting SADI to "1", the interrupt request by overflow of Counter B is selected. At system reset, SADI is reset to "0". Bit 0: EADC This bit selects start/stop of conversion of the A/D converter. When set to "1", A/D conversion is started and when reset to "0", A/D conversion is stopped. When either Counter A or Counter B overflows while EADC is set to "1" to start counting, the EADC bit is set to "0" automaticaly. Consequently, EADC indicates that the measurement is in progress. At system reset, the EADC bit is reset to "0" and the system is in stop state.
12
12-17
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) (2) A/D converter control register 1 (ADCON1) The A/D converter control register 1 (ADCON1) is a 4-bit special function register (SFR) to select oscillation mode of the RC oscillation circuit.
b3 ADCON1 (2BH) (R/W) OM3
b2 OM2
b1 OM1
b0 OM0
Selection of oscillation mode OM0 OM1 OM2 OM3 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : IN0 pin external clock input mode (initial value) 1 : RS0-CS0 oscillation mode 0 : RT0-CS0 oscillation mode 1 : RT(0-1)-CS0 oscillation mode 0 : RS0-CT0 oscillation mode 1 : RS1-CS1 oscillation mode 0 : RT1-CS1 oscillation mode 1 : IN1 pin external clock input mode - : Unavailable
12-18
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) (3) A/D converter counter A registers (CNTA0 to 4) The A/D converter counter A registers (CNTA0 to 4) are 4-bit special function registers (SFRs) to read/write the Counter A.
Note: CNTA0 to CNTA3 are decimal counters and can handle only data from 0H to 9H.
b3 CNTA0 (20H) (R/W) a3
b2 a2
b1 a1
b0 a0
Bits 0 to 3 of Counter A
b3 CNTA1 (21H) (R/W) a7
b2 s6
b1 a5
b0 a4
Bits 4 to 7 of Counter A
b3 CNTA2 (22H) (R/W) a11
b2 a10
b1 a9
b0 a8 12
Bits 8 to 11 of Counter A
b3 CNTA3 (23H) (R/W) a15
b2 a14
b1 a13
b0 a12
Bits 12 to 15 of Counter A
b3 CNTA4 (24H) (R/W) Bits 16 to 18 of Counter A *Reserved bit: "1" is always read. Not valid for write. -----*
b2 a18
b1 a17
b0 a16
12-19
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) (4) A/D converter counter B registers (CNTB0 to 3) The A/D converter counter B registers (CNTB0 to 3) are 4-bit special function registers (SFRs) to read/write the Counter B.
b3 CNTB0 (26H) (R/W) b3
b2 b2
b1 b1
b0 b0
Bits 0 to 3 of Counter B
b3 CNTB1 (27H) (R/W) b7
b2 b6
b1 b5
b0 b4
Bits 4 to 7 of Counter B
b3 CNTB2 (28H) (R/W) b11
b2 b10
b1 b9
b0 b8
Bits 8 to 11 of Counter B
b3 CNTB3 (29H) (R/W) Bits 12 and 13 of Counter B *Reserved bit: "1" is always read. Not valid for write. -----*
b2 -----*
b1 b13
b0 b12
12-20
MSM64164C User's Manual Chapter 12 A/D Converter (ADC) Tables 12-3 and 12-4 list A/D converter-related registers and pins.
Table 12-3 List of A/D Converter-Related Registers
Register name A/D converter control register 0 A/D converter control register 1 A/D converter counter A register 0 A/D converter counter A register 1 A/D converter counter A register 2 A/D converter counter A register 3 A/D converter counter A register 4 A/D converter counter B register 0 A/D converter counter B register 1 A/D converter counter B register 2 A/D converter counter B register 3
Symbol ADCON0 ADCON1 CNTA0 CNTA1 CNTA2 CNTA3 CNTA4 CNTB0 CNTB1 CNTB2 CNTB3
Address 2AH 2BH 20H 21H 22H 23H 24H 26H 27H 28H 29H
Read/Write R/W
Byte access
Value at system reset 0CH
Yes R/W R/W Yes R/W R/W Yes R/W R/W R/W Yes R/W R/W Yes R/W 0CH 0H 0H No 0H 8H 0H 0H 0H 0H 0H
Table 12-4 List of A/D Converter-Related Pins 12
Pin name Pin No. Pad No. Input/Output GS-BK GS-K TS-K 33 34 35 36 37 41 40 39 38 31 32 33 34 35 39 38 37 36 33 34 35 36 37 41 40 39 38 Output Output Output Output Input Output Output Output Input Note
RT0 CRT0 RS0 CS0 IN0 RT1 RS1 CS1 IN1
Resistance sensor connection pin to measure Channel 0 Resistance/capacitance sensor connection pin to measure Channel 0 Reference resistance connection pin for Channel 0 Reference capacitance connection pin for Channel 0 Oscillation input pin for Channel 0 Resistance sensor connection pin to measure Channel 1 Reference resistance connection pin for Channel 1 Reference capacitance connection pin for Channel 1 Oscillation input pin for Channel 1
12-21
MSM64164C User's Manual Chapter 12 A/D Converter (ADC)
12-22
Chapter 13
LCD Driver (LCD)
13
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Chapter 13 LCD Driver (LCD)
13.1 Overview The MSM64164C has a built-in LCD driver. There are three types of driving methods, i.e. 1/4 duty, 1/3 duty and 1/2 duty. Maximum of 120 segments can be driven for 1/4 duty, 93 segments for 1/3 duty and 64 segments for 1/ 2 duty, respectively. The mask option can select either a common driver or a segment driver for each LCD driver. The mask option can also specify assignment of each bit of the display register to each segment. On the one hand, all the display resisters to be used must be selected by the mask option. If not, note that the display registers can not be used. Refer to Appendix F on the mask options. L26 to L33 of the LCD driver can become output ports by the mask option. The following is the relation among the duty, the bias method and the maximum segment number. 1/4 duty 1/3 bias method (VDD = 0 V, VSS1 = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V) - 120 segments 1/3 duty 1/3 bias method (VDD = 0 V, VSS1 = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V) - 93 segments 1/2 duty 1/2 bias method (VDD = 0 V, VSS1 = -1.5 V, VSS2 = -3.0 V) - 64 segments 13.2 Layout of LCD Driver
The layout of the LCD driver is shown in Figure 13-1. Figures 13-2 and 13-3 show the LCD driver and its peripheral circuits.
Internal data bus
13
Mask option circuit
DPSCON
Display register (DSPR0 to 30) 31 nibbles
Timing generation circuit
LCD driver circuit (34)
Bias generation circuit (BIAS)
L0
L33
C1
C2
VSS1
VSS2
VSS3
Figure 13-1 Layout of LCD Driver 13-1
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
L0 (segment output)
VDD VSS1 VSS2 VSS3 LCD (Frame clock)
OUT LCD driver C D COM/SEG
Common timing signals CM4 CM3 CM2 CM1 D Display register DSPR LR RESETS Common output select "1" (Mask option) "0" b0 b1 b2 b3 One of 10 is selected. b4 b5 b6 b7
Display register bit select (mask option) Display register address select (mask option)
Q
D LR
Q
D LR
Q
D LR
Q
Internal data bus
Write Read BANK0 RA7
Data memory address bus
RA6 RA5 RA4 RA3 RA2 RA1 RA0 BYTE 6 input AND
Bits 0 and 1 of DSPR0 are assigned to commons 1 and 2 of L0
Bits 3 and 4 of DSPR1 are assigned to commons 3 and 4 of L0
Figure 13-2 LCD Driver and Display Register (Circuit layout of L0 to L25: One output)
13-2
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
L26 (Common output)
VDD VSS1 VSS2 VSS3
OUT LCD driver C D COM/SEG
LCD (Frame clock)
"1"
Output port select (mask option) Common timing signals "0" CM4 CM3 CM2 CM1 D Display register DSPR LR RESETS Common output select "1" (Mask option) "0" b0 b1 b2 b3 One of 10 is selected. b4 b5 b6 b7 Display register bit select (mask option) LR LR LR Q D Q D Q D Q
Internal data bus
13
Write Read BANK0 RA7 Data memory address bus RA6 RA5 RA4 RA3 RA2 RA1 RA0 BYTE 6 input AND
Common 1 is assigned to L26
Figure 13-3 LCD Driver and Display Register (Circuit layout of L26 to L33: One output)
13-3
Display register address select (mask option)
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) 13.3 Operation of LCD Driver The LCD driver outputs LCD square waveforms based on data written to the display registers. The mask option can select the address of the display register, bit assignment and a segment driver/a common driver. 4 segment display registers per one segment driver are assigned. All the 4 segments are used for 1/4 duty, 3 segments for 1/3 duty and 2 segments for 1/2 duty, respectively. In Figure 13-2, the L0 output is the segment driver. Bits 0 and 1 of DSPR0 are assigned to the segment corresponding to Commons 1 and 2 and Bits 2 and 3 of DSPR1 are assigned to the segment corresponding to Commons 3 and 4. In Figure 13-3, the L26 output is the common 1 driver. Thus, it is possible to assign arbitrary display registers and bits to arbitrary segment by the mask option. Duty of the LCD driver is selected by the display control register (DSPCON).
13.4 Display Control Register (DSPCON) The display control register (DSPCON) is a 4-bit special function register (SFR) to control the duty ratio of the LCD driver.
b3 DSPCON (1EH) (R/W) -----*
b2 -----*
b1 DUTY1
b0 DUTY0
Duty selection DUTY1 DUTY0 0 0 : 1/4 duty (initial value) 0 1 : 1/3 duty 1 0 : 1/2 duty 1 1 : disabled *Reserved bit: "1" is always read out. Not valid for write.
Bits 1 and 0: DUTY1, DUTY0 DUTY1 and DUTY0 are bits to select the duty ratio of the LCD driver. They are reset to "0" at system reset and 1/4 duty is selected. Setting both DUTY1 and DUTY0 to "1" is disabled.
13-4
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) 13.5 Display Registers 0 to 30 (DSPR0 to 30) The display registers 0 to 30 (DSPR0 to 30) are data registers for segment output of the LCD driver. They are assigned to addresses 40H to 5EH of Bank 0.
b3 DSPR30 (5EH) (R/W) d
b2 c
b1 b
b0 a Segment output data
b3 DSPR29
b2 c
b1 b
b0 a Segment output data
. . . . . . . . . .
DSPR0
(5DH) (R/W)
d
13 b3 (40H) (R/W) d b2 c b1 b b0 a Segment output data
It is possible to assign an arbitrary bit of the display register to an arbitrary segment driver by the mask option. At system reset, all the display registers are reset to "0" and LCD segments are all off. Those bits set to "1" in the display register are in on state on the LCD segment while those bits reset to "0" are in off state. For details of assignment of each bit of the display register for the display segment, refer to "List of LCD Driver Mask Option" in "Appendix F: Mask Options".
13-5
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) 13.6 Output Port Selection by Mask Option Each of the 8 pins of L26 to L33 of the LCD driver can be selected as an output port by the mask option. When these pins are selected as output ports, one port pin is assigned to one bit of the display register. Figure 13-4 shows an example of assigning DSPR0 to L26 to L29 as an output port using an equivalent circuit. The output voltage level at this time is at the VDD level at "H" output and is at the VSS level when outputting "L".
Internal data bus 4 0 1 2 3 L26/P5.0 DSPR0 L27/P5.1 L28/P5.2 L29/P5.3
Read/Write DSPR0
VSS
Figure 13-4 Equivalent Circuit when DSPR0 is Assigned to L26 to L29 as an Output Port
Only DSPR0 and DSPR1 can be used as output ports. Other registers cannot be used as output ports. For bit assignment of the display register for output pins and selection of output ports, refer to "List of LCD Driver Mask Options" in "Appendix F: Mask Options".
13-6
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) 13.7 Bias Generation Circuit for LCD Driver (BIAS) The bias generation circuit for LCD (BIAS) generates bias voltages of -1.5 V, -3.0 V and -4.5 V for the LCD driver by rising or dropping the power supply voltage by externally installing capacitors. Figure 13-5 shows the layout of the bias generation part.
MSM64164C (0 V) VDD (-1.5 V) (-3.0 V) Bias generation circuit
VDD
1.5 V
VSS1 VSS2 VSS3
Ca Cb
1 kHz (from the time base counter)
(-4.5 V)
C1 C12 C2 VSS1 VSS2 VSS3 To the LCD driver
(a) 1.5 V spec.
MSM64164C (0 V) VDD
VDD
13
Ca 3.0 V Cb VSS1 VSS2 VSS3 (-1.5 V) (-3.0 V) Bias generation circuit
1 kHz (from the time base counter)
(-4.5 V)
C1 C12 C2 VSS1 VSS2 VSS3 To the LCD driver
(b) 3.0 V spec. Figure 13.5 Layout of the Bias Generation Circuit (Ca, Cb, C12 = 0.1 F) Notes: In a case that LCD driver is not used, it is unnecessary to connect capacitors Ca, Cb and C12 and the corresponding pins should be left open. In a case that LCD duty ratio is selected to 1/2 (1/2 duty), it is unnecessary to connect capacitor Cb to VSS3 pin. 13-7
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) 13.8 LCD Driver Output Waveforms Figures 13-6 (a) to (c) show 1/4 duty of output waveforms of the LCD driver and Figures 137 (a) and (b) show 1/3 duty and Figures 13-8 (a) and (b) show 1/2 duty.
Frame frequency 32 Hz
VDD VSS1 COM1 VSS2 VSS3 VDD COM2 VSS1 VSS2 VSS3 VDD COM3 VSS1 VSS2 VSS3 VDD VSS1 COM4 VSS2 VSS3
Figure 13-6 (a) 1/4 Duty Common Driving Waveforms (1/3 bias)
13-8
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Frame frequency 32 Hz seg n : OFF
system
COM1 COM2 COM3 COM4
VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3
: OFF : OFF : OFF
seg n COM1 : ON COM2 COM3 COM4 COM1 COM2 COM3 COM4 COM1 COM2 COM3 COM4
system system system system
: OFF : OFF : OFF
seg n : OFF : ON : OFF : OFF seg n : ON : ON : OFF : OFF
seg n COM1 : OFF COM2 COM3 COM4 COM1 COM2 COM3 COM4 : OFF : ON : OFF seg n : ON
system
13
VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3
: OFF : ON : OFF
seg n COM1 : OFF COM2 COM3 COM4
system system
: ON : ON : OFF
seg n COM1 : ON COM2 COM3 COM4 : ON : ON : OFF
Figure 13-6 (b) 1/4 Duty Common Driving Waveforms (1/3 bias)
13-9
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Frame frequency 32 Hz seg n : OFF
system
COM1 COM2 COM3 COM4
VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3 VDD VSS1 VSS2 VSS3
: OFF : OFF : ON
seg n COM1 : ON COM2 COM3 COM4 COM1 COM2 COM3 COM4 COM1 COM2 COM3 COM4
system system system system system system system
: OFF : OFF : ON
seg n : OFF : ON : OFF : ON seg n : ON : ON : OFF : ON
seg n COM1 : OFF COM2 COM3 COM4 COM1 COM2 COM3 COM4 : OFF : ON : ON seg n : ON : OFF : ON : ON
seg n COM1 : OFF COM2 COM3 COM4 : ON : ON : ON
seg n COM1 : ON COM2 COM3 COM4 : ON : ON : ON
Figure 13-6 (c) 1/4 Duty Common Driving Waveforms (1/3 bias)
13-10
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Frame frequency 42.67 Hz
VDD VSS1 COM1 VSS2 VSS3 VDD VSS1 COM2 VSS2 VSS3 VDD VSS1 COM3 VSS2 VSS3
Figure 13-7 (a) 1/3 Duty Common Driving Waveforms (1/3 bias)
13
13-11
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Frame frequency 42.67 Hz seg n : OFF system : OFF : OFF
COM1 COM2 COM3
VDD VSS1 VSS2 VSS3
system
COM1 COM2 COM3
seg n : ON : OFF : OFF
VDD VSS1 VSS2 VSS3
system
seg n COM1 : OFF COM2 COM3 : ON : OFF
VDD VSS1 VSS2 VSS3
system
seg n COM1 : ON COM2 COM3 : ON : OFF
VDD VSS1 VSS2 VSS3
system
COM1 COM2 COM3
seg n : OFF : OFF : ON
VDD VSS1 VSS2 VSS3
seg n COM1 : ON system COM2 COM3 : OFF : ON
VDD VSS1 VSS2 VSS3
system
COM1 COM2 COM3
seg n : OFF : ON : ON
VDD VSS1 VSS2 VSS3
system
seg n COM1 : ON COM2 COM3 : ON : ON
VDD VSS1 VSS2 VSS3
Figure 13-7 (b) 1/3 Duty Common Driving Waveforms (1/3 bias)
13-12
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
Frame frequency 32 Hz
VDD COM1 VSS1 VSS2
VDD COM2 VSS1 VSS2
Figure 13-8 (a) 1/2 Duty Common Driving Waveforms (1/2 bias)
Frame frequency 32 Hz
seg
n
VDD VSS1 VSS2
COM1 COM2
system
: OFF : OFF
seg COM1 COM2
n
VDD VSS1 VSS2
13
system
: ON : OFF
seg COM1 COM2
n
VDD VSS1 VSS2
system
: OFF : ON
seg COM1 COM2
n
VDD VSS1 VSS2
system
: ON : ON
Figure 13-8 (b) 1/2 Duty Common Driving Waveforms (1/2 bias)
13-13
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) Tables 13-1 and 13-2 show the list of LCD driver-related registers and pins.
Table 13-1 (a) List of LCD Driver-Related Registers
Register name Display control register Display register 0 Display register 1 Display register 2 Display register 3 Display register 4 Display register 5 Display register 6 Display register 7 Display register 8 Display register 9 Display register 10 Display register 11 Display register 12 Display register 13 Display register 14 Display register 15 Display register 16 Display register 17 Display register 18 Display register 19 Display register 20 Display register 21 Display register 22 Display register 23 Display register 24 Display register 25
Symbol DSPCON DSPR0 DSPR1 DSPR2 DSPR3 DSPR4 DSPR5 DSPR6 DSPR7 DSPR8 DSPR9 DSPR10 DSPR11 DSPR12 DSPR13 DSPR14 DSPR15 DSPR16 DSPR17 DSPR18 DSPR19 DSPR20 DSPR21 DSPR22 DSPR23 DSPR24 DSPR25
Address 1EH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Byte access No Yes
Value at system reset 0CH 0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
Yes
0H 0H
13-14
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) Table 13-1 (b) List of LCD Driver-Related Registers
Register name Display register 26 Display register 27 Display register 28 Display register 29 Display register 30
Symbol DSPR26 DSPR27 DSPR28 DSPR29 DSPR30
Address 5AH 5BH 5CH 5DH 5EH
Read/Write R/W
Byte access Yes
Value at system reset 0H 0H 0H
R/W R/W Yes R/W R/W No
0H 0H
Note : The display registers 0 through 30 are registers that can not be used without selection by the mask option. All the display registers to be used must be allocated on the LCD driver mask option table per bit. (Refer to Appendix F on the mask options.)
13
13-15
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) Table 13-2 (a) List of LCD Driver-Related Pins
Pin No. GS-K Pad No. Input/Output TS-K 40 42 43 44 45 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 46 47 48 49 50 51 52 53 54 42 44 45 46 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 51 52 53 54 55 56 ---- ---- ---- ---- ---- Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output LCD segment/common signal output pins
Pin name VSS1 VSS2 VSS3 C1 C2 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25
GS-BK 42 44 45 46 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 51 52 53 54 55 56
Function Negative side power supply (at 1.5 V spec.) Bias output for driving LCD (-1.5 V) (at 3.0 V spec.) Negative side power supply (at 3.0 V spec.) Bias output for driving LCD (-3.0 V) (at 1.5 V spec.) Bias output for driving LCD (-4.5 V) Capacitor connection pin for LCD driving bias generation
13-16
MSM64164C User's Manual Chapter 13 LCD Driver (LCD) Table 13-2 (b) List of LCD Driver-Related Pins
Pin No. Pin name GS-BK 57 58 59 60 61 62 63 64 GS-K Pad No.Input/Output TS-K 55 56 57 58 59 60 61 62 57 58 59 60 61 62 63 64 Output Output Output Output Output Output Output Output Function
L26/P5.0 L27/P5.1 L28/P5.2 L29/P5.3 L30/P6.0 L31/P6.1 L32/P6.2 L33/P6.3
LCD driver output pins. Can become output ports by the mask option.
13
13-17
MSM64164C User's Manual Chapter 13 LCD Driver (LCD)
13-18
Chapter 14
Constant Voltage Circuit for Logic Power Supply (VR)
14
MSM64164C User's Manual Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR)
Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR)
14.1 Overview The MSM64164C has a built-in constant voltage circuit for the logic power supply (VR).
14.2 Layout of Constant Voltage Circuit for Logic Power Supply Figure 14-1 shows the layout of the constant voltage circuit for the logic power supply.
MSM64164C VDD
RESETS Logic circuit * CPUCLK * BUPF VSSL VSSL 1.3 V (Typ.) + - VR SW1 ON VSS1/VSS2 OFF CL
1.5/3.0 V
14 * BUPF indicates output of the backup flag. CPUCLK indicates output of the system clock selection bit. Figure 14-1 Constant Voltage Circuit for Logic Power Supply
In Figure 14-1, the "CL" capacitor is a noise smoothening condenser on the VSSL line of the logic circuit and it is necessary to install the capacitor of 0.05 F to 0.2 F for CL. SW1 in the Figure becomes ON state when (1) the system clock selection bit (CPUCLK) is set to "1", (2) in system reset mode or (3) the backup flag (BUPF) is set to "1". When developing an application in which CPUCLK or BUPF is set to "1" in the 3.0 V specifications, install the capacitor of 0.47 F 30% for CL. In other cases, install the capacitor of 0.05 F to 0.2 F for CL.
14-1
MSM64164C User's Manual Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR) 14.3 Operation of Constant Voltage Circuit for Logic Power Supply The constant voltage for the logic power supply (VR) outputs a constant voltage of V DD - 1.3 V (Typ.) to the VSSL pin and supplies VSSL level as the power supply of the logic circuit. At system reset or when selecting 400 kHz RC oscillation output as the system clock, the VSSL output is forced to be switched to either VSS1 or VSS2. In normal operation mode, the VSSL output is switched to either VSS1 or VSS2 when Bit 0 (BUPF) of the backup control register (BUPCON) is set to "1" while the crystal oscillation output is the system clock. When resetting BUPF to "0", the VSSL output becomes approximately VDD-1.3 V. In system reset mode, BUPF is reset to "0" but as shown in Figure 14-2, the VSSL output becomes either VSS1 or VSS2 level for 0.5 second after crystal oscillation started. Table 14-1 shows output state of VSSL by the CPUCLK bit, BUPF flag and system reset mode and Figure 14-2 shows output status of VSSL in system reset mode. Table 14-1 Output State of VSSL
System reset mode 0.5 sec duration ---- ---- ----
CPUCLK flag ---- 0 0 1
BUPF flag ---- 0 1 ----
VSSL output level VSS1 or VSS2 about VDD-1.3 V VSS1 or VSS2 VSS1 or VSS2
RESET0 (Internal reset signal) Crystal oscillation output (XT) 32.768 kHz
0.5 sec VDD Logic power supply VSSL VSS1 or VSS2 about 1.3 V
1.5 V or 3.0 V
Figure 14-2 VSSL Output State in System Reset Mode
14-2
MSM64164C User's Manual Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR) 14.4 Backup Control Register (BUPCON) The backup control register (BUPCON) is a 4-bit special function register (SFR) to control the output voltage level of VSSL which is output of the constant voltage circuit for logic.
b3 BUPCON (37H) (R/W) VSSL level 0: VDD-1.3 V level (initial value) 1: VSS1 or VSS2 -----*
b2 -----*
b1 -----*
b0 BUPF
*Reserved bit: "1" is always read out. Not valid for write.
Bit 0:BUPF This bit is a flag to select output voltage level of VSSL which is output of the constant voltage circuit for logic (VR). By resetting BUPF to "0", the VSSL output becomes VDD-1.3 V and by setting BUPF to "1", the VSSL output becomes either VSS1 or VSS2 level. At system reset, it is reset to "0". For 0.5 second after the system reset, the VSSL output is forced to be switched to VSS1 or VSS2 level. Table 14-2 shows those pins related to the constant voltage circuit for logic.
Table 14-2 Pins Related to Constant Voltage Circuit for Logic 14
Pin name Pin No. GS-K Pad No. Input/Output GS-BK TS-K 42 44 31 40 42 29 42 44 31 ---- ---- ---- Note
VSS1 VSS2 VSSL
Negative side power supply (at 1.5 V spec.) Bias output to drive LCD (-1.5 V) (at 3.0 V spec.) Negative side power supply (at 3.0 V spec.) Bias output to drive LCD (-3.0 V) (at 1.5 V spec.) Negative side power supply pin for internal logic (internally generated voltage)
14-3
MSM64164C User's Manual Chapter 14 Constant Voltage Circuit for Logic Power Supply (VR)
14-4
Chapter 15
Test Circuit (TST)
15
MSM64164C User's Manual Chapter 15 Test Circuit (TST)
Chapter 15 Test Circuit (TST)
15.1 Overview The MSM64164C can output RC oscillation clock of the A/D converter or 400 kHz RC oscillation clock of the system clock to Port 4.3 using TST1 and TST2, which are test pins. By monitoring each RC oscillation clock, it is possible to measure the conversion characteristics of the A/D converter and the frequency of the RC oscillation side system clock. 15.2 Operation of Test Circuit When releasing system reset mode by inputting "H" to the RESET pin after selecting system reset mode by inputting "L" to the RESET pin while both TST1 and TST2 are in "L" level, the test mode is selected. To return from test mode to normal mode, both TST1 and TST2 must be left open or in a state where "H" level is input and the system reset must be input after that. When both TST1 and TST2 are open, test mode is released. However, normal operation mode is not restored until the system reset is input. Figure 15-1 shows the relation among the TST1, TST2 pins and the RESET pin.
TST1
Open state (internally pulled up)
TST2 RESET
Test mode
Normal operation mode
15 Figure 15-1 Relation among the TST1, TST2 pins and the RESET pin
Depending the state of Ports 0.0 to 0.3, various RC oscillation signals are output to Port 4.3 after moving to test mode. Tables 15-1 and 15-2 show the list of test modes and test circuit related pins. Figure 15-2 shows an example of connection in test mode. Notes: Please note that there is no guarantee of normal operation if both TST1 and TST2 are not simultaneously open or at "H" level or "L" level.
15-1
MSM64164C User's Manual Chapter 15 Test Circuit (TST) Table 15-1 List of Test Modes
TST1 0 0 0 0 0 0 0 0 0
TST2 0 0 0 0 0 0 0 0 0
P0.3 1 1 1 1 1 1 1 1 0
P0.2 0 0 0 0 1 1 1 1 --
P0.1 0 0 1 1 0 0 1 1 --
P0.0 0 1 0 1 0 1 0 1 --
P4.3 output mode CROSC0 oscillation stop (P4.3 = IN0 input) RS0-CS0 oscillation clock RT0-CS0 oscillation clock RT0-1-CS0 oscillation clock CT0-1-RS0 oscillation clock RS1-CS1 oscillation clock RT1-CS1 oscillation clock CROSC1 oscillation stop (P4.3 = IN1 input) 400 kHz RC oscillation clock output CROSC1 oscillation mode CROSC0 oscillation mode
Notes:
0: "L" level input 1: "H" level input -: Arbitrary Table 15-2 Test Circuit-Related Pins
Pin No. Pin name GS-BK TST1 TST2 RESET P0.0 P0.1 P0.2 P0.3 P4.3 71 72 70 77 78 79 80 29 GS-K Pad No. Input/Output TS-K 69 70 68 75 76 77 78 27 71 72 70 77 78 79 80 29 Input Input Input Input Input Input Input Output Test input Test input Reset input Test mode selection Test mode selection Test mode selection Test mode selection RC oscillation clock monitor output Notes
15-2
MSM64164C User's Manual Chapter 15 Test Circuit (TST)
MSM64164C XT XTAL 32.768 kHz XT P0.1 P0.0
OSC1 ROS OSC2
P0.2
P0.3
VDD 0.1 mF 3.0 V 0.47 mF VSSL
P4.3
RC oscillation clock monitor
R10 VSS2 IN0 CS0 VSS CS0 RS0 TST1 RS0 RT0 TST2 RT0
RESET
CRT0 R11 IN1 CS1 CS1 RS1 RS1 RT1 RT1
15
Figure 15-2 Connection Example of Test Mode (3.0 V operation mode)
15-3
MSM64164C User's Manual Chapter 15 Test Circuit (TST)
15-4
Appendixes
MSM64164C User's Manual Appendix A Appendix A: List of Special Function Registers
Register name Port 2 register Port 3 register Port 4 register Port 0 register Port 1 register Serial port buffer lower register Serial port buffer upper register Serial port control register Frequency control register Buzzer driver control register Buzzer frequency control register Capture register 0 Capture register 1 Capture control register Time base counter register Port 20 control register Port 21 control register Port 22 control register Port 23 control register Symbol P2 P3 P4 P0 P1 SBUFL Address 00H 01H 02H 03H 04H 06H b3 P23 P33 P43 P03 P13 SD3 b2 P22 P32 P42 P02 P12 SD2 b1 P21 P31 P41 P01 P11 SD1 b0 P20 P30 P40 P00 P10 SD0 R/W R/W yes R/W R/W R R/W R/W yes SBUFH 07H SD7 SD6 SD5 SD4 R/W 0H no yes 0H 0H
Depends on input value
Value at Byte system access reset 0H
0H 0H
SCON
08H
SDIR
EXSC
SEND
ENTR
R/W
no
0H
FCON
09H
*--
*--
*--
CPUCLK
R/W
no
0EH
BDCON
0AH
SELF
EBD
BM1
BM0
R/W yes
0H
BFCON
0BH
BF3
BF2
BF1
BF0
R/W
0H
CAPR0 CAPR1 CAPCON
0CH 0DH 0EH
32Hz 32Hz CRF1
64Hz 64Hz CRF0
128Hz 128Hz ECAP1
256Hz 256Hz ECAP0
R R R/W
yes
0H 0H
no
0H
TBCR
0FH
1Hz
2Hz
4Hz
8Hz
R/W
no
0H
P20CON
10H
P20IE
P20F
P20DIR
P20MOD
W yes
0H
P21CON
11H
P21IE
P21F
P21DIR
P21MOD
W
0H
P22CON
12H
P22IE
P22F
P22DIR
P21MOD
W yes
0H
P23CON
13H
P23IE
P23F
P23DIR
P23MOD
W
0H
Appendix-1
MSM64164C User's Manual Appendix A
Register name Port 30 control register
Symbol P30CON
Address 14H
b3 P30IE
b2 P30F
b1 P30DIR
b0 P30MOD
R/W W
Value at Byte system access reset 0H yes
Port 31 control register Port 32 control register Port 33 control register Port 40 control register Port 41 control register Port 42 control register Port 43 control register Port 01 control register Display control register A/D converter counter A register 0
P31CON
15H
P31IE
P31F
P31DIR
P31MOD
W
0H
P32CON
16H
P32IE
P32F
P32DIR
P32MOD
W yes
0H
P33CON
17H
P33IE
SIN
P33DIR
P33MOD
W
0H
P40CON
18H
P40IE
SOUT
P40DIR
P40MOD
W yes
0H
P41CON
19H
P41IE
SPR
P41DIR
P41MOD
W
0H
P42CON
1AH
P42IE
SCLK
P42DIR
P42MOD
W yes
0H
P43CON
1BH
P43IE
MON
P43DIR
P43MOD
W
0H
P01CON
1CH
*--
PUD
P1MOD
P0MOD
W
no
8H
DSPCON
1EH
*--
*--
DUTY1
DUTY0
R/W
no
0CH
CNTA0
20H
a3
a2
a1
a0
R/W yes
0H
A/D converter CNTA1 counter A register 1 A/D converter CNTA2 counter A register 2 A/D converter CNTA3 counter A register 3 A/D converter CNTA4 counter A register 4 A/D converter CNTB0 counter B register 0 A/D converter CNTB1 counter B register 1 A/D converter CNTB2 counter B register 2
21H
a7
a6
a5
a4
R/W
0H
22H
a11
a10
a9
a8
R/W yes
0H
23H
a15
a14
a13
a12
R/W
0H
24H
*--
a18
a17
a16
R/W
no
8H
26H
b3
b2
b1
b0
R/W yes
0H
27H
b7
b6
b5
b4
R/W
0H
28H
b11
b10
b9
b8
R/W
yes
0H
Appendix-2
MSM64164C User's Manual Appendix A
Register name
Symbol
Address 29H
b3 *--
b2 *--
b1 b13
b0 b12
R/W R/W
Value at Byte system access reset yes 0CH
A/D converter CNTB3 counter B register 3 A/D converter control register 0 A/D converter control register 1 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 2 Interrupt request register 0 Interrupt request register 1 Watchdog timer control register Backup control register Display register 0 Display register 1 Display register 2 Display register 3 Display register 4 Display register 5 Display register 6 Display register 7 Display register 8 Display register 9 ADCON0
2AH
*--
*--
SADI
EADC
R/W yes
0CH
ADCON1
2BH
OM3
OM2
OM1
OM0
R/W
0H
IE0
30H
EAD
EXI1
ESIO
EXI0
R/W yes
0H
IE1
31H
E1Hz
E16Hz
E32Hz
E256Hz
R/W
0H
IE2
32H
*--
*--
*--
E01Hz
R/W yes
0EH
IRQ2
33H
*--
*--
QWDT
Q01Hz
R/W
0CH
IRQ0
34H
QAD
QXI1
QSIO
QXI0
R/W yes
0H
IRQ1
35H
Q1Hz
Q16Hz
Q32Hz
Q256Hz
R/W
0H
WDTCON
36H
d3
d2
d1
d0
W
no
0H
BUPCON
37H
*--
*--
*--
BUPF
R/W
no
0EH
DSPR0 DSPR1 DSPR2 DSPR3 DSPR4 DSPR5 DSPR6 DSPR7 DSPR8 DSPR9
40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH
d d d d d d d d d d d
c c c c c c c c c c c
b b b b b b b b b b b
a a a a a a a a a a a
R/W yes R/W R/W yes R/W R/W yes R/W R/W yes R/W R/W yes R/W R/W yes
0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H
Display register 10 DSPR10
Appendix-3
MSM64164C User's Manual Appendix A
Register name
Symbol
Address 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 7CH
b3 d d d d d d d d d d d d d d d d d d d d *--
b2 c c c c c c c c c c c c c c c c c c c c *--
b1 b b b b b b b b b b b b b b b b b b b b *--
b0 a a a a a a a a a a a a a a a a a a a a MI
R/W R/W R/W R/W R/W R/W R/W
Value at Byte system access reset yes yes 0H 0H 0H yes 0H 0H 0H yes 0H yes 0H 0H yes 0H 0H yes 0H 0H yes 0H 0H yes 0H 0H yes 0H 0H no no 0H 0EH
Display register 11 DSPR11 Display register 12 DSPR12 Display register 13 DSPR13 Display register 14 DSPR14 Display register 15 DSPR15 Display register 16 DSPR16 Display register 17 DSPR17 Display register 18 DSPR18 Display register 19 DSPR19 Display register 20 DSPR20 Display register 21 DSPR21 Display register 22 DSPR22 Display register 23 DSPR23 Display register 24 DSPR24 Display register 25 DSPR25 Display register 26 DSPR26 Display register 27 DSPR27 Display register 28 DSPR28 Display register 29 DSPR29 Display register 30 DSPR30 Master interrupt enable register Halt mode register Stack pointer MIEF
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
HALT SP
7DH 7EH 7FH
*-- SP3 *--
*-- SP2 SP6
*-- SP1 SP5
HLT *--
R/W R/W
no yes
0EH 0FFH
SP4
Notes: (1) Only byte access is possible for the Stack pointer. (2) "*--" in the table is a reserved bit. "1" is always read out. Not valid for write. (3) The display registers 0 through 30 are registers that cannot be used without selection by the mask option. All the display registers to be used must be allocated on the LCD driver mask option table per bit. (Refer to Appendix F on the mask options.)
Appendix-4
MSM64164C User's Manual Appendix B Appendix B: Description of Special Function Registers
Register name Port 2 register Port 20 control register Port 21 control register Port 22 control register Port 23 control register Symbol P2 P20CON P21CON P22CON P23CON Address 00H 10H 11H 12H 13H Read/Write R/W W W W W Value at system reset 0H 0H 0H 0H 0H
b3 P2 (00H) (R/W) P23
b2 P22
b1 P21
b0 P20
b3 P20CON (10H) (W) P20IE
b2 P20F
b1 P20DIR
b0 P20MOD
P2.0 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P2.0 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P2.0 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P2.0 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P2.0 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-5
MSM64164C User's Manual Appendix B
b3 P21 (11H) (W) P21IE
b2 P21F
b1 P21DIR
b0 P21MOD
P2.1 Selection of external interrupt disable (initial value) 0: Interrupt disable (initial value) 1: Interrupt enable P2.1 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P2.1 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P2.1 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P2.1 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-6
MSM64164C User's Manual Appendix B
b3 P22CON (12H) (W) P22IE
b2 P22F
b1 P22DIR
b0 P22MOD
P2.2 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P2.2 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P2.2 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P2.2 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P2.2 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-7
MSM64164C User's Manual Appendix B
b3 P23CON (13H) (W) P23IE
b2 P23F
b1 P23DIR
b0 P23MOD
P2.3 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P2.3 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P2.3 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P2.3 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P2.3 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Description The Port 2 register (P2) is a data register to output to Port 2. When P2 is read out while Bit 1 (each DIR bit) of P20CON to P23CON is reset to "0" in input mode, the pin level of each bit is read out for those bits where input mode is selected. The Port 20 to 23 control registers (P20CON, P21CON, P22CON and P23CON) perform selection of input/output mode, selection of pull-down/pull-up resistance input/ high-impedance input in input mode, selection of CMOS/NMOS open drain output in output mode, selection of sampling clocks when used as external interrupt input and selection of external interrupt enable/disable for Port 2. Selection of pull-down/pull-up resistance input is performed by Bit 2 (PUD) of the Port 01 control register (P01CON).
Appendix-8
MSM64164C User's Manual Appendix B
Register name Port 3 register Port 30 control register Port 31 control register Port 32 control register Port 33 control register
Symbol P3 P30CON P31CON P32CON P33CON
Address 01H 14H 15H 16H 17H
Read/Write R/W W W W W
Value at system reset 0H 0H 0H 0H 0H
b3 P3 (01H) (R/W) P33
b2 P32
b1 P31
b0 P30
b3 P30CON (14H) (W) P30IE
b2 P30F
b1 P30DIR
b0 P30MOD
P3.0 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P3.0 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P3.0 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P3.0 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down pull-up resistance input (initial value) 1: High impedance input P3.0 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-9
MSM64164C User's Manual Appendix B
b3 P31CON (15H) (W) P31IE
b2 P31F
b1 P31DIR
b0 P31MOD
P3.1 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P3.1 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P3.1 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P3.1 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P3.1 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-10
MSM64164C User's Manual Appendix B
b3 P32CON (16H) (W) P32IE
b2 P32F
b1 P32DIR
b0 P32MOD
P3.2 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P3.2 Selection of external interrupt sampling clock 0: 64 Hz (initial value) 1: System clock P3.2 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P3.2 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P3.2 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-11
MSM64164C User's Manual Appendix B
b3 P33CON (17H) (W) P33IE
b2 SIN
b1 P33DIR
b0 P33MOD
P3.3 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P3.3 Switching of SIN pin function 0: Input/output port function (initial value) 1: Serial port data input function P3.3 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P3.3 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P3.3 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Description The Port 3 register (P3) is a data register to output to Port 3. When P3 is read out while Bit 1 (each DIR bit) of P30CON to P33CON is reset to "0" in input mode, the pin level of each bit is read out for those bits where input mode is selected. The Port 30 to 33 control registers (P30CON, P31CON, P32CON and P33CON) perform selection of input/output mode, selection of pull-down/pull-up resistance input/ high-impedance input in input mode, selection of CMOS/NMOS open drain output in output mode, selection of sampling clocks when used as external interrupt input and selection of external interrupt enable/disable for Port 3. There is no selection function of sampling clocks for P3.3. Selection of pull-down/pull-up resistance input is performed by Bit 2 (PUD) of the Port 01 control register (P01CON).
Appendix-12
MSM64164C User's Manual Appendix B
Register name Port 4 register Port 40 control register Port 41 control register Port 42 control register Port 43 control register
Symbol P4 P40CON P41CON P42CON P43CON
Address 02H 18H 19H 1AH 1BH
Read/Write R/W W W W W
Value at system reset 0H 0H 0H 0H 0H
b3 P4 (02H) (R/W) P43
b2 P42
b1 P41
b0 P40
b3 P40CON (18H) (W) P40IE
b2 SOUT
b1 P40DIR
b0 P40MOD
P4.0 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P4.0 Switching of SOUT pin function 0: Input/output port function (initial value) 1: Serial port data output function P4.0 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P4.0 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P4.0 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-13
MSM64164C User's Manual Appendix B
b3 P41CON (19H) (W) P41IE
b2 SPR
b1 P41DIR
b0 P41MOD
P4.1 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P4.1 Switching of /SPR pin function 0: Input/output port function (initial value) 1: Serial port ready signal output function P4.1 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P4.1 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P4.1 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-14
MSM64164C User's Manual Appendix B
b3 P42CON (1AH) (W) P42IE
b2 SCLK
b1 P42DIR
b0 P42MOD
P4.2 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P4.2 Switching of SCLK pin function 0: Input/output port function (initial value) 1: Serial port clock input/output function P4.2 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P4.2 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P4.2 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Appendix-15
MSM64164C User's Manual Appendix B
b3 P43CON (1BH) (W) P43IE
b2 MON
b1 P43DIR
b0 P43MOD
P4.3 Selection of external interrupt disable/enable 0: Interrupt disable (initial value) 1: Interrupt enable P4.3 Switching of MON pin function 0: Input/output port function (initial value) 1: RC oscillation clock output function P4.3 Selection of input/output mode 0: Input mode (initial value) 1: Output mode P4.3 Selection of pull-down/pull-up resistance input or high impedance input (in input mode) 0: Pull-down/pull-up resistance input (initial value) 1: High impedance input P4.3 Selection of CMOS output/NMOS open drain output (in output mode) 0: CMOS output (initial value) 1: NMOS open drain output
Description The Port 4 register (P4) is a data register to output to Port 4. When P4 is read out while Bit 1 (each DIR bit) of P40CON to P43CON is reset to "0" in input mode, the pin level of each bit is read out for those bits where input mode is selected. The Port 40 to 43 control registers (P40CON, P41CON, P42CON and P43CON) perform selection of input/output mode, selection of pull-down/pull-up resistance input/ high-impedance input in input mode, selection of CMOS/NMOS open drain output in output mode and selection of external interrupt enable/disable for Port 4. P4.1 can select input/output port functions/serial port data ready output functions. P4.2 can select input/ output port functions or serial port clock input/output functions. P4.3 can select input/ output port functions or clock monitor functions of the RC oscillation circuit. Selection of pull-down/pull-up resistance input is performed by Bit 2 (PUD) of the Port 01 control register (P01CON).
Appendix-16
MSM64164C User's Manual Appendix B
Register name Port 0 register Port 1 register Port 01 control register
Symbol P0 P1 P01CON
Address 03H 04H 1CH
Read/Write R R/W W
Value at system reset
Depends on input value
0H 8H
b3 P0 (03H) (R) P03
b2 P02
b1 P01
b0 P00
Pin level of each bit of Port 0 0: "L" level 1: "H" level
Description The Port 0 register (P0) is a read-only port and each pin level of Port 0 is read out.
b3 P1 (04H) (R/W) P13
b2 P12
b1 P11
b0 P10
Description The Port 1 register (P1) is a data register to output data to Port 1.
Appendix-17
MSM64164C User's Manual Appendix B
b3 P01CON (1CH) (W) -----*
b2 PUD
b1 P1MOD
b0 P0MOD
Selection of P0, P2, P3 and P4 input mode 0: Pull-up resistance input (initial value) 1: Pull-down resistance input Selection of P1 output mode 0: CMOS output (initial value) 1: NMOS open drain output Selection of P0 input mode 0: Pull-down/pull-up resistance input (initial value) 1: High-impedance input *Reserved bit: Not valid for write.
Description Bit 2 (PUD) of the Port 01 control register (P01CON) selects pull-down resistance input or pull-up resistance input when pull-down/pull-up resistance input is selected at P0, P2, P3 and P4. Bit 1 (P1MOD) of P01CON selects CMOS output or NMOS open drain output of Port 1. Bit 0 (P0MOD) of P01CON selects pull-down/pull-up resistance input or high impedance input of Port 0.
Appendix-18
MSM64164C User's Manual Appendix B
Register name Serial port buffer lower register Serial port buffer upper register Serial port control register
Symbol SBUFL SBUFH SCON
Address 06H 07H 08H
Read/Write R/W R/W R/W
Value at system reset 0H 0H 0H
b3 SBUFL (06H) (R/W) SD3
b2 SD2
b1 SD1
b0 SD0 (LSB)
Value of lower 4 bits of the serial port buffer
b3 SBUFH (07H) (R/W) SD7 (MSB) Value of upper 4 bits of the serial port buffer
b2 SD6
b1 SD5
b0 SD4
b3 SCON (08H) (R/W) Selection of transfer data 0: MSB (SD7) head (initial value) 1: LSB (SD0) head Selection of serial clock 0: Internal clock (initial value) 1: External clock Serial transfer completion flag 0: Transfer not completed (initial value) 1: Transfer completed Serial transfer enable flag 0: Transfer halted (initial value) 1: Transfer started SDIR
b2 EXSC
b1 SEND
b0 ENTR
Appendix-19
MSM64164C User's Manual Appendix B
Description The Serial port buffer lower register (SBUFL) and the Serial port buffer upper register (SBUFH) are used to write send data and to read receive data. The Serial port control register (SCON) selects the direction of serial transfer data, selection of the internal or the external system clock and confirms the start and the end of serial transfer. Bit 1 (SEND) of SCON is a read only bit.
Register name Frequency control register Symbol FCON Address 09H Read/Write R/W Value at system reset 0EH
b3 FCON (09H) (R/W) -----*
b2 -----*
b1 -----*
b0 CPUCLK
Selection of system clock 0: Crystal oscillation output (initial value) 1: 400 kHz RC oscillation output *Reserved bit: "1" is always read out. Not valid for write.
Description The Frequency control register (FCON) selects system clocks. When reset to "0", the crystal oscillation output (32.768 kHz) is selected and when set to "1", the RC oscillation output is selected.
Appendix-20
MSM64164C User's Manual Appendix B
Register name Buzzer driver control register Buzzer frequency control register
Symbol BDCON BFCON
Address 0AH 0BH
Read/Write R/W R/W
Value at system reset 0H 0H
b3 BDCON (0AH) (R/W) SELF
b2 EBD
b1 BM1
b0 BM0
Selection of buzzer output logic 0: Positive logic output (initial value) 1: Negative logic output Selection of buzzer enable/disable 0: Buzzer stop (initial value) 1: Buzzer output Selection of buzzer mode b1 b0 0 0: Discontinuous sound 1 output (initial value) 0 1: Discontinuous sound 2 output 1 0: Single sound output 1 1: Continuous sound output
Appendix-21
MSM64164C User's Manual Appendix B
b3 BFCON (0BH) (R/W) BF3
b2 BF2
b1 BF1
b0 BF0
Selection of buzzer output frequency b3 b2 b1 b0 0 0 0 0: Output stops (initial value) 0 0 0 1: 5.461 kHz 0 0 1 0: 4.096 kHz 0 0 1 1: 3.277 kHz 0 1 0 0: 2.730 kHz 0 1 0 1: 2.341 kHz 0 1 1 0: 2.048 kHz 0 1 1 1: 1.820 kHz 1 0 0 0: 1.638 kHz 1 0 0 1: 1.489 kHz 1 0 1 0: 1.365 kHz 1 0 1 1: 1.260 kHz 1 1 0 0: 1.170 kHz 1 1 0 1: 1.092 kHz 1 1 1 0: 1.024 kHz 1 1 1 1: 0.964 kHz
Description The Buzzer driver control register (BDCON) is a register to select buzzer output logic, buzzer output enable/disable and buzzer sound mode. The Buzzer frequency control register (BFCON) is a register to select output frequencies of buzzer.
Appendix-22
MSM64164C User's Manual Appendix B
Register name Capture control register Capture register 0 Capture register 1
Symbol CAPCON CAPR0 CAPR1
Address 0EH 0CH 0DH
Read/Write R/W R R
Value at system reset 0H 0H 0H
b3 CAPCON (0EH) (R/W) CRF1
b2 CRF0
b1 ECAP1
b0 ECAP0
Selection of capture 1 data latch 0: Does not do capture 1 data latch (initial value) 1: Does capture 1 data latch Selection of capture 0 data latch 0: Does not do capture 0 data latch (initial value) 1: Does capture 0 data latch Selection of capture 1 enable/disable 0: Capture 1 disable (initial value) 1: Capture 1 enable Selection of capture 0 enable/disable 0: Capture 0 disable (initial value) 1: Capture 0 enable
b3 CAPR0 (0CH) (R) 32Hz
b2 64Hz
b1 128Hz
b0 256Hz
Values of 32 Hz to 256 Hz of the time base counter
Appendix-23
MSM64164C User's Manual Appendix B
b3 CAPR1 (0DH) (R) 32Hz
b2 64Hz
b1 128Hz
b0 256Hz
Values of 32 Hz to 256 Hz of the time base counter
Description The capture control register (CAPCON) is used to select latch and enable/disable of time base counter output data (32 to 256 Hz) of Capture 0 and Capture 1. The capture register 0 (CAPR0) and the capture register 1 (CAPR1) are used to read time base counter output latch data of Capture 0 and Capture 1.
Register name Time base counter register
Symbol TBCR
Address 0FH
Read/Write R/W
Value at system reset 0H
b3 TBCR (0FH) (R/W) 1Hz
b2 2Hz
b1 4Hz
b0 8Hz
Values of 1 Hz to 8 Hz of the time base counter
Description The time base counter register (TBCR) outputs the contents of the time base counter when reading. When writing, 8 Hz, 4 Hz, 2 Hz, 1 Hz and 0.1 Hz output of the time base counter are reset to "0".
Appendix-24
MSM64164C User's Manual Appendix B
Register name Display control register
Symbol DSPCON
Address 1EH 40H to 5EH
Read/Write R/W R/W
Value at system reset 0CH 0H
Display registers 0 to 30 DSPR0 to DSPR30
b3 DSPCON (1EH) (R/W) -----*
b2 -----*
b1 DUTY1
b0 DUTY0
Duty selection b1 b0 0 0: 1/4 duty (initial value) 0 1: 1/3 duty 1 0: 1/2 duty 1 1: Disabled *Reserved bit: "1" is always read. Not valid for write.
Appendix-25
MSM64164C User's Manual Appendix B
b3 DSPR30 (5EH) (R/W) d
b2 c
b1 b
b0 a Segment output data
b3 DSPR29
b2 c
b1 b
b0 a Segment output data
. . . . . . . . . .
DSPR0
(5DH) (R/W)
d
b3 (40H) (R/W) d
b2 c
b1 b
b0 a Segment output data
Description The Display control register (DSPCON) is a register to select duty of the LCD driver. The Display registers (DSPR0 to 30) are data registers for segment output of the LCD driver and can output to each LCD driver by specifying the mask option of the LCD part.
Appendix-26
MSM64164C User's Manual Appendix B
Register name A/D converter control register 0 A/D converter control register 1 A/D converter counter A register 0 A/D converter counter A register 1 A/D converter counter A register 2 A/D converter counter A register 3 A/D converter counter A register 4 A/D converter counter B register 0 A/D converter counter B register 1 A/D converter counter B register 2 A/D converter counter B register 3
Symbol ADCON0 ADCON1 CNTA0 CNTA1 CNTA2 CNTA3 CNTA4 CNTB0 CNTB1 CNTB2 CNTB3
Address 2AH 2BH 20H 21H 22H 23H 24H 26H 27H 28H 29H
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Value at system reset 0CH 0H 0H 0H 0H 0H 8H 0H 0H 0H 0CH
b3 ADCON0 (2AH) (R/W) -----*
b2 -----*
b1 SADI
b0 EADC
Selection of A/D interrupt request 0: Counter A overflow (initial value) 1: Counter B overflow Selection of A/D conversion start/stop 0: RC oscillation stop (initial value) 1: RC oscillation start *Reserved bit: "1" is always read out. Not valid for write.
Appendix-27
MSM64164C User's Manual Appendix B
b3 ADCON1 (2BH) (R/W) OM3
b2 OM2
b1 OM1
b0 OM0
Selection of oscillation mode b3 b2 b1 b0 0 0 0 0: IN0 pin external clock input mode (initial value) 0 0 0 1: RS0-CS0 oscillation mode 0 0 1 0: RT0-CS0 oscillation mode 0 0 1 1: RT0-1-CS0 oscillation mode 0 1 0 0: RS0-CT0 oscillation mode 0 1 0 1: RS1-CS1 oscillation mode 0 1 1 0: RT1-CS1 oscillation mode 0 1 1 1: IN1 pin external clock input mode
b3 CNTA0 (20H) (R/W) a3
b2 a2
b1 a1
b0 a0
Value of Bits 0 to 3 of Counter A
b3 CNTA1 (21H) (R/W) a7
b2 a6
b1 a5
b0 a4
Value of Bits 4 to 7 of Counter A
Appendix-28
MSM64164C User's Manual Appendix B
b3 CNTA2 (22H) (R/W) a11
b2 a10
b1 a9
b0 a8
Value of Bits 8 to 11 of Counter A
b3 CNTA3 (23H) (R/W) a15
b2 a14
b1 a13
b0 a12
Value of Bits 12 to 15 of Counter A
b3 CNTA4 (24H) (R/W) -----*
b2 a18
b1 a17
b0 a16
Value of Bits 16 to 18 of Counter A *Reserved bit: "1" is always read out. Not valid for write.
b3 CNTB0 (26H) (R/W) b3
b2 b2
b1 b1
b0 b0
Value of Bits 0 to 3 of Counter B
Appendix-29
MSM64164C User's Manual Appendix B
b3 CNTB1 (27H) (R/W) b7
b2 b6
b1 b5
b0 b4
Value of Bits 4 to 7 of Counter B
b3 CNTB2 (28H) (R/W) b11
b2 b10
b1 b9
b0 b8
Value of Bits 8 to 11 of Counter B
b3 CNTB3 (29H) (R/W) -----*
b2 -----*
b1 b13
b0 b12
Value of Bits 12, 13 of Counter B *Reserved bit: "1" is always read out. Not valid for write.
Description The A/D converter control register 0 (ADCON0) selects interrupt by overflow of either Counter A or Counter B and selects operation or stop of A/D conversion. The A/D converter control register 1 (ADCON1) is a register to select various RC oscillation modes. The A/D converter counter A registers 0 to 4 (CNTA0 to 4) are registers to read/ write the contents of Counter A. The A/D converter counter B registers 0 to 3 (CNTB0 to 3) are registers to read/write the contents of Counter B.
Appendix-30
MSM64164C User's Manual Appendix B
Register name Watchdog timer control register
Symbol WDTCON
Address 36H
Read/Write W
Value at system reset 0H
b3 WDTCON (36H) (W) d3
b2 d2
b1 d1
b0 d0
Description The Watchdog timer control register (WDTCON) is a register to reset the watchdog timer. WDTCON is a write-only register.
Register name Backup control register
Symbol BUPCON
Address 37H
Read/Write R/W
Value at system reset 0EH
b3 BUPCON (37H) (R/W) -----*
b2 -----*
b1 -----*
b0 BUPF
VSSL level 0: VDD-1.3 V level (initial value) 1: VSS1 or VSS2 level *Reserved bit: "1" is always read out. Not valid for write.
Description The Backup control register is a register to select the voltage level of VSSL.
Appendix-31
MSM64164C User's Manual Appendix B
Register name Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2
Symbol IE0 IE1 IE2
Address 30H 31H 32H
Read/Write R/W R/W R/W
Value at system reset 0H 0H 0EH
b3 IE0 (30H) (R/W) EAD
b2 EXI1
b1 ESIO
b0 EXI0
A/D converter external interrupt enable flag 0: Disabled (initial value) 1: Enabled External 1 interrupt enable flag 0: Disabled (initial value) 1: Enabled Serial port interrupt enable flag 0: Disabled (initial value) 1: Enabled External 0 interrupt enable flag 0: Disabled (initial value) 1: Enabled
Appendix-32
MSM64164C User's Manual Appendix B
b3 IE1 (31H) (R/W) E1Hz
b2 E16Hz
b1 E32Hz
b0 E256Hz
1 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 16 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 32 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled 256 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled
b3 IE2 (32H) (R/W) -----*
b2 -----*
b1 -----*
b0 E01Hz
0.1 Hz interrupt enable flag 0: Disabled (initial value) 1: Enabled *Reserved bit: "1" is always read out. Not valid for write.
Description These are registers to set disable/enable of each interrupt.
Appendix-33
MSM64164C User's Manual Appendix B
Register name Interrupt request register 0 Interrupt request register 1 Interrupt request register 2
Symbol IRQ0 IRQ1 IRQ2
Address 34H 35H 33H
Read/Write R/W R/W R/Q
Value at system reset 0H 0H 0CH
b3 IRQ0 (34H) (R/W) A/D converter interrupt request flag 0: No request (initial value) 1: Requested External 1 interrupt request flag 0: No request (initial value) 1: Request Serial port interrupt request flag 0: No request (initial value) 1: Requested External 0 interrupt request flag 0: No request (initial value) 1: Requested QAD
b2 QXI1
b1 QSIO
b0 QXI0
Appendix-34
MSM64164C User's Manual Appendix B
b3 IRQ1 (35H) (R/W) 1 Hz interrupt request flag 0: No request (initial value) 1: Requested 16 Hz interrupt request flag 0: No request (initial value) 1: Requested 32 Hz interrupt request flag 0: No request (initial value) 1: Requested 256 Hz interrupt request flag 0: No request (initial value) 1: Requested Q1Hz
b2 Q16Hz
b1 Q32Hz
b0 Q256Hz
b3 IRQ2 (33H) (R/W) Watchdog timer interrupt request flag 0: No request (initial value) 1: Requested 0.1 Hz interrupt request flag 0: No request (initial value) 1: Requested -----*
b2 -----*
b1 QWDT
b0 Q01Hz
*Reserved bit: "1" is always read out. Not valid for write.
Description These bits are set by each interrupt request. When interrupt is enabled by (IE0, IE1 and IE2), the CPU receives interrupts only when the master interrupt enable flag (MI) is set to "1" and the execution is advanced to the vector address of each interrupt. The watchdog timer interrupt does not have interrupt mask functions by the IE register and the MI flag.
Appendix-35
MSM64164C User's Manual Appendix B
Register name Master interrupt enable register
Symbol MIEF
Address 7CH
Read/Write R/W
Value at system reset 0EH
b3 MIEF (7CH) (R/W) Master interrupt enable flag 0: Interrupt disabled (initial value) 1: Interrupt enabled -----*
b2 -----*
b1 -----*
b0 MI
*Reserved bit: "1" is always read out. Not valid for write.
Description When MI is set to "1", interrupt is enabled and interrupts by the interrupt enable registers (IE0, IE1 and IE2) and the interrupt request registers (IRQ0, IRQ1 and IRQ2) are received by the CPU.
Register name Halt mode register
Symbol HALT
Address 7DH
Read/Write R/W
Value at system reset 0EH
b3 HALT (7DH) (R/W) Halt mode transition selection flag 0: Normal operation (initial value) 1: Halt mode -----*
b2 -----*
b1 -----*
b0 HLT
*Reserved bit: "1" is always read out. Not valid for write.
Description A flag to enter halt mode. When the HLT flag is set to "1", the CPU enters halt mode at the first machine cycle of the next instruction.
Appendix-36
MSM64164C User's Manual Appendix B
Register name Stack pointer
Symbol SP
Address 7EH
Read/Write R/W
Value at system reset 0FFH
b7 SP (7EH) (R/W)
b6
b5
b4
b3
b2
b1
b0
-----* SP6
SP5 SP4 SP3 SP2 SP1 -----*
Contents of the stack pointer *Reserved bit: "1" is always read out. Not valid for write.
Description This is a pointer to indicate a stack address. At reset, it becomes "0FFH" and addresses 0FFH and 0FEH on the data memory of Bank 7 are selected. An access to the stack pointer is valid only for byte access instructions as 8-bit transfer instructions and 8-bit arithmetic instructions.
Appendix-37
MSM64164C User's Manual Appendix C Appendix C: Package Dimension Diagrams and Pad Coordinates MSM64164C-xxxGS-BK (Unit: mm)
Mirror finish
Figure C-1 80-Pin QFP: GS-BK Package Dimension Diagram MSM64164C-xxxGS-K
Mirror finish
Figure C-2 80-Pin QFP: GS-K Package Dimension Diagram
Appendix-38
MSM64164C User's Manual Appendix C MSM64164C-xxxTS-K
(Unit: mm)
Mirror finish
Figure C-3 80-Pin TQFP: TS-K Package Dimension Diagram
Appendix-39
MSM64164C User's Manual Appendix C Table C-1 Pad Coordinates MSM64164C-xxx
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 BD VSSL VDD RT0 CRT0 RS0 CS0 IN0 IN1 CS1 RS1 X (m) -2545 -2314 -2083 -1852 -1621 -1390 -1159 -928 -697 -466 -235 0 235 466 697 928 1159 1390 1621 1852 2083 2314 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 2545 Y (m) -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -2090 -1880 -1670 -1460 -1250 -1040 -830 -620 -431 -74 200 410 620 830 1040 1250 1460 1670 Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RT1 VSS1 VSS VSS2 VSS3 C1 C2 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 OSC2 OSC1 VDD XT XT RESET TST1 TST2 P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3
Center of chip : x = 0, y = 0 Pad Name X (m) 2545 2545 2314 2083 1852 1621 1390 1159 928 697 466 235 0 -235 -466 -697 -928 -1159 -1390 -1621 -1852 -2083 -2314 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 -2545 Y (m) 1880 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 2090 1775 1551 1327 1103 879 655 431 207 -207 -431 -655 -879 -1103 -1327 -1551 -1747
Bonding pad size : 100 m x 100 m
Appendix-40
MSM64164C User's Manual Appendix D Appendix D: Layout of Input/Output Circuits A. Input/output ports (P2.0 to P2.3, P3.0 to P3.3, P4.0 to P4.3)
VSS
VDD Pull-up/pull-down control VDD
I/O
Gate control circuit
Output data
VSS Schmitt trigger input
Output control Input data VSS
B. Input ports (P0.0 to P0.3)
VSS
VDD Pull-up/pull-down control
Schmitt trigger input I Input data VSS
C. Output ports (P1.0 to P1.3)
O
Gate control circuit
VDD
Output data
VSS
Output control
Appendix-41
MSM64164C User's Manual Appendix D D. Output port (L26/P5.0 to L29/P5.3, L30/P6.0 to L33/P6.3 pins at the mask option)
O
VSS
E. BD and CS1 outputs
O
NOTE: VSS1/VSS2: 1.5 V spec.-VSS1
VSS1/VSS2
3.0 V spec.-VSS2
F. RS0, RS1, RT0, RT1, CS0 and CRT0 outputs
Output enable O
VSS1/VSS2
G. IN0 and IN1 inputs
I Input VSS1/VSS2 A/D converter enable VSS1/VSS2
Appendix-42
MSM64164C User's Manual Appendix D H. Crystal oscillation circuit
VDD Mask option XT VDD VSSL XT 32.768 kHz clock
I.
400 kHz RC oscillation circuit
OSC2 VDD Oscillation start
OSC1
RC Oscillation clock
VSS1/VSS2
J. RESET, TST1, and TST2 inputs
VDD 2 k (Typ.) Schmitt trigger input I
VSS1/VSS2
Appendix-43
Examples of Application Circuit
Appendix E:
MSM64164C User's Manual Appendix E
LCD
ROS
32768 Hz
CGEX
OSC2 OSC1 VDD XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3
L33
L0 VDD MSM64164C-XXX (3 V spec.) C2 C1 VSS3 VSS2 VSS VSS1 VSSL TST2 TST1 C12 Cb C2
3V 5V
Figure E-1 Example of 3 V Spec. Applied Circuit
CS
Appendix-44
Ca CL
* 5 V interface * Temperature
IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1 BD P4.3 P4.2 P4.1 P4.0 P3.3
Switch matrix (4 4)
RT0
measurement by two thermistors
* CG of crystal oscillation
RT1 RS1 CS1 R11
RS0
CS0
R10
: External (CGEX)
* CL = 0.1 mF +100% - 50%
Buzzer
When CPUCLK = "1" or BUPF = "1", CL = 0.47 mF 30%
OSC monitor SCLK SPR To serial communication interface SOUT (to 5 V (VSS) system). SIN
LCD
ROS L33 VDD MSM64164C-XXX (1.5 V spec.) VSS3 VSS2 Cb Ca C12 C2 C1 C1 L0
32768 Hz
OSC2 OSC1 VDD XT XT RESET
1.5 V
Figure E-2 Example of 1.5 V Spec. Applied Circuit
CL TST1
IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1 BD P4.3 P4.2 P4.1 P4.0 P3.3
Appendix-45
VSS VSS1 VSSL TST2 P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3
RT0 RT1 RS1 CS1 R11 RS0 CS0 R10
* Temperature
measurement by two thermistors
* CG of crystal oscillation
Switch matrix (4 4)
: Built-in
* CL = 0.1 mF +100% - 50%
MSM64164C User's Manual Appendix E
Buzzer
MSM64164C User's Manual Appendix F Appendix F: Mask Options q Table of power supply voltage and CG selection mask options
Item Power supply voltage 3.0 V Built-in CG of crystal oscillator External Mask specification 1.5 V Selection
q Table of LCD driver mask options [Description of LCD driver mask options] SEG LCD driver pin name
SIGNAL Write the name of each segment corresponding each common signal. C/S/P Indicates whether L0 to L33 of the LCD driver are selected as segment diver or common driver or output port. When selected as segment driver, "S" is written. When selected as common driver, "C" is written and when used as output port,"P" is written. When not used, blank is written. Writes the bit name of the display register corresponding to the signal name (a to d). Writes the number of the display register (0 to 30). When not used, blank is written.
DATA DSPR Notes:
(1) There is no need to use all 0 to 30 of the display registers. (2) The same name (i.e. the same display register number and the same bit name) can be used for 2 or more than 2 segments. (3) When "P" is selected, DSPR becomes either 0 or 1. DATA and DSPR are assigned to COM1 when "P" is selected. Selection of "P" is possible only for the LCD drivers of L26 to L33. (4) To make a table of the mask options, use the MASK164 mask option generator. For details of input, refer to "MASK164 Mask Option Generator User's Manual". (5) When the display registers are used as the data register and flag, not for indication, the display registers must be assigned per bit by using the empty segments in the LCD driver mask option table. When the empty segments do not exist on the LCD driver mask option table, the display register can not be used as the data register and flag.
Appendix-46
MSM64164C User's Manual Appendix F [Example of how to make a LCD driver mask options] (1) When L0 is assigned to Common 2, L1 to segment and L2 as unused (1/4 duty)
COM1 SEG SIGNAL C/S/P
COM2
COM3
COM4
DATA DSPR DATA DSPR DATA DSPR DATA DSPR L0 L1 L2 / COM2 / ALARM / MODE / / / 4f / / 4g / C S b 5 d 6 b 14 c 14
(2) When L27 is assigned to Common 1, L28 to segment and L29 as an output port (1/4 duty)
COM1 SEG SIGNAL C/S/P
COM2
COM3
COM4
DATA DSPR DATA DSPR DATA DSPR DATA DSPR L27 L28 L29 COM1 1a OUT / / / 1b / / / / 1c / DP1 / C S P a a 2 0 b 2 c 2 d 2
Appendix-47
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/4 duty) (1/2)
COM1 SEG SIGNAL C/S/P DATA DSPR DATA DSPR DATA DSPR DATA DSPR L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / COM2 COM3 COM4
Appendix-48
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/4 duty) (2/2)
COM1 SEG SIGNAL C/S/P DATA DSPR DATA DSPR DATA DSPR DATA DSPR L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / COM2 COM3 COM4
Appendix-49
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/3 duty) (1/2)
COM1 SEG SIGNAL C/S/P COM2 COM3 DATA DSPR DATA DSPR DATA DSPR
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21
/ / / / / / / / / / / / / / / / / / / / / /
/ / / / / / / / / / / / / / / / / / / / / /
Appendix-50
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/3 duty) (2/2)
COM1 SEG SIGNAL C/S/P COM2 COM3 DATA DSPR DATA DSPR DATA DSPR
L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33
/ / / / / / / / / / / /
/ / / / / / / / / / / /
Appendix-51
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/2 duty) (1/2)
COM1 SEG SIGNAL C/S/P DATA L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 / / / / / / / / / / / / / / / / / / / / / / DSPR DATA DSPR COM2
Appendix-52
MSM64164C User's Manual Appendix F Table of LCD Driver Mask Options (1/2 duty) (2/2)
COM1 SEG SIGNAL C/S/P DATA L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 / / / / / / / / / / / / DSPR DATA DSPR COM2
Appendix-53
MSM64164C User's Manual Appendix G Appendix G: Electrical Characteristics (1) 1.5 V Spec. q Absolute Maximum Ratings (VDD = 0 V)
Parameter Power supply voltage 1 Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 Input voltage 1 Input voltage 2 Input voltage 3 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Storage temperature Symbol VSS1 VSS2 VSS3 VSSL VSS VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 TSTG Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C VSS1 input, Ta = 25C VSS input, Ta = 25C VSSL input, Ta = 25C VSS1 output, Ta = 25C VSS2 output, Ta = 25C VSS3 output, Ta = 25C VSS output, Ta = 25C VSSL output, Ta = 25C -- Rating -2.0 to +0.3 -4.0 to +0.3 -5.5 to +0.3 -2.0 to +0.3 -5.5 to +0.3 VSS1 - 0.3 to +0.3 VSS - 0.3 to +0.3 VSSL - 0.3 to +0.3 VSS1 - 0.3 to +0.3 VSS2 - 0.3 to +0.3 VSS3 - 0.3 to +0.3 VSS - 0.3 to +0.3 VSSL - 0.3 to +0.3 -55 to +125 Unit V V V V V V V V V V V V V C
q Recommended Operating Conditions
(VDD = 0 V)
Parameter Operating temperature Operating voltage 400 kHz OSC external resistance Crystal oscillation frequency Symbol Top VSS1 VSS ROS fXT Condition -- -- -- -- -- Range -40 to +85 -1.7 to -1.25 -5.25 to VSS1 250 to 500 30 to 35 Unit C V V k kHz
Appendix-54
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS1 = VSS = -1.5 V, Ta = -40 to +85C unless otherwise mentioned) (1/5)
Parameter VSS2 voltage VSS3 voltage VSSL voltage XTOSC oscillation start voltage XTOSC oscillation maintaining voltage XTOSC stop detection time XTOSC internal capacitance XTOSC external capacitance XTOSC internal capacitance 400kOSC internal capacitance 400kOSC oscillation frequency fOSC External resistance ROS = 300 kW VSS1 = -1.25 to -1.7 V POR generation voltage POR non-generation voltage VPOR2 VPOR1 VSS1 is within VPOR1 to -1.5 V and POR generated VSS1 is within VPOR2 to -1.5 V and no POR -1.5 -- -1.2 V -0.4 -- 0 V 80 220 350 kHz COS -- 8 12 16 pF CD -- 10 15 20 pF CGEX CG external option 10 -- 30 pF CG -- 10 15 20 pF 1 TSTOP -- 0.1 -- 1000 ms VHOLD Symbol VSS2 VSS3 VSSL VSTA Condition Ca, Cb, C12 = 0.1 mF +100% -50% Ca, Cb, C12 = 0.1 mF +100% -50% -- Min. -3.2 Typ. -3.0 Max. Unit -2.8 V Measuring circuit
-4.7
-4.5
-4.3
V
-1.5
-1.3
-0.6
V
Less than 5 seconds for oscillation starting --
--
--
-1.45
V
--
--
-1.25
V
Notes: * "XTOSC" refers to the 32.768 kHz crystal oscillation circuit. * "400kOSC" refers to the 400 kHz RC oscillation circuit. * "POR" refers to Power-On Reset. * "TSTOP" refers to the generation of system reset when XTOSC stops oscillation for more than this duration.
Appendix-55
MSM64164C User's Manual Appendix G l DC Characteristics (VDD = 0 V, VSS1 = VSS = -1.5 V, Ta = -40 to +85C unless otherwise mentioned) (2/5)
Parameter Supply current 1 Supply current 2 Supply current 3 Supply current 4 IDD4 IDD3 IDD2 Symbol IDD1 CPU in halt state (400kOSC halt) CPU in operation state (400kOSC halt) CPU in operation state (400kOSC in operation) Serial transfer, fSCK = 300 kHz, CPU in operation state (400kOSC halt) Supply current 5 IDD5 CPU in halt state (400kOSC halt), A/D converter in oscillation state RT0 = 2 kW -- 600 900 mA Ta = +40 to +85C RT0 = 10 kW -- -- 7 150 50 230 mA mA Ta = -40 to +40C -- 7 25 mA Condition Ta = -40 to +40C Ta = +40 to +85C Ta = -40 to +40C Ta = +40 to +85C Min. -- -- -- -- -- Typ. 2 2 5 5 40 Max. Unit 5 30 15 40 80 mA mA mA mA mA 1 Measuring circuit
Appendix-56
MSM64164C User's Manual Appendix G l DC Characteristics (VDD = 0 V, VSS1 = VSSL = VSS = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned)
(3/5)
Parameter (pin name) Output current 1 (P1.0) Symbol IOH1 IOL1 IOH1S IOL1S Output current 2 (P1.1 to P1.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Output current 3 (BD) Output current 4 (RT0, RT1, RS0, RS1, CRT0, CS0, CS1) Output current 5 (when L26 to L33 are output ports) IOH2 IOL2 IOH2S IOL2S IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 IOH5S IOL5S Output current 6 (OSC2) Output current 7 (L0 to L33) IOH6 IOL6 IOH7 IOMH7 IOMH7S IOML7 IOML7S IOL7 Output leak
(P1.0 to P1.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1)
Condition VOH1 = -0.5 V VOL1 = VSS + 0.5 V VSS = -5 V, VOH1S = -0.5 V VSS = -5 V, VOL1 = VSS + 0.5 V VOH2 = -0.5 V VOL2 = VSS + 0.5 V VSS = -5 V, VOH2S = -0.5 V VSS = -5 V, VOL2 = VSS + 0.5 V VOH3 = -0.7 V VOL3 = VSS1 + 0.7 V VOH4 = -0.1 V VOL4 = VSS1 + 0.1 V VOH5 = -0.5 V VOL5 = VSS + 0.5 V VSS = -5 V, VOH5S = -0.5 V VSS = -5 V, VOL5S = VSS + 0.5 V VOH6 = -0.5 V VOL6 = VSS1 + 0.5 V VOH7 = -0.2 V (VDD level) VOMH7 = VSS1 + 0.2 V (VSS1 level) VOMH7S = VSS1 - 0.2 V (VSS1 level) VOML7 = VSS2 + 0.2 V (VSS2 level) VOML7S = VSS2 - 0.2 V (VSS2 level) VOL7 = VSS3 + 0.2 V (VSS3 level) VOH = VDD VOL = VSS1
Min. -2.1 1 -36 4 -2.1 0.2 -9 1 -1.8 0.2 -1.1
Typ. -0.7 3 -12 12 -0.7 0.7 -3 3 -0.6 0.6 -0.6
Max. Unit -0.2 9 -4 36 -0.2 2.1 -1 9 -0.2 1.8 -0.3 mA mA mA mA mA mA mA mA mA mA mA
Measuring circuit
0.3 -1.5 0.1 -2.0 0.2 -2.1 0.2 -- 4 -- 4 -- 4 --
0.6 -0.5 0.5 -0.7 0.7 -0.7 0.7 -- -- -- -- -- -- --
1.1 -0.1 1.5 -0.2 2.0 -0.2 2.1 -4 -- -4 -- -4 -- 0.3
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2
IOOH IOOL
-0.3
--
--
mA
Appendix-57
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS1 = VSSL = VSS = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned) (4/5)
Parameter (pin name) Input current 1 (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Symbol IIH1 IIL1 IIH1S IIL1S IIH1Z IIL1Z Input current 2 (IN0, IN1) IIH2 IIH2Z IIL2Z Input current 3 (OSC1) IIL3 IIH3Z IIL3Z Input current 4 (RESET, TST1, TST2) Input voltage 1 (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Input voltage 2 (IN0, IN1, OSC1) Input voltage 3 (RESET, TST1, TST2) IIH4 IIL4 VIH1 VIL1 VIH1S VIL1S VIH2 VIL2 VIH3 VIL3 VSS = -5 V VSS = -5 V -- -- -- -- Condition VIH1 = VDD (pull-down) VIL1 = VSS (pull-up) VIH1 = VDD, VSS = -5 V (pull-down) VIH1 = VSS = -5 V (pull-up) VIH1 = VDD (high-impedance) VIL1 = VSS (high-impedance) VIH2 = VDD (pull-down) VIH2 = VDD (high-impedance) VIL2 = VSS1 (high-impedance) VIL3 = VSS1 (pull-up) VIH3 = VDD (high-impedance) VIL3 = VSS1 (high-impedance) VIH4 = VDD VIL4 = VSS1 -- -- Min. 5 -60 70 Typ. 18 -18 250 Max. Unit 60 -5 660 -70 1 0 60 1 0 -6 1 0 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V 4 3 Measuring circuit
-660 -250 0 -1 5 0 -1 -60 0 -1 0 -- -- 18 -- -- -22 -- -- --
-1.5 -0.75 -0.3 -0.3 -1.5 -1 -5 -0.3 -1.5 -0.3 -1.5 -- -- -- -- -- -- -- -- 0 -1.2 0 -4 0 -1.2 0 -1.2
Appendix-58
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS1 = VSSL = VSS = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned) (5/5)
Parameter (pin name) Hysteresis width (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Hysteresis width (RESET, TST1, TST2) Input pin capacitance (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Symbol Condition Min. Typ. Max. Unit Measuring circuit
DVT1 DVT1S DVT2 VSS = -5 V
--
0.05
0.1
0.3
V
0.25
1.0
1.5
V
4
--
0.05
0.1
0.3
V
CIN
--
--
--
5
pF
1
Appendix-59
MSM64164C User's Manual Appendix G Measuring circuit 1
CS0 RT0 RI0
RT0 OSC1
CS0
IN0
XT XTAL
ROS OSC2
XT C1 C12 C2 VSSL VDD VSS1 VSS2 VSS3 VSS
A CL V
Ca V
Cb V
Ca, Cb, C12, CL ROS XTAL RT0 CS0 RI0
: : : : : :
0.1 F 300 k 32.768 kHz 10 k/2 k 820 pF 10 k
Measuring circuit 2
(Note 2)
OUTPUT
VIH (Note 1) VIL
INPUTS
A
VDD
VSS1
VSS2
VSS3
VSSL
VSS
Appendix-60
MSM64164C User's Manual Appendix G Measuring circuit 3
(Note 3)
A
VDD
VSS1
VSS2
VSS3
VSSL
VSS
Measuring circuit 4
OUTPUT
VDD VSS1 VSS2 VSS3 VSSL VSS
INPUTS
VIH (Note 3) VIL
OUTPUT
Waveform Monitoring
Note 1: Input logic circuit to determine the specified measuring conditions. Note 2: Measured at the specified output pins. Note 3: Measured at the specified input pins.
INPUTS
Appendix-61
MSM64164C User's Manual Appendix G q A/D Converter Characteristics (VDD = 0 V, VSS1 = VSS = -1.5 V,Ta = -40 to +85C unless otherwise mentioned)
Measuring circuit
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Resistor for oscillation RS0, RS1, RT0, CS0, CT0, CS1 740 pF RT0-1, RT1 Input current limiting resistor Oscillation frequency RI0, RI1 fOSC1 fOSC2 fOSC3 RS*RT oscillation frequency ratio (NOTE) Kf1 Kf2 Kf3 -- Resistor for oscillation = 2 kW Resistor for oscillation = 10 kW
2
--
--
kW
1 165 41.8
10 221 52.2 3.04 4.18 1
-- 256 60.6 3.53 4.35 1.010
kW kHz kHz kHz -- -- 5
Resistor for oscillation = 200 kW 2.55 RT0, RT0-1, RT1 = 2 kW RT0, RT0-1, RT1 = 10 kW RT0, RT0-1, RT1 = 200 kW 3.89 0.990
0.0561 0.0584 0.0637 --
(NOTE) Kfx is the ratio of the oscillation frequency by a sensor resistor and the oscillation frequency by a reference resistor in the same condition. fOSCx(RT0-CS0 Oscillation) fOSCx(RS0-CS0 Oscillation) (x = 1, 2, 3) , fOSCx(RT0-1-CS0 Oscillation) fOSCx(RS0-CS0 Oscillation) , fOSCx(RT1-CS1 Oscillation) fOSCx(RS1-CS1 Oscillation)
Kfx =
Measuring circuit 5
(CROSC1)
RS1 CS1 CS0 RT1 RI1 RI0
(CROSC0)
RS0 RT0-1 CT0 RT0
Oscillation mode designation
RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VDD
IN0 CS0 RS0
CRT0
RT0
P4.3 D.U.T.
Frequency measurement (fOSCx)
VSSL
VSS
VSS1
RT0, RT0-1, RT1 = 2 kW/10 kW/200 kW RS0, RS1 = 10 kW RI0, RI1 = 10 kW CS0, CT0, CS1 = 820 pF CL = 0.1 mF
CL
Appendix-62
MSM64164C User's Manual Appendix G q AC Characteristics (Serial interface, VDD = 0 V, VSS1 = -1.5 V, VSS = -5.0 V, Ta = -40 to +85C)
Parameter (pin name) SCLK input fall time SCLK input rise time SCLK input "L" level pulse width SCLK input "H" level pulse width SCLK input cycle time SCLK output cycle time SCLK output cycle time SOUT output delay time SIN input setup time SIN input hold time
Symbol tf tr tCWL tCWH tCYC tCYC1 (O) tCYC2 (O) tDDR tDS tDH
Condition -- -- -- -- -- CPU operated at 32 kHz CPU operated at 400 kHz CL = 10 pF -- --
Min. -- -- 0.8 0.8 2.0 -- -- -- 0.5 0.8
Typ. -- -- -- -- -- 30.5 4.5 -- -- --
Max. Unit 1 1 -- -- -- -- -- 0.4 -- -- ms ms ms ms ms ms ms ms ms ms
q AC Characteristics Timing ("H" level = -1 V, "L" level = -4 V)
tCYC SCLK (P4.2) tr tCWH tDDR SOUT (P4.0) tDDR 0V tf tCWL 0V
tDS SIN (P3.3)
tDH
tDS 0V
Appendix-63
MSM64164C User's Manual Appendix G (2) 3.0 V Spec. q Absolute Maximum Ratings
(VDD = 0 V)
Parameter Power supply voltage 1 Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 Input voltage 1 Input voltage 2 Input voltage 3 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Storage temperature Symbol VSS1 VSS2 VSS3 VSSL VSS VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 VOUT4 TSTG Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C VSS2 input, Ta = 25C VSS input, Ta = 25C VSSL input, Ta = 25C VSS2 output, Ta = 25C VSS3 output, Ta = 25C VSS output, Ta = 25C VSSL output, Ta = 25C -- Rating -2.0 to +0.3 -4.0 to +0.3 -5.5 to +0.3 -4.0 to +0.3 -5.5 to +0.3 VSS2 - 0.3 to +0.3 VSS - 0.3 to +0.3 VSSL - 0.3 to +0.3 VSS2 - 0.3 to +0.3 VSS3 - 0.3 to +0.3 VSS - 0.3 to +0.3 VSSL - 0.3 to +0.3 -55 to +125 Unit V V V V V V V V V V V V C
q Recommended Operating Conditions
(VDD = 0 V)
Parameter Operating temperature Symbol Top VSS2 Operating voltage VSS 400 kHz OSC external resistance Crystal oscillation frequency ROS fXT Condition -- Using LCD with "duty 1/2" Except using LCD with "duty 1/2" (Note) Range -40 to +85 -3.5 to -2.2 -3.5 to -2.0 -5.25 to (0.8 x VSS2, MAX -2.0) 90 to 500 30 to 66 Unit C V
V
-- --
k kHz
Note : Upper limit of VSS is 80% of VSS2 level and is -2.0 V maximum.
Appendix-64
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS2 = VSS = -3.0 V, Ta = -40 to +85C unless otherwise mentioned)
(1/5)
Parameter VSS1 voltage VSS3 voltage VSSL voltage XTOSC oscillation start voltage XTOSC oscillation maintaining voltage XTOSC stop detection time XTOSC internal capacitance XTOSC external capacitance XTOSC internal capacitance 400kOSC internal capacitance 400kOSC oscillation frequency fOSC External resistance ROS = 100 kW VSS2 = -2.0 to -3.5 V POR generation voltage POR non-generation voltage VPOR2 VPOR1 VSS2 is within VPOR1 to -3.0 V and POR generated VSS2 is within VPOR2 to -3.0 V and no POR -3 -- -2 V -0.7 -- 0 V 300 400 620 kHz COS -- 8 12 16 pF CD -- 10 15 20 pF CGEX CG external option 10 -- 30 pF CG -- 10 15 20 pF 1 TSTOP -- 0.1 -- 1000 ms VHOLD Symbol VSS1 VSS3 VSSL VSTA Condition Ca, Cb, C12 = 0.1 mF +100% -50% Ca, Cb, C12 = 0.1 mF +100% -50% -- Min. -1.7 Typ. -1.5 Max. Unit -1.3 V Measuring circuit
-4.7
-4.5
-4.3
V
-1.9
-1.3
-0.6
V
Less than 5 seconds for oscillation starting --
--
--
-2.0
V
--
--
-2.0
V
Notes: * "XTOSC" refers to the 32.768 kHz crystal oscillation circuit. * "400kOSC" refers to the 400 kHz RC oscillation circuit. * "POR" refers to Power-On Reset. * "TSTOP" refers to the generation of system reset when XTOSC stops oscillation for more than this duration.
Appendix-65
MSM64164C User's Manual Appendix G l DC Characteristics (VDD = 0 V, VSS2 = VSS = -3.0 V, Ta = -40 to +85C unless otherwise mentioned) (2/5)
Parameter Supply current 1 Supply current 2 Supply current 3 Supply current 4 IDD4 IDD3 IDD2 Symbol IDD1 CPU in halt state (400kOSC halt) CPU in operation state (400kOSC halt) CPU in operation state (400kOSC in operation) Serial transfer, fSCK = 300 kHz, CPU in operation state (400kOSC halt) Supply current 5 IDD5 CPU in halt state (400kOSC halt), A/D converter in oscillation state RT0 = 2 kW -- 1200 2000 mA Ta = +40 to +85C RT0 = 10 kW -- -- 7 300 50 450 mA mA Ta = -40 to +40C -- 7 25 mA Condition Ta = -40 to +40C Ta = +40 to +85C Ta = -40 to +40C Ta = +40 to +85C Min. -- -- -- -- -- Typ. 1.5 1.5 5 5 220 Max. Unit 4.5 30 15 40 450 mA mA mA mA mA 1 Measuring circuit
Appendix-66
MSM64164C User's Manual Appendix G l DC Characteristics (VDD = 0 V, VSS1 = VSSL = VSS = -1.5 V, VSS2 = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned) (3/5)
Parameter (pin name) Output current 1 (P1.0) Symbol IOH1 IOL1 IOH1S IOL1S Output current 2 (P1.1 to P1.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Output current 3 (BD) Output current 4 (RT0, RT1, RS0, RS1, CRT0, CS0, CS1) Output current 5 (when L26 to L33 are output ports) IOH2 IOL2 IOH2S IOL2S IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 IOH5S IOL5S Output current 6 (OSC2) Output current 7 (L0 to L33) IOH6 IOL6 IOH7 IOMH7 IOMH7S IOML7 IOML7S IOL7 Output leak
(P1.0 to P1.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1)
Condition VOH1 = -0.5 V VOL1 = VSS + 0.5 V VSS = -5 V, VOH1S = -0.5 V VSS = -5 V, VOL1 = VSS + 0.5 V VOH2 = -0.5 V VOL2 = VSS + 0.5 V VSS = -5 V, VOH2S = -0.5 V VSS = -5 V, VOL2 = VSS + 0.5 V VOH3 = -0.7 V VOL3 = VSS2 + 0.7 V VOH4 = -0.1 V VOL4 = VSS2 + 0.1 V VOH5 = -0.5 V VOL5 = VSS + 0.5 V VSS = -5 V, VOH5S = -0.5 V VSS = -5 V, VOL5S = VSS + 0.5 V VOH6 = -0.5 V VOL6 = VSS2 + 0.5 V VOH7 = -0.2 V (VDD level) VOMH7 = VSS1 + 0.2 V (VSS1 level) VOMH7S = VSS1 - 0.2 V (VSS1 level) VOML7 = VSS2 + 0.2 V (VSS2 level) VOML7S = VSS2 - 0.2 V (VSS2 level) VOL7 = VSS3 + 0.2 V (VSS3 level) VOH = VDD VOL = VSS2
Min. -6 3 -36 4 -6 0.7 -9 1 -6 0.7 -2.5
Typ. -2 8 -12 12 -2 2 -3 3 -2 2 -1.3
Max. Unit -0.7 25 -4 36 -0.7 6 -1 9 -0.7 6 -0.7 mA mA mA mA mA mA mA mA mA mA mA
Measuring circuit
0.7 -1.5 0.15 -2.0 0.2 -6 0.7 -- 4 -- 4 -- 4 --
1.3
2.5
mA
-0.6 -0.15 mA 0.6 -0.7 0.7 -2 2 -- -- -- -- -- -- -- 1.5 -0.2 2.0 -0.7 6 -4 -- -4 -- -4 -- 0.3 mA mA mA mA mA mA mA mA mA mA mA mA
2
IOOH IOOL
-0.3
--
--
mA
Appendix-67
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS1 = VSSL = -1.5 V, VSS2 = VSS = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned)
(4/5)
Parameter (pin name) Input current 1 (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Symbol IIH1 IIL1 IIH1S IIL1S IIH1Z IIL1Z Input current 2 (IN0, IN1) IIH2 IIH2Z IIL2Z Input current 3 (OSC1) IIL3 IIH3Z IIL3Z Input current 4 (RESET, TST1, TST2) Input voltage 1 (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Input voltage 2 (IN0, IN1, OSC1) Input voltage 3 (RESET, TST1, TST2) IIH4 IIL4 VIH1 VIL1 VIH1S VIL1S VIH2 VIL2 VIH3 VIL3 VSS = -5 V VSS = -5 V -- -- -- -- Condition VIH1 = VDD (pull-down) VIL1 = VSS (pull-up) VIH1 = VDD, VSS = -5 V (pull-down) VIH1 = VSS = -5 V (pull-up) VIH1 = VDD (high-impedance) VIL1 = VSS (high-impedance) VIH2 = VDD (pull-down) VIH2 = VDD (high-impedance) VIL2 = VSS2 (high-impedance) VIL3 = VSS2 (pull-up) VIH3 = VDD (high-impedance) VIL3 = VSS2 (high-impedance) VIH4 = VDD VIL4 = VSS2 -- -- Min. 30 -300 80 Typ. 90 -90 250 Max. Unit 300 -30 800 -80 1 0 300 1 0 -10 1 0 1 mA mA mA mA mA mA mA mA mA mA mA mA mA 3 Measuring circuit
-800 -250 0 -1 30 0 -1 -- -- 90 -- --
-300 -110 0 -1 0 -3 -0.6 -3.0 -1 -5 -0.6 -3.0 -0.6 -3.0 -- -- --
-1.5 -0.75 mA -- -- -- -- -- -- -- -- 0 -2.4 0 -4 0 -2.4 0 -2.4 V V V V V V V V 4
Appendix-68
MSM64164C User's Manual Appendix G q DC Characteristics (VDD = 0 V, VSS1 = VSSL = -1.5 V, VSS2 = VSS = -3.0 V, VSS3 = -4.5 V, Ta = -40 to +85C, unless otherwise mentioned) (5/5)
Parameter (pin name) Hysteresis width (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Hysteresis width (RESET, TST1, TST2) Input pin capacitance (P0.0 to P0.3) (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) Symbol Condition Min. Typ. Max. Unit Measuring circuit
DVT1 DVT1S DVT2 VSS = -5 V
--
0.2
0.5
1
V
0.25
1.0
1.5
V
4
--
0.2
0.5
1
V
CIN
--
--
--
5
pF
1
Appendix-69
MSM64164C User's Manual Appendix G Measuring circuit 1
CS0 RT0 RI0
RT0 OSC1 ROS OSC2
CS0
IN0
XT XTAL XT C1 C12 C2
VSSL VDD VSS2 VSS1 VSS3
VSS
A CL V
Ca V
Cb V
CL Ca, Cb, C12 ROS XTAL RT0 CS0 RI0 Measuring circuit 2
: : : : : : :
0.47 F 0.1 F 100 k 32.768 kHz 10 k/2 k 820 pF 10 k
(Note 2)
OUTPUT
VIH (Note 1) VIL
INPUTS
A
VDD
VSS1
VSS2
VSS3
VSSL
VSS
Appendix-70
MSM64164C User's Manual Appendix G Measuring circuit 3
(Note 3)
OUTPUT INPUTS
A
VDD
VSS1
VSS2
VSS3
VSSL
VSS
Measuring circuit 4
VIH (Note 3) VIL
OUTPUT
VDD VSS1 VSS2 VSS3 VSSL VSS
INPUTS
Waveform Monitoring
Note 1: Input logic circuit to determine the specified measuring conditions. Note 2: Measured at the specified output pins. Note 3: Measured at the specified input pins.
Appendix-71
MSM64164C User's Manual Appendix G q A/D Converter Characteristics (VDD = 0 V, VSS2 = VSS = -3.0 V,Ta = -40 to +85C unless otherwise mentioned)
Measuring circuit
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
Resistor for oscillation RS0, RS1, RT0, CS0, CT0, CS1 740 pF RT0-1, RT1 Input current limiting resistor Oscillation frequency RI0, RI1 fOSC1 fOSC2 fOSC3 RS*RT oscillation frequency ratio (NOTE) Kf1 Kf2 Kf3 -- Resistor for oscillation = 2 kW Resistor for oscillation = 10 kW
1
--
--
kW
1 200 46.5
10 239 55.4 3.32
-- 277 64.3 3.85
kW kHz kHz kHz -- -- 5
Resistor for oscillation = 200 kW 2.79 RT0, RT0-1, RT1 = 2 kW RT0, RT0-1, RT1 = 10 kW RT0, RT0-1, RT1 = 200 kW
4.115 4.22 4.326 0.990 1 1.010
0.0573 0.0616 0.0659 --
(NOTE) Kfx is the ratio of the oscillation frequency by a sensor resistor and the oscillation frequency by a reference resistor in the same condition. fOSCx(RT0-CS0 Oscillation) fOSCx(RS0-CS0 Oscillation) (x = 1, 2, 3) , fOSCx(RT0-1-CS0 Oscillation) fOSCx(RS0-CS0 Oscillation) , fOSCx(RT1-CS1 Oscillation) fOSCx(RS1-CS1 Oscillation)
Kfx =
Measuring circuit 5
(CROSC1)
RS1 CS1 CS0 RT1 RI1 RI0
(CROSC0)
RS0 RT0-1 CT0 RT0
Oscillation mode designation
RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VDD
IN0 CS0 RS0
CRT0
RT0
P4.3 D.U.T.
Frequency measurement (fOSCx)
VSSL
VSS
VSS2
RT0, RT0-1, RT1 = 2 kW/10 kW/200 kW RS0, RS1 = 10 kW RI0, RI1 = 10 kW CS0, CT0, CS1 = 820 pF CL = 0.47 mF
CL
Appendix-72
MSM64164C User's Manual Appendix G q AC Characteristics (Serial interface, VDD = 0 V, VSS2 = -3.0 V, VSS = -5.0 V, Ta = -40 to +85C)
Parameter (pin name) SCLK input fall time SCLK input rise time SCLK input "L" level pulse width SCLK input "H" level pulse width SCLK input cycle time SCLK output cycle time SCLK output cycle time SOUT output delay time SIN input setup time SIN input hold time
Symbol tf tr tCWL tCWH tCYC tCYC1 (O) tCYC2 (O) tDDR tDS tDH
Condition -- -- -- -- -- CPU operated at 32 kHz CPU operated at 400 kHz CL = 10 pF -- --
Min. -- -- 0.8 0.8 2.0 -- -- -- 0.5 0.8
Typ. -- -- -- -- -- 30.5 2.5 -- -- --
Max. Unit 1 1 -- -- -- -- -- 0.4 -- -- ms ms ms ms ms ms ms ms ms ms
q AC Characteristics Timing ("H" level = -1 V, "L" level = -4 V)
tCYC SCLK (P4.2) tr tCWH tDDR SOUT (P4.0) tDDH 0V tf tCWL 0V
tDS SIN (P3.3)
tDH
tDS 0V
Appendix-73
MSM64164C User's Manual Appendix H Appendix H: Instruction List
"B" indicates the byte length of an instruction. "C" indicates the execution machine cycle number of an instruction.
Mnemonic
ADC ADC ADCB ADCB ADCS ADCS ADS ADS ADSB ADSB AIS AND AND ANDI CAB CAI CAL CAM CAM CAMB CAMB CAMD CLI CMA CMI CZP
Op-code
@XY
B
1 2 1
C
1 2 2 3 1 2 1 2 2 3 1 1 2 2 1 2 4 1 2 2 3 2 2 2 2 4 A, C A, C
Operation
A + M (HL) + C
@XY
2 1
@XY
2 1
@XY
2 1
@XY n4
2 1 1
@XY n4
2 2 1
A + M (XY) + C BA, C BA + Mb (HL) + C BA, C BA + Mb (XY) + C A, C A + M (HL) + C, Skip if Carry = 1 A, C A + M (XY) + C, Skip if Carry = 1 A A + M (HL), Skip if Carry = 1 A A + M (XY), Skip if Carry = 1 BA BA + Mb (HL), Skip if Carry = 1 BA BA + Mb (XY), Skip if Carry = 1 A A + n4, Skip if Carry = 1 A A M (HL) A A M (XY) A A n4
Skip if A = B Skip if A = n4 ST
n4 a11
2 2 1
PC + 2, PC10 to 0
a11, SP
SP - 2
Skip if A = M (HL) Skip if A = M (XY) Skip if BA = Mb (HL) Skip if BA = Mb (XY) Skip if A = M (m8) Skip if L = n4 A
@XY
2 1
@XY m8 n4
2 2 2 2
A
n4 a5
2 1
Skip if M (HL) = n4 ST
PC + 1, PC4 to 0
a5, PC11 to 5 0
SP SP - 2 (a5 indicates the even number between 10H and 1EH.)
Appendix-74
MSM64164C User's Manual Appendix H
Mnemonic
DCA DCH DCL DCM DCM DCMD DCX DCY EOR EOR EORI INA INH INL INM INM INMD INX INY JA JCP JM JP LAB LAH LAI LAL LALB LAM LAM
Op-code
B
1 1 1 1
C
1 1 1 1 2 2 1 1 1 2 2 1 1 1 1 2 2 1 1 1 1 3 2 2 1 1 1 2 1 2 A H L
Operation
A - 1, Skip if A = 0FH H - 1, Skip if H = 0FH L - 1, Skip if L = 0FH
M (HL) M (XY) M (m8)
@XY m8
2 2 1 1 1
M (HL) - 1, Skip if M (HL) = 0FH M (XY) - 1, Skip if M (XY) = 0FH M (m8) - 1, Skip if M (m8) = 0FH
@XY n4
2 2 1 1 1 1
A A A A H L
X Y
X - 1, Skip if X = 0FH Y - 1, Skip if Y = 0FH
A A
A
M (HL) M (XY) n4
A + 1, Skip if A = 0 H + 1, Skip if H = 0 L + 1, Skip if L = 0
M (HL) M (XY) M (m8) X Y
@XY m8
2 2 1 1 1
M (HL) + 1, Skip if M (HL) = 0 M (XY) + 1, Skip if M (XY) = 0 M (m8) + 1, Skip if M (m8) = 0
X + 1, Skip if X = 0 Y + 1, Skip if Y = 0
a6
1 1
a11
2 2 1
n4
1 1 2 1
@XY
2
BA (bit 0 to bit 5) PC5 to 0 a6 PC Mb (HL), BA PC10 to 0 a11 A B A H A n4 (Vertical Stack Instruction) A L BA HL A M (HL) A M (XY)
PC5 to 0
Appendix-75
MSM64164C User's Manual Appendix H
Mnemonic
LAMB LAMB LAMD LAMDB LAMM LAM+ LAMLAX LAY LAYB LBA LBAI LBS0I LBS1I LCAL LHA LHI LHLI LJP LLA LLAB LLI LMA LMA LMAB LMAB LMAD LMADB LMA+ LMA-
Op-code
@XY m8 m8 n2
B
1 2 2 2 1 1 1 1 1 2 2
C
2 3 2 2 1 2 2 1 1 2 2 2 2 2 5 1 2 2 5 1 2 1 1 2 2 3 2 2 2 2 BA
Operation
n8 n3 n3 a12
2 2 2 3 1
n4 n8 a12
2 2 3 1 2
n4
1 1
@XY
2 1
@XY m8 m8
2 2 2 1 1
Mb (HL) BA Mb (XY) A M (m8) BA Mb (m8) A M (HL), H H n2 A M (HL), L L + 1, Skip if L = 0 A M (HL), L L - 1, Skip if L = 0FH A X A Y BA XY B A BA n8 BSR0 n3 BSR1 n3 ST PC + 3, PC a12, SP SP - 2 HA H n4 HL n8 PC a12 LA HL BA L n4 (Vertical Stack Instruction) M (HL) A M (XY) A Mb (HL) BA Mb (XY) BA M (m8) A Mb (m8) BA M (HL) A, L L + 1, Skip if L = 0 M (HL) A, L L - 1, Skip if L = 0FH
Appendix-76
MSM64164C User's Manual Appendix H
Mnemonic
LMBI LMBI LMI LMTB LXA LXI LXYI LYA LYAB LYI NOP OR OR ORI POP POP POP PUSH PUSH PUSH RAL RAR RBC RBE RC RMB RMB RMBD RT RTI RTS
Op-code
n8 @XY, n8 n4 a4
B
2 3 2 2 1
C
2 3 2 3 1 2 2 1 2 2 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 3 5 3 Mb (HL) Mb (XY) M (HL)
Operation
n8 n8 n4
A n4
Mb (HL) X X
T (a4, XY)
n4 n8
2 2 1 2
XY Y
n8
A BA
XY Y
n4
2 1 1
n4
No operation A A A
A
M (HL)
@XY n4 BA HL BSR BA HL BSR
2 2 1 1 1 1 1 1 1 1 1 1 1
A M (XY)
A n4
SP SP SP ST ST ST
SP + 1, BA
ST
SP + 1, HL ST
SP + 1, BSR BA, SP
ST
SP - 1
HL, SP SP - 1
BSR, SP
SP - 1
C A3, A3 A2, A2 A1, A1 A0, A0 C C A0, A0 A1, A1 A2, A2 A3, A3 C BCF BEF C
0 0
0
n2 @XY, n2 m8, n2
1 2 2 1 1 1
M (HL) [n2] M (XY) [n2] M (m8) [n2]
0 0
0
PC ST, SP SP + 2 PC * C * HL * BA PC
ST, SP
SP + 4, MI
1
ST, SP
SP + 2, Then skip
Appendix-77
MSM64164C User's Manual Appendix H
Mnemonic
SBC SBE SC SMB SMB SMBD SUBC SUBC SUBCB SUBCB SUBCS SUBCS SUBS SUBS SUBSB SUBSB TAB TC TMB TMB TMBD XAB XAM XAM XAMB XAMB XAMD XAMDB XAMM XAM+ XAM-
Op-code
B
1 1 1
C
1 1 1 1 2 2 1 2 2 3 1 2 1 2 2 3 1 1 1 2 2 2 1 2 2 3 2 2 1 2 2 BCF BEF C
Operation
1 1
1
n2 @XY, n2 m8, n2
1 2 2 1
M (HL) [n2] M (XY) [n2] M (m8) [n2] A, C
1 1 1
@XY
2 1
@XY
2 1
@XY
2 1
@XY
2 1
@XY n2
2 1 1
A - M (HL) - C A, C A - M (XY) - C BA, C BA - Mb (HL) - C BA, C BA - Mb (XY) - C A, C A - M (HL) - C, Skip if Borrow = 0 A, C A - M (XY) - C, Skip if Borrow = 0 A A - M (HL), Skip if Borrow = 1 A A - M (XY), Skip if Borrow = 1 BA BA - Mb (HL), Skip if Borrow = 1 BA BA - Mb (XY), Skip if Borrow = 1
Skip if A [n2] = 1 Skip if C = 1 Skip if M (HL) [n2] = 1 Skip if M (XY) [n2] = 1 Skip if M (m8) [n2] = 1
n2 @XY, n2 m8, n2
1 2 2 1 1
@XY
2 1
@XY m8 m8 n2
2 2 2 1 1 1
B A M (HL) A M (XY) BA Mb (HL) BA Mb (XY) A M (m8) BA Mb (m8) A M (HL), H A M (HL), L A M (HL), L
A
H
n2
L + 1, Skip if L = 0 L - 1, Skip if L = 0FH
Appendix-78
MSM64164C User's Manual Appendix H [Explanation of Symbols] The meaning of the symbols used in the following sections are explained below. * * * * A .......................................... Accumulator C ......................................... Carry flag B, H, L, X, Y ........................ Working registers BA ....................................... Indicates 8-bit data of the content of B registers (B3 to B0), and accumulators (A3 to A0), with B register at the MSB side 7 B3 6 B2 5 B1 4 B0 3 A3 2 A2 1 A1 0 A0
BA:
* HL ........... ........................
Indicates 8-bit data of the content of H, L registers, with H register at the MSB side 5 H1 4 H0 3 L3 2 L2 1 L1 0 L0
HL:
7 H3
6 H2
* XY ........... ........................
Indicates 8-bit data of the content of X, Y registers, with X register at the MSB side 5 X1 4 X0 3 Y3 2 Y2 1 Y1 0 Y0
XY:
7 X3
6 X2
* BSR .................................
Indicates bank select registers (BSR1, BSR0), bank common flag (BCF) and bank enable flag (BEF) 5 BSR1 4 3 BCF 2 1 BSR0 0
BSR:
7 BEF
6
* M (y) ................................
Indicates 4-bit data memory content in address indicated by y 1 M(y) Indicates 8-bit data memory content in address indicated by y. The data configuration is shown below. The LSB side is always an even address. 3 1 0 M(y) (Even Address) 2 0
3 M(y):
2
* Mb (y) ..............................
7 Mb(y):
6 5 4 M(y+1) (Odd Address)
* T (y) ......... .......................
Indicates 8-bit program memory (ROM) content in address indicated by y (for ROM table data). 5 4 T(y) 3 2 1 0
7 T(y)
6
Appendix-79
MSM64164C User's Manual Appendix H * PC ........... ......................... Indicates content of program counter (max. 12 bit). The PC value is the program memory address. * SP ........... ......................... Indicates content of stack pointer (8-bit). SP value is the stack address in data memory. SP is allocated to 7FH, 7EH addresses of data memory bank0. 7 6 5 4 3 2 1 1 SP6 SP5 SP4 SP3 SP2 SP1 (07FH Address) (07EH Address) 0 1
SP:
* ST ........... ......................... Indicates 8-bit stack content. This is 8-bit data indicated by SP in data memory. The configuration is shown below. 7 ST: 5 4 (SP) (Odd Address) 6 3 2 1 0 (SP-1) (Even Address)
* MI ............ ......................... Indicates the master interrupt enable flag. MI is allocated to 7CH address, bit 0 of data memory bank0. * @XY ................................ Indicates XY indirect addressing mode instruction. An indirect address mode instruction without this symbol is HL indirect addressing.
* nx ............ .......................... Indicates x-bit of immediate data. * In ............. .......................... Indicates n-bit of immediate data. (n = 0, 1, 2 * * *) * ax .................................... Indicates immediate data to be loaded to PC as an x-bit program memory (ROM) address. x-bit is usually from bit 0, but in the table address it is from bit 8. Indicates immediate data to be the low-order 8-bit address for direct addressing to data memory. Indicates value of bit shown as n2 (see figure below) in content of r (data memory, working registers, accumulators, etc.). n2: 11/ 10/ 01/ 00 r: r3 r2 r1 r0
* m8
............................................
* r [n2] ................................
* .................................... * .................................... * ............ ........................ * XH ..................................
Indicates OR. Indicates AND. Indicates exclusive-OR (EOR). "H" indicates that "X" is a hexadecimal value.
Appendix-80
MSM64164C User's Manual Appendix H * Skip if ...... ......................... The next instruction is skipped if the condition is met, that is, the machine cycle time of the next instruction is spent and the instruction is not executed. * Carry ....... ......................... Indicates the carry of an operation result. * Borrow ..... ......................... Indicates the borrow after an operation result.
Appendix-81
MSM64164C User's Manual Appendix H
Appendix-82
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