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| SN74LS194A 4-Bit Bidirectional Universal Shift Register The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL families. http://onsemi.com LOW POWER SCHOTTKY * * * * * Typical Shift Frequency of 36 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA 16 PLASTIC N SUFFIX CASE 648 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS194AN SN74LS194AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 1999 1 December, 1999 - Rev. 6 Publication Order Number: SN74LS194A/D SN74LS194A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 CP 11 S1 10 S0 9 1 MR 2 DSR 3 P0 4 P1 5 P2 6 P3 7 DSL 8 GND LOADING (Note a) PIN NAMES S0, S1 P0 - P3 DSR DSL CP MR Q0 - Q3 Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. http://onsemi.com 2 SN74LS194A LOGIC DIAGRAM P0 10 P1 3 4 P2 5 P3 6 S1 9 S0 2 DSR 7 DSL VCC = PIN 16 GND = PIN 8 = PIN NUMBERS S CP Q0 S CP Q1 S CP Q2 S CP Q3 R CLEAR R CLEAR R CLEAR R CLEAR CP MR 11 1 15 14 13 12 Q0 Q1 Q2 Q3 FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the ON Semiconductor LS195A Universal Shift Register when used in serial or parallel data register transfers. Some of the common features of the two devices are described below: All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers. The four parallel data inputs (P0, P1, P2, P3) are D-type inputs. When both S0 and S1 are HIGH, the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and Q3 outputs respectively following the next LOW to HIGH transition of the clock. The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW. Special logic features of the LS194A design which increase the range of application are described below: Two mode control inputs (S0, S1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 1, etc.) or right to left (shift left, Q3 Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a "do nothing" mode without restricting the HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation. ! !Q http://onsemi.com 3 SN74LS194A MODE SELECT -- TRUTH TABLE OPERATING MODE Reset Hold Shift Left Shift Right Parallel Load INPUTS MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Pn X X X X X X Pn Q0 L q0 q1 q1 L H P0 Q1 L q1 q2 q2 q0 q0 P1 OUTPUTS Q2 L q2 q3 q3 q1 q1 P2 Q3 L q3 L H q2 q2 P3 L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 23 0.5 20 V A mA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Min 25 Typ 36 14 17 19 22 26 30 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions http://onsemi.com 4 SN74LS194A AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tW ts ts th trec Parameter Clock or MR Pulse Width Mode Control Setup Time Data Setup Time Hold time, Any Input Recovery Time Min 20 30 20 0 25 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME(ts) --is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. S0 1/fmax 1.3 V CLOCK tPHL OUTPUT 1.3 V tW tPLH 1.3 V P0 P1 P2 P3 ts(L) th(L) = 0 CLOCK OUTPUT* 1.3 V ts(H) th(H) = 0 1.3 V 1.3 V S1 1.3 V ts(L) th(L) = 0 ts(H) th(H) = 0 (--- IS SHIFT LEFT) DSR DSL OTHER CONDITIONS: S1 = L, MR = H, S0 = H Figure 1. Clock to Output Delays Clock Pulse Width and fmax MR 1.3 V tW trec 1.3 V OTHER CONDITIONS: MR = H OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY CLOCK tPHL OUTPUT Figure 3. Setup (ts) and Hold (th) Time for Serial Data (DSR, DSL) and Parallel Data (P0, P1, P2, P3) (STABLE TIME) 1.3 V S0 S1 1.3 V ts th = 0 CLOCK 1.3 V OTHER CONDITIONS: MR = H ts th = 0 1.3 V OTHER CONDITIONS: S0, S1 = H OTHER CONDITIONS: PO = P1 = P2 = P3 = H Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time Figure 4. Setup (ts) and Hold (th) Time for S Input http://onsemi.com 5 SN74LS194A PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M http://onsemi.com 6 SN74LS194A D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R http://onsemi.com 7 SN74LS194A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 SN74LS194A/D |
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