View AD9850_150075.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation Low Power: 380 mW @ 125 MHz (+5 V) Low Power: 155 mW @ 110 MHz (+3.3 V) Power-Down Function Ultrasmall 28-Lead SSOP Packaging APPLICATIONS Frequency/Phase-Agile Sine-Wave Synthesis Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications
CMOS, 125 MHz Complete DDS Synthesizer AD9850
FUNCTIONAL BLOCK DIAGRAM
+VS REF CLOCK IN MASTER RESET GND DAC RSET HIGH SPEED DDS 32-BIT TUNING WORD FREQUENCY UPDATE/ DATA REGISTER RESET WORD LOAD CLOCK PHASE AND CONTROL WORDS 10-BIT DAC ANALOG OUT
ANALOG IN CLOCK OUT CLOCK OUT
FREQUENCY/PHASE DATA REGISTER
DATA INPUT REGISTER SERIAL LOAD 1-BIT 40 LOADS PARALLEL LOAD
COMPARATOR
AD9850
8-BITS 5 LOADS FREQUENCY, PHASE, AND CONTROL DATA INPUT
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance, D/A converter and comparator, to form a complete digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/ phase-programmable, analog output sine wave. This sine wave can be used directly as a frequency source or converted to a square wave for agile-clock generator applications. The AD9850's innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz, for a 125 MHz reference clock input. The AD9850's circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180, 90, 45, 22.5, 11.25 and any
combination thereof. The AD9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output. This facilitates the device's use as an agile clock generator function. The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; bytes 2-5 comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete-DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (+3.3 V supply). The AD9850 is available in a space saving 28-lead SSOP, surface mount package. It is specified to operate over the extended industrial temperature range of -40C to +85C.
REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9850-SPECIFICATIONS (V = +5 V
S
5% except as noted, RSET = 3.9 k )
Test Level Min AD9850BRS Typ Max Units
Parameter CLOCK INPUT CHARACTERISTICS Frequency Range +5 V Supply +3.3 V Supply Pulsewidth High/Low +5 V Supply +3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current RSET = 3.9 k RSET = 1.95 k Gain Error Gain Temperature Coefficient Output Offset Output Offset Temperature Coefficient Differential Nonlinearity Integral Nonlinearity Output Slew Rate (50 , 2 pF Load) Output Impedance Output Capacitance Voltage Compliance Spurious-Free Dynamic Range (SFDR): Wideband (Nyquist Bandwidth) 1 MHz Analog Out 20 MHz Analog Out 40 MHz Analog Out Narrowband 40.13579 MHz 50 kHz 40.13579 MHz 200 kHz 4.513579 MHz 50 kHz/20.5 MHz CLK 4.513579 MHz 200 kHz/20.5 MHz CLK COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Input Voltage Range Comparator Offset* COMPARATOR OUTPUT CHARACTERISTICS Logic "1" Voltage +5 V Supply Logic "1" Voltage +3.3 V Supply Logic "0" Voltage Propagation Delay, +5 V Supply (15 pF Load) Propagation Delay, +3.3 V Supply (15 pF Load) Rise/Fall Time, +5 V Supply (15 pF Load) Rise/Fall Time, +3.3 V Supply (15 pF Load) Output Jitter (p-p) CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.)
Temp
Full Full +25C +25C
IV IV IV IV
1 1 3.2 4.1
125 110
MHz MHz ns ns
+25C +25C +25C Full +25C Full +25C +25C +25C +25C +25C +25C
V V I V I V I I V IV IV I
10.24 20.48 -10 150 10 50 0.5 0.5 400 120 0.75 1 +10
50
8 1.5
mA mA % FS ppm/C A nA/C LSB LSB V/s k pF V
+25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full Full +25C +25C +25C +25C +25C +25C
IV IV IV IV IV IV IV V IV I IV VI VI VI VI V V V V V IV
63 50 46
72 58 54 80 77 84 84 3
dBc dBc dBc dBc dBc dBc dBc pF k A V mV V V V ns ns ns ns ps %
500 -12 0 30 +4.8 +3.1
+12 VDD 30
+0.4 5.5 7 3 3.5 80 50 10
-2-
REV. E
AD9850
Parameter CMOS LOGIC INPUTS (Including CLKIN) Logic "1" Voltage, +5 V Supply Logic "1" Voltage, +3.3 V Supply Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance POWER SUPPLY (AOUT = 1/3 CLKIN) +VS Current @: 62.5 MHz Clock, +3.3 V Supply 110 MHz Clock, +3.3 V Supply 62.5 MHz Clock, +5 V Supply 125 MHz Clock, +5 V Supply PDISS @: 62.5 MHz Clock, +3.3 V Supply 110 MHz Clock, +3.3 V Supply 62.5 MHz Clock, +5 V Supply 125 MHz Clock, +5 V Supply PDISS Power-Down Mode +5 V Supply +3.3 V Supply
NOTES *Tested by measuring output duty cycle variation. Specifications subject to change without notice.
Temp +25C +25C +25C +25C +25C +25C
Test Level I I I I I V
AD9850BRS Min Typ Max 3.5 3.0 0.4 12 12 3
Units V V V A A pF
Full Full Full Full Full Full Full Full Full Full
VI VI VI VI VI VI VI VI V V
30 47 44 76 100 155 220 380 30 10
48 60 64 96 160 200 320 480
mA mA mA mA mW mW mW mW mW mW
TIMING CHARACTERISTICS* (V = +5 V
S
5% except as noted, RSET = 3.9 k )
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full +25C Test Level IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV IV V AD9850BRS Min Typ Max 3.5 3.5 3.5 3.5 7.0 3.5 7.0 7.0 18 13 7.0 3.5 3.5 5 13 2 5 Units ns ns ns ns ns ns ns ns CLKIN Cycles CLKIN Cycles ns ns ns CLKIN Cycles CLKIN Cycles CLKIN Cycles s
Parameter tDS tDH tWH tWL tWD tCD tFH tFL tCF tFD tRH tRL tRS tOL tRR (Data Setup Time) (Data Hold Time) (W_CLK min. Pulsewidth High) (W_CLK min. Pulsewidth Low) (W_CLK Delay After FQ_UD) (CLKIN Delay After FQ_UD) (FQ_UD High) (FQ_UD Low) (Output Latency from FQ_UD) Frequency Change Phase Change (FQ_UD Min. Delay After W_CLK) (CLKIN Delay After RESET Rising Edge) (RESET Falling Edge After CLKIN) (Minimum RESET Width) (RESET Output Latency) (Recovery from RESET) Wake-Up Time from Power-Down Mode
NOTES *Control functions are asynchronous with CLKIN. Specifications subject to change without notice.
REV. E
-3-
AD9850
ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
Maximum Junction Temperature . . . . . . . . . . . . . . . +165C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 V to +VS Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300C SSOP JA Thermal Impedance . . . . . . . . . . . . . . . . . . 82C/W
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
Test Level I - 100% Production Tested. III - Sample Tested Only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device. Doing so may result in a latch-up condition.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD9850BRS
Temperature Range -40C to +85C
Package Description Shrink Small Outline (SSOP)
Package Option RS-28
-4-
REV. E
AD9850
Table I. Lead Function Descriptions
Pin No. 4-1, 28-25 5, 24 6, 23 7 8 9 10, 19 11, 18 12
Mnemonic D0-D7 DGND DVDD W_CLK FQ_UD CLKIN AGND AVDD RSET
Function 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/ control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word. Digital Ground. These are the ground return leads for the digital circuitry. Supply Voltage Leads for digital circuitry. Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words. Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase) loaded in the data input register, it then resets the pointer to Word 0. Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at 1/2 V supply. The rising edge of this clock initiates operation. Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator). Supply Voltage for the analog circuitry (DAC and comparator). This is the DAC's external RSET connection. This resistor value sets the DAC full-scale output current. For normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 k connected to ground. The RSET/IOUT relationship is: IOUT = 32 (1.248 V/RSET). Output Complement. This is the comparator's complement output. Output True. This is the comparator's true output. Inverting Voltage Input. This is the comparator's negative input. Noninverting Voltage Input. This is the comparator's positive input.
13 14 15 16 17 20 21 22
QOUTB QOUT VINN VINP
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should normally be considered a "no connect" for optimum performance. IOUTB IOUT RESET The Complementary Analog Output of the DAC. Analog Current Output of the DAC. Reset. This is the master reset function; when set high it clears all registers (except the input register) and the DAC output will go to Cosine 0 after additional clock cycles--see Figure 19.
PIN CONFIGURATIONS
D3 D2 D1 LSB D0 DGND DVDD W CLK FQ UD CLKIN 1 2 3 4 5 6 7
28 D4 27 D5 26 D6 25 D7 MSB/SERIAL LOAD 24 DGND 23 DVDD
AD9850
TOP VIEW 8 (Not to Scale) 21 IOUT
22 RESET
9
20 IOUTB 19 AGND 18 AVDD 17 DACBL (NC) 16 VINP 15 VINN
AGND 10 AVDD 11 RSET 12 QOUTB 13 QOUT 14
NC = NO CONNECT
REV. E
-5-
AD9850-Typical Performance Characteristics
CH1 S Spectrum AD9850 10dB/REF -8.6dBm 76.642 dB Fxd
CH1 S
Spectrum AD9850
10dB/REF
-10dBm
59.925 dB Fxd
CLOCK 125MHz
CLOCK 125MHz
0
0
RBW # 100Hz START 0Hz
VBW 100Hz
ATN # 30dB SWP 762 sec STOP 62.5MHz
RBW # 300Hz START 0Hz
VBW 300Hz
ATN # 30dB SWP 182.6 sec STOP 62.5MHz
Figure 1. SFDR, CLKIN = 125 MHz/fOUT = 1 MHz
Figure 4. SFDR, CLKIN = 125 MHz/fOUT = 20 MHz
CH1 S
Spectrum AD9850
10dB/REF
-10dBm
54.818 dB Fxd
CH1 S
Spectrum AD9850
12dB/REF
0dBm
-85.401 dB -23 kHz Mkr
CLOCK 125MHz
0
0
RBW # 300Hz START 0Hz
VBW 300Hz
ATN # 30dB
SWP 182.6 sec STOP 62.5MHz
RBW # 3Hz VBW 3Hz CENTER 4.513579MHz
ATN # 20dB
SWP 399.5 sec SPAN 400kHz
Figure 2. SFDR, CLKIN = 125 MHz/fOUT = 41 MHz
Figure 5. SFDR, CLKIN = 20.5 MHz/fOUT = 4.5 MHz
Tek Run: 100GS/s ET Sample
-105 PN.3RD
: 300ps @: 25.26ns
-110 -115 -120 -125
dBc
-130 -135 -140 -145
1
-150 -155 100 10k 1k OFFSET FROM 5MHz CARRIER - Hz 100k
Ch 1
500mV
M 20.0ns D 500ps
Ch 1 1.58V Runs After
Figure 3. Typical Comparator Output Jitter, AD9850 Configured as Clock Generator w/42 MHz LP Filter (40 MHz AOUT/125 MHz CLKIN)
Figure 6. Output Residual Phase Noise (5 MHz AOUT/ 125 MHz CLKIN)
-6-
REV. E
AD9850
Tek Run: 50.0GS/s ET Average
Tek Run: 50.0GS/s ET Average
Ch 1 Rise 2.870ns
Ch 1 Fall 3.202ns
1
1
Ch1 1.00V
M 1.00ns Ch 1
1.74V
Ch1 1.00V
M 1.00ns Ch 1
1.74V
Figure 7. Comparator Output Rise Time (5 V Supply/15 pF Load)
Figure 10. Comparator Output Fall Time (5 V Supply/15 pF Load)
68
90
fOUT = 1/3 OF CLKIN
66
SUPPLY CURRENT - mA
80 70 60 50 40 30 20 10
0 20 40 60 80 CLKIN - MHz 100 120 140
64 62 SFDR - dB 60 58 56 54 52 VCC = 3.3V VCC = 5V
VCC = 5V
VCC = 3.3V
0
20
40 60 80 100 CLOCK FREQUENCY - MHz
120
140
Figure 8. SFDR vs. CLKIN Frequency (AOUT = 1/3 of CLKIN)
Figure 11. Supply Current vs. CLKIN Frequency (AOUT = 1/3 of CLKIN)
90
75
80
SUPPLY CURRENT - mA
70
VCC = 5V
fOUT = 1MHz
70 SFDR - dB
65
60
60
fOUT = 20MHz
50
VCC = 3.3V
55
fOUT = 40MHz
50
40
30
45
0 10 20 30 FREQUENCY OUT - MHz 40
5
10 15 DAC IOUT - mA
20
Figure 9. Supply Current vs. AOUT Frequency (CLKIN = 125/110 MHz for 5 V/3.3 V Plot)
Figure 12. SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN)
REV. E
-7-
AD9850
+VS GND IOUT 100k 8-b 5 PARALLEL DATA, DATA OR 1-b 40 SERIAL DATA, PROCESSOR BUS RESET, AND 2 CLOCK LINES 100k AD9850 IOUTB VINN XTAL CLK VINP OSC QOUT QOUTB RSET 5-POLE ELLIPTICAL 42MHz LOW-PASS 200 IMPEDANCE LOW-PASS FILTER 200 470pF
IF FREQUENCY IN FILTER 125MHz
FILTER
RF FREQUENCY OUT
AD9850
COMPLETE-DDS REFERENCE
TUNING WORD
100
a. Frequency/Phase-Agile Local Oscillator
CMOS CLOCK OUTPUTS COMP 200
125MHz
TRUE
AD9850
COMPLETEDDS
FILTER
REFERENCE CLOCK
PHASE COMPARATOR DIVIDE-BY-N
LOOP FILTER
RF FREQUENCY OUT VCO
Figure 13. Basic AD9850 Clock Generator Application with Low-Pass Filter
TUNING WORD
b. Frequency/Phase-Agile Reference for PLL
REF FREQUENCY PHASE COMPARATOR FILTER LOOP FILTER
VCO
Rx IF IN
I 8 I/Q MIXER AD9059 AND DUAL 8-BIT 8 LOW-PASS Q ADC FILTER VCA ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL PN RATE 125MHz
DIGITAL DEMODULATOR
Rx BASEBAND DIGITAL DATA OUT AGC
RF FREQUENCY OUT
ADC ENCODE
PROGRAMMABLE "DIVIDE-BY-N" FUNCTION
AD9850
COMPLETEDDS TUNING WORD
REFERENCE CLOCK
AD9850 32 CLOCK GENERATOR CHIP/SYMBOL/PN RATE DATA
c. Digitally-Programmable "Divide-by-N" Function in PLL Figure 14. AD9850 Clock Generator Application in a Spread-Spectrum Receiver Figure 15. AD9850 Complete-DDS Synthesizer in Frequency Up-Conversion Applications
THEORY OF OPERATION AND APPLICATION
The AD9850 uses direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/phase-agile sine wave. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter, and an onboard high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOScompatible output square wave. DDS technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz with a 125 MHz reference clock applied. The AD9850's output waveform is phase-continuous when changed. The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 16. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2N number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows it wraps around, making the phase accumulator's output contiguous. The frequency tuning word sets the modulus of the counter that effectively determines the size of the increment ( Phase) that gets added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the accumulator overflows, which results in a higher output frequency. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula: fOUT = ( Phase x CLKIN)/232 where: Phase = value of 32-bit tuning word CLKIN = input reference clock frequency in MHz fOUT = frequency of the output signal in MHz The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter that reconstructs the sine
-8-
REV. E
AD9850
REF CLOCK
DDS CIRCUITRY N PHASE ACCUMULATOR AMPLITUDE/COS CONV. ALGORITHM D/A CONVERTER LP COMPARATOR CLK OUT
TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY IN DIGITAL DOMAIN COS (x)
Figure 16. Basic DDS Block Diagram and Signal Flow of AD9850
wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. Since the output of the AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the Reference Clock Frequency the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 17.
fOUT
SIGNAL AMPLITUDE
The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. When in this state, if the clock frequency again exceeds the threshold, the device resumes normal operation. This shutdown mode prevents excessive current leakage in the dynamic registers of the device. The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end-system. The typical application of the AD9850 is with single-ended output/ input analog signals, a single low-pass filter, and generating the comparator reference midpoint from the differential DAC output as shown in Figure 13.
Programming the AD9850
sin(x)/x ENVELOPE fc-fo fc+fo fc
x=(pi)fo/fc
2fc-fo 2fc+fo 3fc-fo
120MHz 20MHz 80MHz 2ND IMAGE FUNDAMENTAL 1ST IMAGE 100MHz REFERENCE CLOCK FREQUENCY
180MHz 3RD IMAGE
220MHz 4TH IMAGE
280MHz 5TH IMAGE
The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word, the 5-bit phase modulation word and the power-down function. This register can be loaded in a parallel or serial mode. In the parallel load mode, the register is loaded via an 8-bit bus; the full 40-bit word requires five iterations of the 8-bit word. The W_CLK and FQ_UD signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to) 40-bit control data word into the device and resets the address pointer to the first register. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register. In serial load mode, subsequent rising edges of W_CLK shift the 1-bit data on Lead 25 (D7) through the 40 bits of programming information. After 40 bits are shifted through, an FQ_UD pulse is required to update the output frequency (or phase). The function assignments of the data and control words are shown in Table III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering-up/down, are shown in the timing diagrams of Figures 18-24. Note: There are specific control codes, used for factory test purposes, that render the AD9850 temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes listed in Table II.
Figure 17. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, depending on the fo/Ref Clk relationship, the first aliased image can be on the order of -3 dB below the fundamental. A low-pass filter is generally placed between the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the selected output frequency and the Reference Clock frequency to avoid unwanted (and unexpected) output anomalies. A good rule-of-thumb for applying the AD9850 as a clock generator is to limit the selected output frequency to <33% of Reference Clock frequency, thereby avoiding generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice will ease the complexity (and cost) of the external filter requirement for the clock generator application.
REV. E
-9-
AD9850
Table II. Factory-Reserved Internal Test Control Codes
Loading Format Parallel Serial
Factory-Reserved Codes 1) W0 = XXXXXX10 2) W0 = XXXXXX01 1) W32 = 1; W33 = 0 2) W32 = 0; W33 = 1 3) W32 = 1; W33 = 1
t CD
DATA W0* W1 W2 W3 W4
t DS
W CLK
tDH
tWH
tWL t FD
t FL
FQ UD
t FH
REF CLK
tCF
COS OUT *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK OLD FREQ (PHASE) VALID DATA NEW FREQ (PHASE)
SYMBOL tDS tDH tWH tWL tCD tFH tFL tFD tCF
DEFINITION
DATA SETUP TIME DATA HOLD TIME W CLK HIGH W CLK LOW CLK DELAY AFTER FQ_UD FQ UD HIGH FQ UD LOW FQ UD DELAY AFTER W CLK OUTPUT LATENCY FROM FQ UD FREQUENCY CHANGE PHASE CHANGE
MIN
3.5ns 3.5ns 3.5ns 3.5ns 3.5ns 7.0ns 7.0ns 7.0ns 18 CLOCK CYCLES 13 CLOCK CYCLES
Figure 18. Parallel-Load Frequency/Phase Update Timing Sequence
Table III. 8-Bit Parallel-Load Data/Control Word Functional Assignment
Word W0 W1 W2 W3 W4
data[7] Phase-b4 (MSB) Freq-b31 (MSB) Freq-b23 Freq-b15 Freq-b7
data[6] Phase-b3 Freq-b30 Freq-b22 Freq-b14 Freq-b6
data[5] Phase-b2 Freq-b29 Freq-b21 Freq-b13 Freq-b5
data[4] Phase-b1 Freq-b28 Freq-b20 Freq-b12 Freq-b4
data[3] Phase-b0 (LSB) Freq-b27 Freq-b19 Freq-b11 Freq-b3
data[2] Power-Down Freq-b26 Freq-b18 Freq-b10 Freq-b2
data[1] Control Freq-b25 Freq-b17 Freq-b9 Freq-b1
data[0] Control Freq-b24 Freq-b16 Freq-b8 Freq-b0 (LSB)
-10-
REV. E
AD9850
REF CLK
tRH
RESET
tRL
tRR
tRS tOL
COS OUT COS (0)
SYMBOL tRH tRL tRR tRS tOL
DEFINITION
CLK DELAY AFTER RESET RISING EDGE RESET FALLING EDGE AFTER CLK RECOVERY FROM RESET MINIMUM RESET WIDTH RESET OUTPUT LATENCY
MIN SPEC
3.5ns 3.5ns 2 CLK CYCLES 5 CLK CYCLES 13 CLK CYCLES
RESULTS OF RESET: - FREQUENCY/PHASE REGISTER SET TO 0 - ADDRESS POINTER RESET TO W0 - POWER-DOWN BIT RESET TO "0" - DATA INPUT REGISTER UNEFFECTED
Figure 19. Master Reset Timing Sequence
DATA (W0)
XXXXX100
W CLK
FQ UD
REF CLK
DAC STROBE INTERNAL CLOCKS DISABLED
Figure 20. Parallel-Load Power-Down Sequence/Internal Operation
DATA (W0)
XXXXX000
W CLK
FQ UD
REF CLK INTERNAL CLOCKS ENABLED
Figure 21. Parallel-Load Power-Up Sequence/Internal Operation
REV. E
-11-
AD9850
DATA (W0) (PARALLEL) DATA (SERIAL) REQUIRED TO RESET CONTROL REGISTERS XXXXX011
W32 = 0
W33 = 0
W34 = 0
NOTE: AT LEAST FIRST 8 BITS OF 40-BIT SERIAL LOAD WORD ARE REQUIRED TO SHIFT IN REQUIRED W32-W34 DATA W CLK
FQ UD
ENABLE SERIAL MODE
RESET CONTROL WORDS
NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARD-WIRE LEAD 2 AT "0", LEAD 3 AT "1", AND LEAD 4 AT "1" (SEE FIGURE 23).
Figure 22. Serial-Load Enable Sequence
2
+V SUPPLY
3 4
AD9850BRS
Figure 23. Leads 2-4 Connection for Default Serial-Mode Operation
DATA -
W0
W1
W2
W3
W39
FQ UD
W CLK 40 W CLK CYCLES
Figure 24. Serial-Load Frequency/Phase Update Sequence
Table IV. 40-Bit Serial-Load Word Function Assignment
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
Freq-b0 (LSB) Freq-b1 Freq-b2 Freq-b3 Freq-b4 Freq-b5 Freq-b6 Freq-b7 Freq-b8 Freq-b9 Freq-b10 Freq-b11 Freq-b12 Freq-b13
W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27
Freq-b14 Freq-b15 Freq-b16 Freq-b17 Freq-b18 Freq-b19 Freq-b20 Freq-b21 Freq-b22 Freq-b23 Freq-b24 Freq-b25 Freq-b26 Freq-b27
W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39
Freq-b28 Freq-b29 Freq-b30 Freq-b31 (MSB) Control Control Power-Down Phase-b0 (LSB) Phase-b1 Phase-b2 Phase-b3 Phase-b4 (MSB)
-12-
REV. E
AD9850
DATA (7) - W32=0 W33=0 W34=1 W35=X W36=X W37=X W38=X W39=X
FQ UD
W CLK
Figure 25. Serial-Load Power-Down Sequence
VCC
VCC
VCC
VCC
QOUT/ QOUTB
VINP/ VINN
DIGITAL IN
IOUT IOUTB
DAC Output
Comparator Output
Comparator Input
Digital Inputs
Figure 26. AD9850 I/O Equivalent Circuits
PCB LAYOUT INFORMATION
Evaluation Boards
The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 27-30) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolution design and layout practices. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should be free of etched traces that cause discontinuities in the planes. It is recommended that the top layer of the multilayer board also contain interspatial ground plane, which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist, they should be connected together at the AD9850 for optimum results. Avoid running digital lines under the device as these will couple noise onto the die. The power supply lines to the AD9850 should use as large a track as possible to provide a low-impedance path and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signal paths. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the circuit board. Use microstrip techniques where possible. Good decoupling is also an important consideration. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with high quality ceramic capacitors. To achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is recommended that the system's AVDD supply be used. Analog Devices, Inc., applications engineering support is available to answer additional questions on grounding and PCB layout. Call 1-800-ANALOGD.
Two versions of evaluation boards are available for the AD9850, which facilitate the implementation of the device for benchtop analysis, and serve as a reference for PCB layout. The AD9850/FSPCB is intended for applications where the device will primarily be used as frequency synthesizer. This version facilitates connection of the AD9850's internal D/A converter output to a 50 spectrum analyzer input; the internal comparator on the AD9850 DUT is not enabled (see Figure 28 for electrical schematic of AD9850/FSPCB). The AD9850/CGPCB is intended for applications using the device in the clock generator mode. It connects the AD9850's DAC output to the internal comparator input via a single-ended, 42 MHz low-pass, 5pole Elliptical filter. This model facilitates the access of the AD9850's comparator output for evaluation of the device as a frequency- and phase-agile clock source (see Figure 29 for electrical schematic of AD9850/CGPCB). Both versions of the AD9850 evaluation boards are designed to interface to the parallel printer port of a PC. The operating software runs under Microsoft(R) Windows and provides a userfriendly and intuitive format for controlling the functionality and observing the performance of the device. The 3.5" floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen. The evaluation board may be operated with +3.3 V or +5 V supplies. The evaluation boards are configured at the factory for an external reference clock input; if the onboard crystal clock source is used, remove R2.
All trademarks are the property of their respective holders.
REV. E
-13-
AD9850
AD9850 Evaluation Board Instructions Required hardware/software:
IBM compatible computer operating in a Windows environment Printer port, 3.5" floppy drive and Centronics compatible printer cable. XTAL clock or signal generator--if using a signal generator, dc offset the signal to one-half the supply voltage and apply at least 3 V p-p signal across the 50 (R2) input resistor. Remove R2 for high Z clock input. AD9850 evaluation board software disk and AD9850/FSPCB or AD9850/CGPCB evaluation board. +5 V voltage supply
Setup:
Locate the "CLOCK" box and place the cursor in the frequency box. Type in the clock frequency (in MHz) that you will be applying to the AD9850. Click the LOAD button or press enter on the keyboard. Move the cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in MHz). Click the "LOAD" button or press the enter key. The BUS MONITOR section of the control panel will show the 32-bit word that was loaded into the AD9850. Upon completion of this step, the AD9850 output should be active and outputting your frequency information. Changing the output phase is accomplished by clicking on the "down arrow" in the OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button. Other operational modes (Frequency Sweeping, Sleep, Serial Input) are available to the user via keyboard/mouse control. The AD9850/FSPCB provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). The two active inputs are labeled TP1 and TP2. The unmarked hole next to each labeled test point is a ground connection. The two active outputs are labeled TP5 and TP6. Unmarked ground connections are adjacent to each of these test points. The AD9850/CGPCB provides BNC inputs and outputs associated with the on-chip comparator and the onboard, 5th order, 200 ohm input/output Z, elliptic 45 MHz low-pass filter. Jumpering (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connects the onboard filter and the midpoint switching voltage to the comparator. Users may elect to insert their own filter and comparator threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold voltage at E1. If you choose to use the XTAL socket to supply the clock to the AD9850, you must remove R2 (a 50 ohm chip resistor). The crystal oscillator must be either TTL or CMOS (preferably) compatible.
Copy the contents of the AD9850 disk onto your hard drive (there are three files). Connect the printer cable from computer to the AD9850 evaluation board. Apply power to AD9850 evaluation board. The AD9850 is powered separately from the connector marked "DUT +V." The AD9850 may be powered with 3.3 V to +5 V. Connect external 50 ohm clock or remove R2 and apply a high Z input clock such as a crystal "can" oscillator. Locate the file called 9850REV2.EXE and execute that program. Monitor should display a "control panel" to allow operation of the AD9850 evaluation board.
Operation:
On the control panel, locate the box called "COMPUTER I/O." Point to and click the selection marked LPT1 and then point to the "TEST" box and click. A message will appear telling you if your choice of output ports is correct. Choose other ports as necessary to achieve a correct setting. If you have trouble getting your computer to recognize any printer port, try the following: connect three 2K pull-up resistors from Pins 9, 8 and 7 of U3 to +5 V. This will assist "weak" printer port outputs in driving the heavy capacitance load of the printer cable. If troubles persist, try a different printer cable. Locate the "MASTER RESET" button with the mouse and click it. This will reset the AD9850 to 0 Hz, 0 degrees phase. The output should be a dc voltage equal to the full-scale output of the AD9850.
-14-
REV. E
AD9850
C36CRPX J1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P O R T 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 STROBE +V C6 10 F +5V C7 10 F C2 0.1 F C3 0.1 F C4 0.1 F C5 0.1 F C8 0.1 F C9 0.1 F C10 0.1 F WWCLK CHECK RRESET WWCLK FFQUD RRESET 9 8 7 6 5 4 3 2 FFQUD STROBE 10mA RSET TP5 R1 3.9k RRESET 9 8 7 6 5 4 3 2
U2 74HCT574
8D 7D 6D 5D 4D 3D 2D 1D 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 1 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7
J2 +V
H1 #6 D3 1 D3 D2 2 D2 D1 3 D1 D0 4 D0 D4 28 D4 D5 27 D5
H2 #6
H3 #6
H4 #6
BANANA J3 JACKS
J4
+5V GND
MOUNTING HOLES
U1 D6 AD9850
26 D6
D7 25 D7 DGND 24 GND DVDD 23 +V RESET 22 RESET IOUT 21 IOUTB 20 AGND 19 GND AVDD 18 DACBL 17 VINP 16 VINN 15 GND GND R6 1k J5 +V R7 1k GND TP1 +V R5 25 R4 50
GND 5 DGND +V 6 DVDD WCLK 7 W CLK FQUD 8 FQ UD CLKIN 9 CLKIN GND 10 AGND +V 11 AVDD
12 RSET 13 QOUT 14 QOUTB
J6 DAC OUT TO 50
CLK OE
TP2 COMPARATOR TP3 INPUTS TP4
COMPARATOR TP6 OUTPUTS TP7 U3 74HCT574
8D 7D 6D 5D 4D 3D 2D 1D CLK 11 STROBE 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 RESET WCLK FQUD CHECK TP8
GND GND
CLKIN REMOVE WHEN USING Y1 +5V 14 R2 50
XTAL OSC
VCC
Y1
GND 7
OUT
8 +5V R10 2.2k R9 2.2k FFQUD R8 2.2k WWCLK R3 2.2k STROBE
+V
+5V
RRESET
Figure 27. AD9850/FSPCB Electrical Schematic
COMPONENT LIST Integrated Circuits
U1 U2, U3
Capacitors
AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop 0.1 F Ceramic Chip Capacitor 10 F Tantalum Chip Capacitor 3.9 k Resistor 50 Resistor 2.2 k Resistor 25 Resistor 1 k Resistor 36-Pin D Connector Banana Jack BNC Connector
C2-C5, C8-C10 C6, C7
Resistors
R1 R2, R4 R3, R8, R9, R10 R5 R6, R7
Connectors
J1 J2, J3, J4 J5, J6
REV. E
-15-
AD9850
a. AD9850/FSPCB Top Layer
c. AD9850/FSPCB Power Plane
b. AD9850/FSPCB Ground Plane
d. AD9850/FSPCB Bottom Layer
Figure 28. AD9850/FSPCB Evaluation Board Layout
-16-
REV. E
AD9850
C36CRPX J1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P O R T 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 STROBE STROBE WWCLK CHECK RRESET WWCLK FFQUD RRESET 9 8 7 6 5 4 3 2 +5V J9 J8 BNC FFQUD 10mA RSET BNC STROBE RRESET J2 +V
U2 74HCT574
9 8 7 6 5 4 3 2 8D 7D 6D 5D 4D 3D 2D 1D CLK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7
BANANA J3 JACKS
J4
+5V GND
H1 #6
H2 #6
H3 #6
H4 #6
MOUNTING HOLES
D4 28 D4 D5 27 D5
200 Z 42MHz ELLIPTIC LOW PASS FILTER
L1 1008CS 910nH 1 2 C12 3.3pF L2 1008CS 680nH 1 2 C14 8.2pF C13 33pF C15 22pF
D3 D2 D1 D0 GND +V WCLK FQUD CLKIN R1 3.9k
1 2 3 4 5 6 7 8 9
D3 D2 D1 D0 DGND DVDD
U1 D6 AD9850
26 D6
E6 J7 BNC
E5
D7 25 D7 DGND 24 GND DVDD 23 +V
R4 100k R5 100k R8 100 J6
R6 200
C11 22pF
W CLK RESET 22 RESET FQ UD CLKIN IOUT 21 IOUTB 20 AGND 19 GND AVDD 18 DACBL 17 VINP 16 VINN 15 C1 470pF E1 E2 E4 E3 J5 CLKIN R9 2.2k R10 2.2k FFQUD R11 2.2k WWCLK R3 2.2k STROBE REMOVE WHEN USING Y1 +5V 14 VCC R2 50 +V
GND 10 AGND +V 11 AVDD
12 13 14
RSET QOUT QOUTB
R7 200
U3 74HCT574
8D 7D 6D 5D 4D 3D 2D 1D CLK 11 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OE 1 12 13 14 15 16 17 18 19 +V RESET WCLK FQUD CHECK
RRESET
XTAL OSC
Y1
GND 7
OUT
8
+V +5V C6 10 F C7 10 F C2 0.1 F C3 0.1 F C4 0.1 F C5 0.1 F
+5V C8 0.1 F C9 0.1 F C10 0.1 F
Figure 29. AD9850/CGPCB Electrical Schematic
COMPONENT LIST Integrated Circuits
Resistors
U1 U2, U3
Capacitors
AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop 470 pF Ceramic Chip Capacitor 0.1 F Ceramic Chip Capacitor 10 F Tantalum Chip Capacitor 22 pF Ceramic Chip Capacitor 3.3 pF Ceramic Chip Capacitor 33 pF Ceramic Chip Capacitor 8.2 pF Ceramic Chip Capacitor 22 pF Ceramic Chip Capacitor
C1 C2-C5, C8-C10 C6, C7 C11 C12 C13 C14 C15
R1 R2 R3, R9, R10, R11 R4, R5 R6, R7 R8
Connectors
3.9 k Resistor 50 Resistor 2.2 k Resistor 100 k Resistor 200 Resistor 100 Resistor Banana Jack BNC Connector 910 nH Surface Mount 680 nH Surface Mount
J2, J3, J4 J5-J9
Inductors
L1 L2
REV. E
-17-
AD9850
a. AD9850/CGPCB Top Layer
c. AD9850/CGPCB Power Plane
b. AD9850/CGPCB Ground Plane
d. AD9850/CGPCB Bottom Layer
Figure 30. AD9850/CGPCB Evaluation Board Layout
-18-
REV. E
AD9850
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING PLANE
0.009 (0.229) 0.005 (0.127)
8 0
0.03 (0.762) 0.022 (0.558)
REV. E
-19-
PRINTED IN U.S.A.
C2155e-0-5/99

▲Up To Search▲

Price & Availability of AD9850

	To Download AD9850 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .