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FST3306 2-Bit Low Power Bus Switch
February 2001 Revised February 2001
FST3306 2-Bit Low Power Bus Switch
General Description
The FST3306 is a 2-bit ultra high-speed CMOS FET bus switch with TTL-compatible active LOW control inputs. The low on resistance of the switch allows inputs to be connected to outputs with minimal propagation delay and without generating additional ground bounce noise. The device is organized as a 2-bit switch with independent bus enable (BE) controls. When BE is LOW, the switch is ON and Port A is connected to Port B. When BE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. Control inputs tolerate voltages up to 5.5V independent of VCC.
Features
s Typical 3 switch resistance at 5.0V VCC s Minimal propagation delay through the switch s Power down high impedance input/output s Zero bounce in flow through mode. s TTL compatible active LOW control inputs s Control inputs are overvoltage tolerant
Ordering Code:
Order Number FST3306MTC Package Number MTC08 Package Description 8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
(Top View)
Pin Descriptions
Pin Name A B BE Description Bus A Bus B Bus Enable Input
Function Table
Bus Enable Input BE L H
H = HIGH Logic Level L = LOW Logic Level
Function B Connected to A Disconnected
(c) 2001 Fairchild Semiconductor Corporation
DS500479
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FST3306
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Switch Voltage (VS) DC Output Voltage (VIN) (Note 2) DC Input Diode Current (IIK) VIN < 0V DC Output (IOUT) Current DC VCC or Ground Current (ICC/GND) Storage Temperature Range (TSTG) Junction Lead Temperature under Bias (TJ) Lead Temperature (TL) (Soldering, 10 seconds) Power Dissipation (PD) @ +85C
-0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -50 mA
128 mA
Recommended Operating Conditions (Note 3)
Supply Operating (VCC) Control Input Voltage (VIN) Switch Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TA) Input Rise and Fall Time (tr, tf) Control Input Switch I/O Thermal Resistance (JA) 0 ns/V to 5 ns/V 0 ns/V to DC 250C/W 4.0V to 5.5V 0V to 5.5V 0V to 5.5V 0V to 5.5V
-40C to +85C
100 mA -65C to +150C +150C +260C
250 mW
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 3: Unused logic inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH IIN IOFF RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage Input Leakage Current Switch OFF Leakage Current Switch On Resistance (Note 4) VCC (V) 4.5 4.0-5.5 4.0-5.5 4.5-5.5 5.5 5.5 4.5 4.5 4.5 4.0 ICC ICC Quiescent Supply Current Increase in ICC per Input (Note 5) 5.5 5.5 1 3 3 6 10 see Figure 3 1.0 1.0 7 7 15 20 3 2.5 A mA 2.0 0.8 Min TA = -40C to +85C Typ Max -1.2 Units V V V V A A VIN = VCC 0 VIN 5.5V 0 A, B, VCC VIN = 0V, IIN = 64 mA VIN = 0V, IIN = 30 mA VIN = 2.4V, IIN = 15 mA VIN = 2.4V, IIN = 15 mA VIN = VCC or GND, IOUT = 0 VIN = 3.4V, IO = 0, Control Input Only Conditions IIN = -18 mA
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. Note 5: Per TTL driven input (VIN = 3.4V, control input only). A and B pins do not contribute to ICC.
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FST3306
AC Electrical Characteristics
TA = -40C to +85C Symbol tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Output Disable Time Parameter Prop Delay Bus to Bus (Note 6) Output Enable Time 4.5-5.5 4.0 4.5-5.5 4.0 0.8 0.8 0.8 0.8 2.5 3.0 3.1 2.9 4.2 4.6 4.8 4.4 ns ns VI = 7V for tPZL VI = 0V for tPZH VI = 7V for tPLZ VI = 0V for tPHZ VCC (V) 4.0-5.5 CL = 50 pF, RU = RD = 500 Min Typ Max 0.25 ns VI = OPEN Figures 1, 2 Figures 1, 2 Figures 1, 2 Units Conditions Figure Number
Note 6: This parameter is guaranteed. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). The specified limit is calculated on this basis.
Capacitance
Symbol CIN CI/O (OFF) CI/O (ON) Parameter Control Pin Input Capacitance Port OFF Capacitance Switch ON Capacitance Typ 2.5 6 12 Max Units pF pF pF VCC = 0V VCC = 5.0V = BE VCC = 5.0V, BE = 0V Conditions
AC Loading and Waveforms
Input driven by 50 source terminated in 50. CL includes load and stray capacitance. Input PRR = 1.0 MHz tw = 500 ns.
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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FST3306
DC Characteristics
FIGURE 3. Typical High Level Output Voltage vs. Supply Voltage www.fairchildsemi.com 4
FST3306 2-Bit Low Power Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC08 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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