sdh TRANSCEIVER WITH INTERNAL LOOP TIMING
FEATURES * 2.488-Gbps sonet/sdh transceiver with dual differential
serial I/O * Fully integrated CDR, MUX, DEMUX, and CMU * Selectable LVPECL/CMOS 16-bit, 155.52-Mbps interface to framer or networ...
Description
2.488-Gbps Transceiver with Internal Loop Timing 2.488 GBPS sonet/sdh TRANSCEIVER WITH INTERNAL LOOP TIMING 2.488 GBPS sonet/ sdh TRANSCEIVER WITH INTERNAL LOOP TIMING
...ed footprint
Applications
* sdh STM-64 LH * sonet OC-192 LR
Description
The laser module, intended for OC-192/STM-64 applications, consists of a DFB laser with integrated absorption modulator mounted in a high frequency package whic...
...the presence of a receive sonet/sdh bit error rate, the device may destuff the DS1 from the VT1.5 incorrectly. This is the result of an error in the VT1.5 C-bit decoding process. The C-bit decoding process should be capable of correcting si...
Description
TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device
...yload block of the sonet STS-3c/sdh STM-1 frame and sending them to PMD (Physical Media Dependent) in the physical layer, and a receive function for separating the overhead block and ATM cells from the data string received from the PMD subl...
...ub-layer functions in the sonet/sdh-base physical layer within the ATM protocol defined by the ATM Forum's UNI3.1 recommendations. This product's main functions include transmission functions such as mapping of ATM cells sent from the ATM l...
...as a PCI bus interface, a sonet/sdh 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The PD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer.
FE...