...r-Integrated Circuit Bus; CAN = controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array; ADC = Analog-t...drivers VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 drivers
PORT 2 LATCH
ROM/EPROM
...
Description
80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V low power high speed 30/33 MHz
...
Description Local Area Network controller for Ethernet (LANCE) Serial Interface Adapter (SIA) IEEE 802.3/Ethernet/Cheapernet Transceiver CM...drivers which transmit the serial stream to the network. These pins are connected to the copper or f...
Description
Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY⑩-SD) Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY-SD)
...sceiver CMOS Local Area Network controller for EthernetTM (C-LANCE) Integrated Local Area Communications controllerTM (ILACCTM) Media Access...drivers are placed in their inactive state.
DI+, DI-
Data In Output AUI port differential driver...
Description
Twisted-Pair Ethernet Transceiver Plus (TPEX Plus)
.... Interface to the Media Access controller (MAC) layer is established via the standard Media Independent Interface (MII), a 5-bit symbol int...drivers
22235I-1
2
Am79C874
PRELIMINARY
CONNECTION DIAGRAM
TVCC2 TVCC1 TXTX+ TGND2 X...
Description
NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
...e-Chip 10/100 Mbps PCI Ethernet controller with Integrated PHY Am79C976 Am79C978A Am79C874 Am79C901A PCnet-PROTM 10/100 Mbps PCI Ethernet Co...drivers convert the NRZI serial output to MLT-3 format. The RX receivers convert the received MLT-3 ...
Description
NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver NetPHY 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver
controller
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for the Industry Standard Architecture (ISA) and Extended Industr...drivers for transmit, receive, collision, receive polarity, link integrity, or jabber status. The PC...
...ects the CPUs, L2 cache, memory controller and I/O bridges * Runs at half the CPU core frequency; 256 bits wide * 512 KB, shared by both CPU...drivers
Deep Packet Look-up, L4-L7 Processing
BCM1250
OVERVIEW
BCM1250 Block Diagram
...
... connected to a MAC or repeater controller through the MII on one side, and connects directly to the network media on the other side (through isolation transformers for UTP mode or fiber optic transmitter/receiver components for FX modes). ...