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    MUAA8K80M-20B388C MUAA2K80-20QGC03

MUSIC Semiconductors
Part No. MUAA8K80M-20B388C MUAA2K80-20QGC03
OCR Text ...a is wider than the port, it is loaded or unloaded in multiple cycles starting with the least significant word. Internally the device is pipelined; once an operation is started on the synchronous port the next operation may be loaded and th...
Description MUAA Routing CoProcessor (RCP) Family
File Size 264.78K  /  24 Page

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    MU9C3640L-90TZC MU9C3640L-90TZI MU9C3640L-70TZC MU9C3640L MU9C5640L-70TZC MU9C5640L-90TZC MU9C5640L-90TZI

MUSIC Semiconductors
Part No. MU9C3640L-90TZC MU9C3640L-90TZI MU9C3640L-70TZC MU9C3640L MU9C5640L-70TZC MU9C5640L-90TZC MU9C5640L-90TZI
OCR Text ... control interface and commands loaded into the Instruction decoder control the device. A powerful instruction set increases the control flexibility and minimizes software overhead. These and other features make the LIST-XL a powerful assoc...
Description LIST-XL Family
File Size 162.66K  /  22 Page

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    CY7C1484V25-167AXC CY7C1484V25-167AXI CY7C1484V25-167BZC CY7C1484V25-167BZI CY7C1484V25-167BZXC CY7C1484V25-167BZXI CY7C

Cypress Semiconductor
Part No. CY7C1484V25-167AXC CY7C1484V25-167AXI CY7C1484V25-167BZC CY7C1484V25-167BZI CY7C1484V25-167BZXC CY7C1484V25-167BZXI CY7C1484V25-200AXC CY7C1484V25-200AXI CY7C1484V25-200BZC CY7C1484V25-200BZI CY7C1484V25-200BZXC CY7C1484V25-200BZXI CY7C1484V25-250AXC CY7C1484V25-250AXI CY7C1484V25-250BZC CY7C1484V25-250BZI CY7C1484V25-250BZXC CY7C1484V25 CY7C1484V25-250BZXI
OCR Text ... when a new external address is loaded. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. C...
Description 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
File Size 960.50K  /  26 Page

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    HYE18L512320BF-7.5 HYB18L512320BF-7.5

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Qimonda AG
Part No. HYE18L512320BF-7.5 HYB18L512320BF-7.5
OCR Text ...ne which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: defines the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle. In addi...
Description DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM
File Size 923.76K  /  23 Page

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    HYE18L512160BF-7.5 HYB18L512160BF-7.5

Qimonda AG
Part No. HYE18L512160BF-7.5 HYB18L512160BF-7.5
OCR Text ...ine which mode register will be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 A9 define the column address during a READ or WRITE command cycle. I...
Description DRAMs for Mobile Applications 512-Mbit Mobile-RAM
File Size 1,250.40K  /  57 Page

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    HYE18L256169BFX-7.5 HYB18L256169BFX HYB18L256169BFX-7.5

Qimonda AG
Part No. HYE18L256169BFX-7.5 HYB18L256169BFX HYB18L256169BFX-7.5
OCR Text ...ne which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle....
Description DRAMs for Mobile Applications 256-Mbit Mobile-RAM
File Size 1,306.90K  /  47 Page

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    HYE18L256169BF-7.5 HYB18L256169BF-7.5 HYB18L256169BF

Qimonda AG
Part No. HYE18L256169BF-7.5 HYB18L256169BF-7.5 HYB18L256169BF
OCR Text ...ne which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle....
Description 256-Mbit Mobile-RAM
File Size 969.78K  /  48 Page

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    HYE18L256160BFX-7.5 HYE18L256160BCX-7.5 HYB18L256160BFX-7.5 HYB18L256160BCX-7.5

Qimonda AG
Part No. HYE18L256160BFX-7.5 HYE18L256160BCX-7.5 HYB18L256160BFX-7.5 HYB18L256160BCX-7.5
OCR Text ...ne which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle....
Description DRAMs for Mobile Applications 256-Mbit Mobile-RAM
File Size 1,513.96K  /  48 Page

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    HYB18L256160BCL-7.5 HYB18L256160BFL-7.5

Qimonda AG
Part No. HYB18L256160BCL-7.5 HYB18L256160BFL-7.5
OCR Text ...ne which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle....
Description DRAMs for Mobile Applications 256-Mbit Mobile-RAM
File Size 1,793.20K  /  58 Page

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