...oltage (AVDD) or digital supply buffer voltage (DBVDD). The digital supply buffer voltage (DBVDD) must always be less than or equal to the a...divider resistance 0dBFs Full scale output voltage SNR (Note 1,2) SNR (Note 1,2) SNR (Note 1,2) VVMI...
Description
Internet Audio DAC with Integrated Headphone Driver
...oltage (AVDD) or digital supply buffer voltage (DBVDD). The digital supply buffer voltage (DBVDD) must always be less than or equal to the a...divider resistance 0dBFs Full scale output voltage SNR (Note 1,2) SNR (Note 1,2) SNR (Note 1,2) VVMI...
Description
Internet Audio DAC with Integrated Headphone Driver
...e buffered out of the device by buffer amplifiers. These amplifiers will source load current of several mA and sink current up to 1.5mA, so allowing significant loads to be driven. The output source is active and the sink is Class A, i.e. f...
...e buffered out of the device by buffer amplifiers. These amplifiers will source load current of several mA and sink current up to 1.5mA, so allowing significant loads to be driven. The output source is active, the sink is Class A, i.e. fixe...
...oltage (AVDD) or digital supply buffer voltage (DBVDD). The digital supply buffer voltage (DBVDD) must always be less than or equal to the a...divider resistance Line Input to ADC Input Signal Level (0dB) SNR (Note 1,3) SNR (Note 1,3) SNR (Not...
...upply voltage or digital supply buffer voltage. The digital supply buffer voltage must always be less than or equal to the analogue supply v...divider resistance Input to ADC Input Signal Level (0dB) VINLINE AVDD = 3.3V AVDD = 1.8V (WM8739 onl...
...en collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pulldown. ...
Description
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
...en collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down....
Description
2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM
... pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH)...divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VC...
Description
Dual Voltage CPU Supervisor with 64K Serial EEPROM