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lvpecl-to-lvttl Datasheet PDF File

For lvpecl-to-lvttl Found Datasheets File :: 2216 Search Time::2.219ms
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				ONSEMI[ON Semiconductor]
Part No.	NB4N855S NB4N855SMR4 NB4N855SMR4G
OCR Text	...lating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signa...
Description	3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
File Size	130.78K / 10 Page	View it Online	Download Datasheet

				Micrel Semiconductor, Inc. MICREL[Micrel Semiconductor]
Part No.	SY10ELT23L SY10ELT23LZCTR SY10ELT23LZC SY100ELT23L SY100ELT23LZC SY100ELT23LZCTR
OCR Text	lvpecl-to-lvttl TRANSLATOR FEATURES s s s s s s s 3.3V power supply 2.0ns typical propagation delay <500ps typical output-to-output skew Differential LVPECL inputs 24mA LVTTL outputs Flow-through pinouts Available in 8-pin SOIC package ...
Description	3.3V DUAL DIFFERENTIAL lvpecl-to-lvttl TRANSLATOR DUAL PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8
File Size	50.18K / 4 Page	View it Online	Download Datasheet

				ATMEL Corporation
Part No.	ATC18RHA
OCR Text	...nd Receiver differential pads * LVPECL Receiver differential pads Standard pads Input level compatibility * IO18: CMOS * IO33: CMOS,LVTTL co...to 3.3V (max 3.6V) with negligible leakage current. An IO33 standard pad with VCCB=1.8V can also be ...
Description	Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use
File Size	217.03K / 19 Page	View it Online	Download Datasheet

				Agilent(Hewlett-Packard)
Part No.	HDMP-0440
OCR Text	...zers on all inputs * High-speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.5 W typical power a...to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two...
Description	Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
File Size	244.17K / 10 Page	View it Online	Download Datasheet

				Agilent(Hewlett-Packard)
Part No.	HDMP-0450
OCR Text	...zers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.5 W typical power a...to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). FM_NO...
Description	Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
File Size	231.70K / 10 Page	View it Online	Download Datasheet

				Agilent(Hewlett-Packard)
Part No.	HDMP-0452
OCR Text	...zers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.66 W typical power ...to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD). An HD...
Description	Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops
File Size	245.06K / 12 Page	View it Online	Download Datasheet

				Agilent (Hewlett-Packard) Agilent(Hewlett-Packard)
Part No.	HDMP-0480
OCR Text	...zers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.76 W typical power ...to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along...
Description	HDMP-0480 · 1.0625-1.25 GBd Octal Port Bypass Circuit without CDR for Fibre Channel/Storage and GbE Applications Octal Cell Port Bypass Circuit without Clock and Data Recovery
File Size	111.22K / 11 Page	View it Online	Download Datasheet

				Motorola
Part No.	MPC942C
OCR Text	...t clock while the MPC942P has a LVPECL input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200ps, the MPC...
Description	Low Voltage 1:18 Clock Distribution Chlp
File Size	85.96K / 4 Page	View it Online	Download Datasheet

				Agere Systems
Part No.	OR4E2 OR4E4 OR4E6 OR4E10
OCR Text	...Double-ended: LDVS, bused-LVDS, LVPECL. -- Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards. New capability to (de)multiplex I/O signals. -- New DDR on both input and output at rates up to 31...
Description	Field-Programmable Gate Arrays
File Size	1,412.01K / 124 Page	View it Online	Download Datasheet

				ICS
Part No.	M2026
OCR Text	...frequencies of 15 to 700 MHz * LVPECL clock output (CML and LVDS options available) Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock (LOL) output pin; Narrow Bandwidth control i...
Description	SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
File Size	333.73K / 12 Page	View it Online	Download Datasheet

For lvpecl-to-lvttl Found Datasheets File :: 2216 Search Time::2.219ms
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