...as non-ECC modules in 32M x 64 (256 MB), 64M x 64 (512 MB), 128M x 64(1 GB) and as ECC modules in 64M x 72 (512 MB), 128M x 72(1 GB) organiz...512mb DDR2 SDRAMS Not Connected Less than 1gb DDR2 SDRAMS Bank Address Bus 1:0 RAS CAS WE I I NC I I...
...ing specifications * Built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages.
TABLE 1
Performance for -2.5 & -3 (S)
Product Typ...512mb DDR2 SDRAMS Not Connected Less than 1gb DDR2 SDRAMS Bank Address Bus 1:0 RAS CAS WE RESET I I ...
... Non CA parity modules based on 256 Mbit component
Rev. 1.22, 2007-06 07042006-834B-Z31V
7
Internet Data Sheet
HYS72T[64/128]3x0HP-[3S/3.7/5]-A Registered DDR2 SDRAM Modules
Pin No. 174
Name A14 NC
Pin Type I NC I NC
...
...n * 512 MByte module built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages. * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR...512mb DDR2 SDRAMS Not Connected Less than 1gb DDR2 SDRAMS Bank Address Bus 1:0 RAS CAS WE RESET I I ...
...net Data Sheet
HYS72T[64/128/256]4[00/20]HFA-[2.5/3S/3.7]-B Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.1.01, 2007-06-20 P...512mb Modules built with chipsize packages PG-TFBGA-60 * Re-drive and re-sync of all address, comman...
...net Data Sheet
HYS72T[64/128/256]4[00/20]HFD-[3S/3.7]-A
Revision History Revision History: Rev. 1.2, 2006-11-27 All Page 19 All Adapted ...512mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages. * Re-drive and re-sync of all address, command,...
...net Data Sheet
HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B
Revision History Revision History: 2006-11-14, Rev. 1.1 All Page 25 All Adapted ...512mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages. * Re-drive and re-sync of all address, command,...
...net Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD-3S-B
Revision History Revision History: 2007-02-09, Rev. 1.2 All Page 4 Page 20 Adapted...512mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages. * Re-drive and re-sync of all address, command,...
...as non-ECC modules in 32M x 64 (256 MB), 64M x 64 (512 MB) and 128M x 64(1 GB) organization and density, intended for mounting into 200-pin ...512mb DDR2 SDRAMS Less than 1gb DDR2 SDRAMS Bank Address Bus 2:0 RAS CAS WE I I NC I I I SSTL SSTL -...
...), 1gb (128 Meg x 64), and 2GB (256 Meg x 64) * Exclusively designed for high-performance systems * Critical performance parameters tested f...512mb 512mb 1gb 1gb 1gb 2GB MEMORY CLOCK/ DATA BIT RATE 2.5ns/800 MT/s 3.0ns/667 MT/s 1.87ns/1066 MT...