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    MT8940-1 MT8940AE

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8940-1 MT8940AE
OCR Text ...ding on the output of the phase comparison, the master clock frequency is corrected. The MT8940 achieves the frequency correction in both directions by using the master clock at a slightly higher frequency and dividing it unaltered or stret...
Description ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL
ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL

File Size 132.04K  /  19 Page

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    MT8940AC MT8940AE

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8940AC MT8940AE
OCR Text ...ding on the output of the phase comparison, the master clock frequency is corrected. The MT8940 achieves the frequency correction in both directions by using the master clock at a slightly higher frequency and dividing it unaltered or stret...
Description T1/CEPT Digital Trunk PLL

File Size 204.10K  /  16 Page

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    MT8940 MT8940AE

MITEL[Mitel Networks Corporation]
Part No. MT8940 MT8940AE
OCR Text ...ding on the output of the phase comparison, the master clock frequency is corrected. The MT8940 achieves the frequency correction in both directions by using the master clock at a slightly higher frequency and dividing it unaltered or stret...
Description ISO-CMOS ST-BUSFAMILY T1/CEPT Digital Trunk PLL
ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL
ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL

File Size 116.52K  /  16 Page

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    MT8941B MT8941BE MT8941BP

MITEL[Mitel Networks Corporation]
Part No. MT8941B MT8941BE MT8941BP
OCR Text ...ding on the output of the phase comparison, the master clock frequency is corrected. Master clock (12.352 MHz / 16.384 MHz) Internal 8 kHz correction CS F0b (DPLL #2) speed-up region correction slow-down region tCS no-correction ...
Description CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL

File Size 130.44K  /  22 Page

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    MT8941 MT8941AE MT8941AP

MITEL[Mitel Networks Corporation]
Part No. MT8941 MT8941AE MT8941AP
OCR Text ...ding on the output of the phase comparison, the master clock frequency is corrected. Master clock (12.352 MHz / 16.384 MHz) Internal 8 kHz correction CS F0b (DPLL #2) speed-up region correction slow-down region tCS no-correction ...
Description CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL
CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL

File Size 246.12K  /  18 Page

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    Zarlink Semiconductor
Part No. ZL10100LDG1
OCR Text ... synthesizer designed for high comparison frequencies and low phase noise ? available in 28 pin ssop and mlp packages applications ? double conversion tuners ? digital terrestrial tuners ? cable modems ? cable telephony ?matv description t...
Description Single chip synthesized downconverter with IF amplifier.

File Size 403.57K  /  19 Page

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