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Integrated Device Technology, Inc.
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| Part No. |
79RC32V364100DAI 79RC32364 79RC32V364133DAI
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| OCR Text |
...ncy algorithm is uncached, non- coherent write-back, or non-coherent write-through no write-allocate.
4 of 21 june 20, 2000 79rc32364? *notice: the information in this document is subject to change without notice this allows the system a... |
| Description |
RISController Embedded 32-bit Microprocessor, based on RISCore32300 RISController嵌入32位的基础上RISCore32300微处理器
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| File Size |
362.53K /
21 Page |
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it Online |
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Broadcom
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| Part No. |
BCM1125H
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| OCR Text |
...edictors ? fast, on-chip memory-coherent bus (zbbus) ? connects the cpu, l2 cache, memory controller and i/o bridges ? runs at half the cpu core clock; 256 bits wide ? on-chip l2 cache ? 256 kb, shared by cpu and i/o bridges ? four-way asso... |
| Description |
High Performance MIPS Processor
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| File Size |
174.46K /
2 Page |
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it Online |
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Fujitsu Microelectronics
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| Part No. |
1394
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| OCR Text |
...1394 serial bus with a Scalable coherent Interface. Each bus bridge monitors the highest bus in the hierarchy to detect a transaction for a node on its bus. When a bridge receives a packet addressed to a node on its bus, it forwards the pac... |
| Description |
IEEE 1394 SERIAL BUS CONTROLLER
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| File Size |
87.65K /
30 Page |
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it Online |
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Analog Devices, Inc.
ANALOG DEVICES INC
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| Part No. |
AD6620S/PCB AD6620PCB AD6620AS
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| OCR Text |
... Each channel is processed with coherent frequency translation and output sample clocks. In addition, external synchronization pins are provided to facilitate coherent frequency translation and output sample clocks among several AD6620s. Th... |
| Description |
65 MSPS Digital Receive Signal Processor 65 MSPS的数字接收信号处理器
16 Characters x 1 Lines, 5x7 Dot Matrix Character and Cursor 65 MSPS的数字接收信号处理器
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| File Size |
363.84K /
43 Page |
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it Online |
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