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HYNIX SEMICONDUCTOR INC
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| Part No. |
HY5DU561622ELTP-L
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| OCR Text |
...tage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v +0.1v / -0.2v for ddr400 ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock ... |
| Description |
16M X 16 DDR DRAM, 0.75 ns, PDSO66
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| File Size |
235.08K /
29 Page |
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it Online |
Download Datasheet
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HYNIX SEMICONDUCTOR INC
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| Part No. |
HY5DU561622ELTP-JI
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| OCR Text |
...tage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v +0.1v / -0.2v for ddr400 ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock ... |
| Description |
16M X 16 DDR DRAM, 0.7 ns, PDSO66
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| File Size |
235.26K /
29 Page |
View
it Online |
Download Datasheet |
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NANYA TECHNOLOGY CORP
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| Part No. |
NT5DS16M16BS-6KL
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| OCR Text |
...riodic refresh interval 2.5v (sstl_2 compatible) i/o v ddq = 2.5v 0.2v v dd = 2.5v 0.2v available in 6k, 6kl and 75b speed sorts 6kl sort has idd6<=1.5ma available as lead-free and halogen-free products description the 25... |
| Description |
16M X 16 DDR DRAM, 0.7 ns, PDSO66
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| File Size |
2,290.92K /
80 Page |
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it Online |
Download Datasheet |
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HYNIX SEMICONDUCTOR INC
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| Part No. |
HY5DU28822LT-K
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| OCR Text |
...ge levels are compat- ible with sstl_2. mode register set options include the length of pipeline ( cas latency of 2 / 2.5), the number of consecutive read or write cycles initiated by a single control command (burst length of 2 / 4 / 8), t... |
| Description |
16M X 8 DDR DRAM, PDSO66
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| File Size |
84.91K /
10 Page |
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it Online |
Download Datasheet |
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Samsung Electronic
SAMSUNG[Samsung semiconductor]
SAMSUNG SEMICONDUCTOR CO. LTD.
Samsung Semiconductor Co., Ltd.
DiCon Fiberoptics, Inc.
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| Part No. |
K4D261638F-TC33 K4D261638F-TC25 K4D261638F-TC40 K4D261638F K4D261638F-TC50 K4D261638 K4D261638F-TC2A K4D261638F-TC36 K4D261638F-TC250 K4D261638F-LC250
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| OCR Text |
...ower supply for I/O interface * SSTL_2 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs -. Read latency 3, 4 and 5(clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) * All inputs e... |
| Description |
128Mbit GDDR SDRAM 128Mbit GDDR SDRAM内存
8M X 16 DDR DRAM, 0.55 ns, PDSO66 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
8M X 16 DDR DRAM, 0.55 ns, PDSO66 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
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| File Size |
223.53K /
18 Page |
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it Online |
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NANYA TECHNOLOGY CORP
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| Part No. |
NT5DS16M16BW-6K
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| OCR Text |
...riodic refresh interval ? 2.5v (sstl_2 compatible) i/o ? v ddq = 2.5v 0.2v ? v dd = 2.5v 0.2v ? -6k speed sort: supports pc2700/pc2100 modules ? -75b speed sort: supports pc2100 modules description the 256mb ddr sdram is a high-spe... |
| Description |
16M X 16 DDR DRAM, 0.7 ns, PBGA60
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| File Size |
1,341.90K /
80 Page |
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it Online |
Download Datasheet |
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Price and Availability
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