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ICST[Integrated Circuit Systems]
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| Part No. |
MK5814 MK5814STR MK5814S MK5814SLF MK5814SLFTR
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| OCR Text |
... table above. (default-internal mid-level). Function select 0 input. Selects spread amount and direction per table above. (default-internal ...capacitance. For example, a crystal with a 16 pF load capacitance uses two 20 pF [(16-6) x 2] capaci... |
| Description |
From old datasheet system
Low EMI Clock Generator
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| File Size |
97.38K /
7 Page |
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it Online |
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IDT
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| Part No. |
IDT5T2010 5T2010_DATASHEET
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| OCR Text |
... hard-wired to appropriate high-mid-low levels. The outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all th...CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN COUT Description Input Capacitance Output ... |
| Description |
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK?
From old datasheet system
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| File Size |
154.86K /
23 Page |
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it Online |
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IDT
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| Part No. |
IDT5T9950APFI IDT5T9950APFI8 IDT5T9950PFI IDT5T9950PFI8
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| OCR Text |
... hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is ...CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. ... |
| Description |
2.5V Programmable Skew PLL Clock Driver Turboclock II Jr.
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| File Size |
76.96K /
9 Page |
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it Online |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V995PFI IDT5V995 IDT5V995PFGI
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| OCR Text |
...e hardwired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0...CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. ... |
| Description |
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
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| File Size |
71.68K /
10 Page |
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it Online |
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IDT
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| Part No. |
IDT5V9950PFI8
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| OCR Text |
... hard-wired to appropriate high-mid-low levels. when the soe pin is held low, all the outputs are synchronously enabled. however, if soe ...capacitance applies to all inputs except test, fs, nf [1:0] , and ds [1:0] . capacitance (t a = +25... |
| Description |
3.3V Programmable Skew PLL Clock Driver Turboclock II Jr.
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| File Size |
66.00K /
9 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT5V925
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| OCR Text |
...der/mode select pins. float to mid. q [2:0] o output at n*clkin frequency q/n o programmable divide-by-n clock output oe i tri-state output...capacitance of 15pf. output used for allowable clkin range (mhz) (1,2) output frequency relationship... |
| Description |
Programmable Clock Generator
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| File Size |
50.32K /
7 Page |
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it Online |
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Price and Availability
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