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ALTERA
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Part No. |
EP20K100EQ EP20K100QC EP20K100EQC240-2
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OCR Text |
...T, stubseries terminated logic (sstl-3 and sstl-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I) - Pull-up on I/O pins before and during configuration Advanced interconnect structure - Four-level hie... |
Description |
Apex 20KE Device Family (1.8V, LVDS Apex 20K Device Family (2.5V)
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File Size |
585.74K /
116 Page |
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it Online |
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HYNIX SEMICONDUCTOR INC
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Part No. |
HY5DU56422BT-D43
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OCR Text |
...tage levels are compatible with sstl_2. features preliminary rev. 0.4 / aug. 2003 ... |
Description |
64M X 4 DDR DRAM, 0.7 ns, PDSO66
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File Size |
220.70K /
32 Page |
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it Online |
Download Datasheet
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NANYA TECHNOLOGY CORP
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Part No. |
NT512D64SH8B0GN-75B
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OCR Text |
...ions inputs and outputs are sstl-2 compatible v dd = v ddq = 2.5v 0.2v sdrams have 4 internal banks for concurrent operation differential clock inputs data is read or written on both clock edges dram dll aligns dq ... |
Description |
64M X 64 DDR DRAM MODULE, 0.75 ns, DMA200
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File Size |
508.34K /
18 Page |
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it Online |
Download Datasheet
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Price and Availability
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