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reset--hold Datasheet PDF File

For reset--hold Found Datasheets File :: 21228 Search Time::2.406ms
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				TIANMA
Part No.	TM9632ACIWG TM9632ACIWGSPEC
OCR Text	...l description 1 resetb h/l reset signal input 2 cs1b h/l chip select input 3 rs h/l selects registers input 4 vdd 3.0v pow...hold time rs t ass t ahs 90 360 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 90 9...
Description	LCD_Module
File Size	313.64K / 22 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74HCT299 74HC299PW 74HC299 74HC299D 74HC299DB 74HC299N 74HCT299D 74HCT299DB 74HCT299N 74HCT299PW
OCR Text	...gnal on the asynchronous master reset input (MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes a...hold times, relative to the rising edge of CP, are observed. A HIGH signal on the 3-state output ena...
Description	8-bit universal shift register; 3-state 8-bit universal shift register 3-state
File Size	85.22K / 11 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V. PHILIPS[Philips Semiconductors]
Part No.	74HCT4510 74HC4510 74HC4510PW 74HC4510D 74HC4510DB 74HC4510N 74HCT4510D 74HCT4510DB 74HCT4510N 74HCT4510PW
OCR Text	... overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all ot...hold time CE to CP hold time Dn to PL hold time UP/DN to CP 80 16 14 80 16 14 100 20 17 100 20 17 10...
Description	Quadruple D-Type Flip-Flops With Clear 16-TSSOP -40 to 85 BCD up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16 BCD up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16 BCD up/down counter BCD码向向下计数
File Size	97.72K / 12 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V. PHILIPS[Philips Semiconductors]
Part No.	74HCT4516 74HC4516 74HC4516N 74HC4516D 74HC4516DB 74HCT4516D 74HCT4516DB 74HCT4516N
OCR Text	... overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all ot...hold time CE to CP hold time Dn to PL hold time UP/DN to CP 80 16 14 80 16 14 100 20 17 100 20 17 10...
Description	Binary up/down counter HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16
File Size	95.51K / 14 Page	View it Online	Download Datasheet

				QuickLogic, Corp.
Part No.	QL3060-0PB456C QL3060-1PB456M QL3060-1PB456C QL3060-2PB456C QL3060-4PB456C QL3060-4PQ208C QL3060-1PQ208I
OCR Text	... cell flip-flop clock, set and reset inputs ? each driven by an input-only pin six global clock/control networks available to the logic...hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 ...
Description	60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. FPGA\|1584-CELL\|CMOS\|QFP\|208PIN\|PLASTIC FPGA的\| 1584细胞\|的CMOS \| QFP封装\| 208PIN \|塑料 FPGA\|1584-CELL\|CMOS\|BGA\|456PIN\|PLASTIC
File Size	212.99K / 19 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	74LS174 SN74LS174 SN74LS174D SN74LS174N ON2855 SN74LS174-D
OCR Text	...sition. The device has a Master Reset to simultaneously clear all flip-flops. The LS174 is fabricated with the Schottky barrier diode proces...Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions ...
Description	Hex D Flip-Flop LOW POWER SCHOTTKY From old datasheet system
File Size	104.95K / 8 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	74LS175 SN74LS175D SN74LS175N ON2857 SN74LS175 SN74LS175-D
OCR Text	...lip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated w...Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions ...
Description	From old datasheet system LOW POWER SCHOTTKY Quad D Flip-Flop
File Size	108.45K / 8 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V.
Part No.	PCU9661B
OCR Text	...hannel buffer ? three levels of reset: software channel rese t, global software reset on parallel bus, global hardware reset pin ? communi...hold low (v ss ). tms 14 i jtag test mode select input. for normal operation, hold high (v dd ). t...
Description	Parallel bus to 1 channel UFm I2C-bus controller
File Size	326.43K / 52 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9804-15
OCR Text	...le sampler (cds) allowable ccd reset transient 1 max input range before saturation 1 max ccd black pixel amplitude 1 500 1.0 100 mv ...hold time t h 6.0 7.6 ns pipeline delay 9 cycles serial interface maximum sck frequency f ...
Description	Complete 10-Bit 18 MSPS CCD Signal Processor
File Size	107.10K / 8 Page	View it Online	Download Datasheet

For reset--hold Found Datasheets File :: 21228 Search Time::2.406ms
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