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MOSEL-VITELIC
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Part No. |
V827332K04SATG-A0
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OCR Text |
...sh all inputs, outputs are sstl-2 compatible 4096 refresh cycles every 64 ms serial present detect (spd) ddr sdram performance description the v827332k04satg memory module is organized 33,554,432 x 72 bits in a 184 ... |
Description |
32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
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File Size |
370.21K /
14 Page |
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Part No. |
PROMOSTECHNOLOGIESINC-V827464N24SCJX-D3
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OCR Text |
...efresh all inputs, outputs are sstl-2 compatible 8192 refresh cycles every 64 ms serial presence detect (spd) ddr sdram performance description the v827464n24sc memory module is organized 67,108,864 x 72 bits in a 184 pin memory module... |
Description |
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File Size |
325.06K /
17 Page |
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hitachi
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Part No. |
HM5216808CSERIES 5216808C
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OCR Text |
sstl-3) 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (sstl-3)
ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996
Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series,... |
Description |
1,048,576-word ′ 8-bit ′ 2-bank Synchronous Dynamic RAM
(sstl-3)
2,097,152-word ′ 4-bit ′ 2-bank Synchronous Dynamic RAM
(sstl-3) From old datasheet system
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File Size |
578.59K /
51 Page |
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it Online |
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Part No. |
MT5HTF3272KY-40EXX
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OCR Text |
....6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? single rank ? multiple internal device banks for concurrent operation ? supports duplicate output strobe (r... |
Description |
32M X 72 DDR DRAM MODULE, 0.9 ns, ZMA244
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File Size |
245.56K /
15 Page |
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it Online |
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Part No. |
K4D553235F-GC220
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OCR Text |
...er supply for i/o interface ? sstl_18 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 4, 5 and 6 (clock) -. burst length (2, 4 and 8) -. burst type (sequential & inter... |
Description |
8M X 32 DDR DRAM, 0.45 ns, PBGA144
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File Size |
316.09K /
18 Page |
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it Online |
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