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![ICS85408 ICS85408BG ICS85408BGLF ICS85408BGLFT ICS85408BGT](Maker_logo/integrated_circuit_systems.GIF)
ICS Integrated Circuit Systems
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Part No. |
ICS85408 ICS85408BG ICS85408BGLF ICS85408BGLFT ICS85408BGT
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OCR Text |
...wing differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks * Translates any singl... |
Description |
Low Skew, 1-to-8, Differential-to-LVDS Fanout Buffer LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
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File Size |
168.14K /
12 Page |
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ICS
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Part No. |
M2006-03
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OCR Text |
... output clocks are differential LVPECL compatible Two downstream clocks, frequency-selectable One upstream clock, frequency-selectable RE...to within 1nsec of selected input reference rising edge (unless M2_SEL= 1) Output duty cycle 47-53%... |
Description |
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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File Size |
223.26K /
6 Page |
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ICS
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Part No. |
M2006-04
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OCR Text |
... reference inputs support LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Power-up frequency translation ratio of x32 useful for 19.44M...to +3.3V. Clock output pairs. Differential LVPECL. P Divider control. LVCMOS/LVTTL. For P1: Logic 1 ... |
Description |
VCSO Frequency Translator
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File Size |
300.56K /
12 Page |
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ICS
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Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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OCR Text |
... reference inputs support LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequenc...to +3.3V. Clock output pairs. Differential LVPECL. P Divider control. LVCMOS/LVTTL. For P1: Logic 1 ... |
Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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File Size |
312.67K /
14 Page |
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Integrated Circuit System
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Part No. |
M2006-12
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OCR Text |
...lock output pairs. Differential LVPECL. P Divider controls. LVCMOS/LVTTL. (For P0_SEL, P1_SEL, see Table 5 on pg. 3. Reference clock input p...to these pins can cause erratic device operation.
Table 2: Pin Descriptions
Input Input
Inter... |
Description |
VCSO BASED FEC CLOCK PLL
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File Size |
262.41K /
8 Page |
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Fairchild
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Part No. |
FIN1101
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OCR Text |
...uencies. It can directly accept LVPECL, HSTL, and SSTL-2 for translating directly to LVDS.
Features
s Greater than 800 Mbps full differential path s 3.5 ps max random jitter and 135 ps max deterministic jitter s 3.3V power supply operat... |
Description |
LVDS Single Port High Speed Repeater
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File Size |
251.13K /
6 Page |
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ICS
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Part No. |
ICS83023I
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OCR Text |
...ifferential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 350MHz (typical) * Output skew: 60ps (maximum) * Part-to-part skew: 500ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V operating supply... |
Description |
Dual 1-to-1, Differential-to-LVCMOS Translator/Buffer. Industrial Temperature.
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File Size |
68.81K /
12 Page |
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ICST[Integrated Circuit Systems]
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Part No. |
ICS843004-01 ICS843004AG-01T ICS843004A01 ICS843004AG-01
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OCR Text |
LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Four 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended in...to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843004-01 is a 4 output LVPECL s... |
Description |
FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
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File Size |
213.16K /
15 Page |
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Price and Availability
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