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IBM Microeletronics
International Business Machines, Corp.
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| Part No. |
IBM0418A80QLAB IBM0418A40QLAB
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| OCR Text |
256kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
* 256K x 36 or 512K x 18 Organizations * 128K x 36 or 256K x 18 Organizations * 0.25 Micron CMOS Technology * Synchronous Flow Thru Mode of Operation with Self-Timed Late Write * Differe... |
| Description |
8Mb( 512K x 18 ) SRAM(8Mb( 512K x 18 )同步CMOS静态RAM)
4Mb( 256K x 18 ) SRAM(4Mb( 256K x 18 )同步CMOS静态RAM) 4Mb的（256 × 18）的SRAMMb的（256 × 18）同步的CMOS静态RAM）的
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| File Size |
26.41K /
5 Page |
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Cypress
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| Part No. |
CY7C1354V25 CY7C1356V25 7C1354V
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| OCR Text |
256kx36/512Kx18 Pipelined SRAM with NoBLTM Architecture
Features
* Pin compatible and functionally equivalent to ZBTTM * Supports 200-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self-timed o... |
| Description |
256kx36/512Kx18 Pipelined SRAM with NoBL Architecture
From old datasheet system
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| File Size |
339.06K /
26 Page |
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Cypress
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| Part No. |
CY7C1302V25 7C1302V25
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| OCR Text |
...rnally, the device is organized 256kx36. Therefore, only 18 address inputs are needed to access the entire memory array.These inputs are ignored when the appropriate port is deselected. Therefore, on the rising edge of the positive input cl... |
| Description |
9-Mb Pipelined SRAM with QDR?Architecture
From old datasheet system
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| File Size |
249.54K /
23 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1355V25 CY7C1357V25 7C1355V
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| OCR Text |
256kx36/512Kx18 Flow-Thru SRAM with NoBLTM Architecture
Features
* Pin compatible and functionally equivalent to ZBTTM devices * Supports 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self... |
| Description |
256kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture
From old datasheet system
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| File Size |
334.51K /
26 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1303BV25-100BZXC CY7C1306BV25-100BZXC
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| OCR Text |
...ster
18
A(17:0)
K K
256kx36 Memory Array
256kx36 Memory Array
CLK Gen.
Control Logic
RPS C C
Read Data Reg. 72 Vref WPS BWS0 BWS1 BWS2 BWS3 Control Logic 36 Reg. 36 Reg. 36
Reg. 36
36 Q[35:0]
Selection Gu... |
| Description |
18-Mbit Burst of 2 Pipelined SRAM with QD(TM) Architecture
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| File Size |
246.26K /
19 Page |
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it Online |
Download Datasheet |
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Price and Availability
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