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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
9DB233AGILFT 9DB233AGLFT
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| OCR Text |
...ower distribution table vdd gnd 5,9,12,16 6,15 differential outputs 9 6 smbus 20 19 iref 20 19 analog vdd & gnd for pll core description pin...pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 5 vdd pwr power ... |
| Description |
9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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| File Size |
165.83K /
14 Page |
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| Part No. |
CY2SSTU877BVXC-32T
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| OCR Text |
...nit v in input voltage range ?0.5 v ddq + 0.5 v v out output voltage range ?0.5 v ddq + 0.5 v t s storage temperature ?65 150 c v cc, av cc supply voltage range ?0.5 2.5 v i ik input clamp current ?50 50 ma i ok output clamp current ?... |
| Description |
SSTU SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
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| File Size |
127.85K /
8 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
8741004BGILF
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| OCR Text |
...004i can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100mhz input/125mhz output) using the f_sel pins. the ics8741004i uses idt?...pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sst... |
| Description |
8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
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| File Size |
699.23K /
22 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
8741004AGLF
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| OCR Text |
...1004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100mhz input/125mhz output) using the f_sel pins. the ics8741004 uses idt?s...pair ? clk, clk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sst... |
| Description |
8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
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| File Size |
707.88K /
19 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
ICS85314BMI-01T
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| OCR Text |
5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer g eneral d escription the ics85314i-01 is a low skew, high perfor- mance 1-to-5 dif...pair can accept most standard differential input levels. the single-ended clk1 can accept lvcmos or ... |
| Description |
85314 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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| File Size |
235.71K /
19 Page |
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it Online |
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Integrated Circuit Syst...
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| Part No. |
ICS1892Y-14LF ICS1892
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| OCR Text |
...ed features ? supports category 5 cables with attenuation in excess of 24 db at 100 mhz across a temperature range from -5 to +85 c ...pair (utp) category 5 cable with attenuation in excess of 24 db at 100 mhz. with this ics-patented t... |
| Description |
10Base-T/100Base-TX Integrated PHYceiver
1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP64
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| File Size |
803.42K /
148 Page |
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it Online |
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Price and Availability
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